hmc1035lp6ge - radiant.suradiant.su/other/hittite/pdf/hmc1035lp6g.pdf · the differential output of...

For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824Phone 978-250-3343 Fax 978-250-3373 Order On-line at wwwhittitecom

Application Support Phone 978-250-3343 or appshittitecom

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HMC1035LP6GEv010712

HigH Performance +33 V clock generator 25 - 2500 mHz

functional Diagram

features

33 V only single supply rail operation

output Frequency range 25 MHz - 2500 MHz

Integer or Fractional-n mode Frequency translation

Configurable lVDs-compatible or lVPeCl type Differential outputs

ldquoPower Priorityrdquo andldquoPerformance Priorityrdquo modes

97 fs rMs Jitter Generation (12 kHz - 20 MHz 2500 MHz typ)

-163 dBcHz Phase noise Floor to Improve aDCDaC snr (maximum output swing levels)

adjustable Pll loop BW via external Filter

output DisableMute Control

lock Detect signal

exact Frequency Mode to achieve reference frequency tuning and 0 Hz frequency error

40 lead 6x6 mm sMt Package 36 mm2

typical applications

bull 10G40G100G optical Modules transponders line Cards

bull otn and sonetsDH applications

bull Data Converters sample Clock Generation

bull Cellular4G Infrastructure

bull High Frequency ProcessorFPGa Clocks

bull any Frequency Clock rate Generation

bull low Jitter saW oscillator replacement

bull DDs replacement

bull Frequency translation

bull Frequency Margining



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HMC1035LP6GEv010712


general Description

the HMC1035lP6Ge is a low-noise wide-band 33 V clock generator IC with a fractional-n Phase locked loop (Pll) that features an integrated Voltage Controlled oscillator (VCo) the device provides differential clock outputs between 25 MHz and 2500 MHz range the HMC1035lP6Ge features a low noise Phase Detector (PD) and Delta-sigma modulator capable of operating at up to 100 MHz which permits wider loop-bandwidths and excellent spurious performance

the HMC1035lP6Ge features industry leading phase noise and jitter performance across the operating range that enable it to improve link level jitter performance Bit-error-rates (Ber) and eye diagram metrics the superior noise floor (lt-162 dBcHz) makes the HMC1035lP6Ge an ideal source for a variety of applications ndashsuch as clock references for high speed data converters physical layer devices (PHY) serializerdeserializer (serDes) circuits FPGas and processors the HMC1035lP6Ge can also be used as an lo for 10G40G100G optical modules and transponders as well as primary reference clock for 10G40G100G line cards and for jitter attenuation and frequency translation

the differential output of the HMC1035lP6Ge can be set to either external termination which could be used for lVPeCl operation or Internal termination for operation in an lVDs compatible mode or lVPeCl see Figure 18 additionally an ouput swing adjustment makes the device flexible and compatible with a wide variety of signal level requirements the output can be internally terminated to reduce component count and cost or could be terminated externally using standard lVPeCl termination methods such as Figure 21 an output Mute function allows the user to shut off the outputs such as may be required for board testing or debugging the lVPeCllVDs amplitude select and output Mute function are all programmed sPI serial programming

the HMC1035lP6Ge is designed to select between a Power Priority or a Performance Priority mode the Power Priority setting reduces the current consumption of the part whereas the Performance Priority setting improves the Jitter and Phase noise performance

the 24 bit Delta-sigma Modulator further enhances Hittitersquos exact Frequency Mode which enables users to generate output frequencies with 0 Hz frequency error in many applications



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HMC1035LP6GEv010712


electrical Specifications VPPcP VDDlS 3VrVDD Vcc1 Vcc2 VccHf VccPS VccPD = 33V min amp max Specified across temperature -40 degc to 85 degc

Parameter Condition Min typ Max Units

OUT_N OUT_P Output Characteristicsoutput Frequency 25 2500 MHz

Differential output amplitude

Gain setting = 0000 690 mVpp












output Common Mode Voltage

lVDs Mode 12 mV

lVPeCl Mode 20 V

output rise and Fall time lVDs mode Gain = 0001 120 ps

output rise and Fall time lVPeCl mode Gain = 0110 130 ps

Duty CycleaC coupled measured at the 0 V crossing 622080 MHz and

25 GHz outputs49 50 51

VCO Output DividerVCo rF Divider range 1246862 1 62

PLL RF Divider Characteristics19-Bit n-Divider range (Integer) Max = 219 - 1 16 524287

19-Bit n-Divider range (Fractional)Fractional nominal Divide ratio Varies (-3 +4) Dynamically Max

20 524283

CLKIN Input CharacteristicsMax Input Frequency2 350 MHz

Input amplitude aC Coupled [1] 02 33 Vp-p

Input Capacitance 5 pF

Input slew rate 157 mVns

14 Bit r-Divider range 16383

Phase Detector (PD) [2]

PD Frequency Fractional Mode 0006 100 MHz

PD Frequency Integer Mode 0006 100 MHz

Charge Pumpoutput Current 002 254 ma

Charge Pump Gain step size 20 microa

PDCharge Pump ssB Phase noise 50 MHz ref Input referred

1 kHz -143 dBcHz

10 kHz add 1 dB for Fractional -150 dBcHz


Logic Inputs

Vswswitching threshold for logic

levels40 50 60 DVDD

Logic OutputsVoH output High Voltage DVDD V

Vol output low Voltage 0 V

output Impedance 100 200 Ω

Maximum load Current 15 ma



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HMC1035LP6GEv010712



Power Supply Voltages

+ 33V supplies

aVDD VPPCP VDDls3VrVDD DVDD3V

VCC1 VCC2 VCCHF VCCPs VCCPD

315 33 35 V

Power Supply Currents

+33V

lVPeCl Performance Priority Mode 25 GHz output

excluding load186 ma

lVPeCl Performance Prior-ity Mode 25 GHz output

Includes termination218 ma

lVPeCl Performance Priority Mode 622080 MHz output


lVDs Power Priority Mode 25 GHz output Includes

termination173 ma

lVDs Power Priority Mode 622080 MHz output Includes

termination221 ma

Power Down - Crystal offreg 01h=0

Crystal not Clocked10 microa

Power Down - Crystal on 100 MHzreg 01h=0

Crystal Clocked 100 MHz5 ma

Power on Resettypical reset Voltage on DVDD 700 mV

Minimum DVDD Voltage for no reset 15 V

Power on reset Delay 250 micros

Figure of MeritFloor Integer Mode normalized to 1 Hz -227 dBcHz

Floor Fractional Mode normalized to 1 Hz -226 dBcHz

Flicker (Both Modes) normalized to 1 Hz -268 dBcHz

Phase Jitter rMs Integer Mode

62208 MHz output 12 kHz to 20 MHz

107 fs

25 GHz output12 kHz -20MHz

97 fs

Phase Jitter rMs Fractional Mode


125 fs


110 fs

[1] Measurements made are aC coupled into a 100 differential load (except Phase noise)[2] the maximum phase detector frequency can only be achieved if the minumum n value is respected eg in the case of fractional feedback mode the maximum PFD rate = fvco20 or 100 MHz whichever is less operation gt 70MHz may require offsett currents to be disabled and reenabled

electrical Specifications (Continued)



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HMC1035LP6GEv010712


[1] the Pn plot is measured with a 100MHz oCXo followed with a divide by 2 using the loop Filter in the loop Filter Configuration table [2] the Pn plot is measured with 50 MHz Crystal oscillator (red) versus a 50MHz oCXo (blue)[3] Jitter is Integrated over a 12kHz to 20MHz Band

-180

-170

-160

-150

-140

-130

-120

-110

-100

1 10 100 1000 10000 100000

625 MHz_LVDS

625 MHz_LVPECL

2500 MHz_LVDS

2500 MHz_LVPECL

OFFSET(KHz)

PH

AS

E N

OIS

E(d

BcH

z)

-180

-170

-160

-150

-140

-130

-120

-110

-100

1 10 100 1000 10000 100000

625 MHz_LVDS

625 MHz_LVPECL

2500 MHz_LVDS

2500 MHz_LVPECL

OFFSET(KHz)

PH

AS

E N

OIS

E(d

BcH

z)

-180

-170

-160

-150

-140

-130

-120

-110

-100

1 10 100 1000 10000 100000

62208 MHz_LVDS62208 MHz_LVPECL2500 MHz_LVDS2500 MHz_LVPECL

OFFSET(KHz)

PH

AS

E N

OIS

E(d

BcH

z)

-180

-170

-160

-150

-140

-130

-120

-110

-100

1 10 100 1000 10000 100000

62208 MHz_LVDS

62208 MHz_LVPECL

2500 MHz_LVDS

2500 MHz_LVPECL

OFFSET(KHz)

PH

AS

E N

OIS

E(d

BcH

z)

40

60

80

100

120

140

160

LVDS_PWR_PRI

LVDS_PERF_PRI

LVPECL_PWR_PRI

LVPECL_PWR_PRI

INT

EG

RA

TE

D R

MS

JIT

TE

R (

fs)

625

FREQUENCY (MHz)

2500

-180

-160

-140

-120

-100

-80

1 10 100 1000 10000 100000

XO

OCXO

OFFSET(KHz)

PH

AS

E N

OIS

E(d

BcH

z)

figure 1 typical Phase noise integer mode Power Priority[1]

figure 2 typical Phase noise integer mode Performance Priority[1]

figure 3 typical Phase noise fractional mode Power Priority[1]

figure 4 typical Phase noise fractional mode Performance Priority[1]

figure 5 integer Phase noise vs reference Source[2]

figure 6 Jitter from integrated Phase noise vs output frequency integer mode[2]



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HMC1035LP6GEv010712


-200

-150

-100

-50

0

50

100

150

200

-50 0 50 100 150 200 250 300

TIME( (uS)

PH

AS

E E

RR

OR

(D

EG

RE

E)

200

400

600

800

1000

1200

1400

100 1000

LVDS_PWR_PRI

LVDS_PERF_PRI

LVPECL_PWR_PRI

LVPECL_PERF_PRI

FRQUENCY (MHz)

Vp

pd

(m

V)

3000

[4] the HMC1035lP6Ge has a preloaded register file for a 2GHz output and time is measured from VCo disable to VCo enable using the loop Filter in the loop Filter Configuration table [5] the output signal amplitude is measured with HMC1035 aC coupled to a 100 ohm differntial loadinstrument [6] Measured at 20 to 80 levels

40

60

80

100

120

140

160

LVDS_PWR_PRI

LVDS_PERF_PRI

LVPECL_PWR_PRI

LVPECL_PWR_PRI

INT

EG

RA

TE

D R

MS

JIT

TE

R (

fs)

250062208

FREQUENCY (MHz)

-50 0 50 100 150 200 250 300

TIME( (uS)

FR

EQ

UE

NC

Y E

RR

OR

(H

z)

2 109

60

80

100

120

140

160

LVDS_PWR_PRILVDS_PERF_PRILVPECL_PWR_PRILVPECL_PERF_PRI

RIS

E T

IME

(p

s)

250062208

FREQUENCY (MHz)

60

80

100

120

140

160


FA

LL

TIM

E (

ps)

250062208

FREQUENCY (MHz)

figure 7 Jitter from integrated Phase noise vs frequency fractional mode[3]

figure 8 lock time vs Phase error[4]

figure 9 lock time vs frequency error[4] figure 10 output amplitude vs output frequency[5]

figure 11 output rise time vs output frequency[6]

figure 12 output fall time vs output frequency



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HMC1035LP6GEv010712


loop Filter BW (kHz)

C1 (pF)

C2 (nF)

C3 (pF)

C4 (pF)

r2 (Ω)

r3 (Ω)

r4 (Ω)

loop Filter Design

127 390 10 82 82 750 300 300

75 270 27 200 390 430 390 390

loop filter configuration table

100

120

140

160

180

200

220

LVDSLOWILVDSLOWNLVPECLLOWILVPECLLOWN

IDD(m

A)

Fo16 Fo4Fo8 FoFo2

FREQUENCY

[7] Duty Cycle is measured with the output aC coupled at the 0 crossing level[8] the current is measured at nominal VCo VDD supply under Fractional locked Condition by varying different the output divider ratio

47

48

49

50

51

52

LVDS_PWR_PRI

LVDS_PERF_PRI

LVPECL_PWR_PRI

LVPECL_PERF_PRI

DU

TY

CY

CL

E (

)

250062208

FREQUENCY (MHz)

-1500

-1000

-500

0

500

1000

1500

0 05 1 15 2 25 3

LVDS PERF PRI

LVDS PWR PRI

LVPECL PERF PRI

LVPECL PWR PRI

TIME (ns)

Vp

pd

(m

V)

figure 13 output Duty cycle vs output frequency[7]

figure 14 Supply current vs output frequency[8]

figure 15 output amplitude vs gain Setting over temperature

figure 16 out Waveform Performance Priority and Power Priority in lVDS and lVPecl mode

500

1000

1500

2000

2500

3000

0 2 4 6 8 10

Vp

pd

(m

V)

27C

-40C

85C

GAIN SETTING STEP



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HMC1035LP6GEv010712


outline Drawing

notes

1 PaCkaGe BoDY MaterIal loW stress InJeCtIon MolDeD PlastIC sIlICa anD

sIlICon IMPreGnateD

2 leaD anD GroUnD PaDDle MaterIal CoPPer alloY

3 leaD anD GroUnD PaDDle PlatInG 100 Matte tIn

4 DIMensIons are In InCHes [MIllIMeters]

5 leaD sPaCInG toleranCe Is non-CUMUlatIVe

6 PaD BUrr lenGtH sHall Be 015mm MaX PaD BUrr HeIGHt sHall Be 025mm MaX

7 PaCkaGe WarP sHall not eXCeeD 005mm

8 all GroUnD leaDs anD GroUnD PaDDle MUst Be solDereD to PCB rF GroUnD

9 reFer to HIttIte aPPlICatIon note For sUGGesteD PCB lanD Pattern

absolute maximum ratingsaVDD VPPCP VDDls 3VrVDD DVDD3V VCC1 VCC2 VCCHF VCCPs VCCPD

-03V to +36V

operating temperature -40degC to +85degC

storage temperature -65degC to 150degC

Maximum Junction temperature 125 degC

thermal resistance (rtH) (junction to ground paddle)

10 degCW

reflow soldering

Peak temperature 260degC

time at Peak temperature 40 sec

esD sensitivity (HBM) Class 1B

stresses above those listed under absolute Maximum ratings may cause permanent damage to the device this is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied exposure to absolute maximum rating conditions for extended periods may affect device reliability

Part number Package Body Material lead Finish Msl rating Package Marking [1]

HMC1035lP6Ge roHs-compliant low stress Injection Molded Plastic 100 matte sn Msl1H1035XXXX

[1] 4-Digit lot number XXXX

Package information



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HMC1035LP6GEv010712


Pin Descriptions

Pin number Function Description

1 aVDD 33 VDC Power supply for analog Circuitry

2 5 6 8 9 11 - 14 18 - 22 24

26 34 37 38nC

the pins are not connected internally however all data shown herein was measured with these pins connected to rFDC ground externally

3 VPPCP 33V Power supply for Charge Pump analog section

4 CP Charge Pump output

7 VDDls 33V Power supply for the Charge Pump Digital section

10 3VrVDD reference supply

15 XreFP reference oscillator Input

16 DVDD3V 33V DC Power supply for Digital (CMos) Circuitry

17 Cen Chip enable Connect to logic high for normal operation

23 VtUne VCo Varactor tuning Port Input

25 VCC2 33V VCo analog supply 2


28 oUt_n negative output signal (Differential)

29 oUt_P Positive output signal (Differential)

30 sen Pll serial Port enable (CMos) logic Input

31 sDI Pll serial Port Data (CMos) logic Input

32 sCk Pll serial Port Clock (CMos) logic Input

33 lDsDo lock Detect or serial Data or General Purpose (CMos) logic output (GPo)

35 VCCHF 33 V DC Power supply for analog Circuitry

36 VCCPs 33 V DC Power supply for analog Prescaler

39 VCCPD 33 V DC Power supply for Phase Detector

40 BIas

external bypass decoupling for precision bias circuits note 1920V plusmn20mV reference voltage (BIas) is generated internally and cannot

drive an external load Must be measured with 10GΩ meter such as agilent 34410a normal 10MΩ DVM will read erroneously



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HMC1035LP6GEv010712


evaluation PcB Schematic

the circuit board used in the application should use rF circuit design techniques signal lines should have 50 ohm impedance while the package ground leads and exposed paddle should be connected directly to the ground plane similar to that shown a sufficient number of via holes should be used to connect the top and bottom ground planes the evaluation circuit board shown is available from Hittite upon request

the HMC1035 evaluation board and associated software offers the user an easy way to quickly evaluate the performance and flexibility of the HMC1035 the evaluation board operates off a +5V supply and includes an HMC1060 lDo which generates a low noise 33V source and a precision Pll which generates a 50MHz clock which is locked to an externally supplied 10 MHz reference

the Pll design is an HMC1031 phasefrequency detector passive loop filter and a low noise 50 MHz VCXo the Pll is normally or default upon shipping set to lock on to a 10 MHz reference feed into ldquoreF Inrdquo a 5MHz input reference can be used if D1 D0 is reconfigured to ldquo11rdquo or 50 MHz if D1 D0 is reconfigured to ldquo01rdquo the ldquoreF Inrdquo would normally have a +-50 ppm tolerance which falls within the VCXo pull range although not recommended the HMC1035 eB can be operated without supplying an external reference and the Pll will pull the VCXo to about 49992 MHz or 180 ppm low alternatively an external 50 MHz reference can be feed into the HMC1035 evaluation board which requires removing C44C35 r32 and J6 the tPlltCXo and placing a 0 ohm resistor in the r20 and r36 locations

To view this evaluation PCB schematic please visit wwwhittitecom and choose HMC1035LP6GE from the ldquoSearch by Part Numberrdquo pull down menu to view the product splash page

evaluation PcB

Item Contents Part number

evaluation PCB only HMC1035lP6Ge evaluation PCB eVal01-HMC1035lP6Ge

evaluation kit

HMC1035lP6Ge evaluation PCBUsB Interface Board6rsquo UsB a Male to UsB B Female CableCD roM (Contains User Manual evaluation PCB schematic evaluation software Hittite Pll Design software)

ekIt01-HMC1035lP6Ge

evaluation order information

eVal01-HMC1035lP6G

ekIt01-HMC1035lP6G

HMC1035lP6G evaluation PCB




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HMC1035LP6GEv010712


Hmc1035lP6ge input Stagea representative schematic for the HMC1035lP6Ge output stage is given in Figure 17 below the buffer is internally DC biased with 100 ohm internal termination For 50 ohm match an external 100 ohm resistor to ground should be added followed by an aC coupling capacitor (impedance lt 1 ohm) then to the XreFP pin of the part

Hmc1035lP6ge output Stagea representative schematic for the HMC1035lP6Ge output stage is given in Figure 18 below the output is derived from an emitter which can be internally biased to a current source (the default setting) or the Internal termination switch can be opened VCo_reg03[4] and external termination used the internal bias would be used when lVDs levels are required and the load would normally be a 100 differential load as shown in Figure 19 With the internal bias set the HMC1035lP6Ge output can also be used to drive 50 ohm single ended loads see Figures 19 and 20 this would simplify lVPeCl designs and reduce component cost

Figure 17 Input Stage

Figure 18 Output Stage

Figure 19 AC Coupling into 100 Ohm Differential Load

Figure 20 AC Coupling into a 50 Ohm Load



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HMC1035LP6GEv010712


alternatively the user can disable the internal bias VCo_reg 03h[4]=0 and use a standard lVPeCl termination scheme one of the most common methods is shown in Figure 21 with the resistors being located near the receiver aC coupling can be used after the DC biasing resistor network

the outputs can either be DC or aC coupled and the loads may be internal to the receiver or aDC etc - consult the manufacture for internal biasing and loading requirements selecting the aC coupling capacitors is a balance between impedance loading and rise and fall time versus signal loss and DC level drooping during the logic high and logic low levels - a low value such as 10 pF can be used for high frequency signals in the GHz range to ensure optimized rise and fall times while a 100 nF capacitor can be used to insure low loss and minimal DC drooping when the output is a low value such as 25 MHz

Waveform Diagramssee Figure 22 which shows the definition for rise and fall time as well as VCM and VaMP Figure 23 shows the Duty Cycle which is defined as (on timePeriod) were on time is positive goinglogic high level Measurements are made using the Internal Bias setting

Figure 22 Rise and Fall Time VCM VAMP

Figure 23 Duty Cycle

Figure 21 LVPECL Termination



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HMC1035LP6GEv010712


11 Serial Port

111 Serial Port modes of operationthe HMC1035lP6Ge serial port interface can operate in two different modes of operation

a HMCsPI HMC Mode (HMC legacy Mode) - single slave per HMCsPI Bus

b HMCsPI open Mode - Up to 8 slaves per HMCsPI Bus

Both Modes support 5-bits of register address space HMC Mode can support up to 6 bits of register address

register 0 has a dedicated function in each mode open Mode allows wider compatibility with other manufacturers sPI protocols

register 0 comparison - Single vs multi-User modesSingle UserHMC Mode

Multi-UserOpen Mode

reaDChip ID24-bits

Chip ID 24-bits

WRITEsoft reset

General strobes

read address [40]soft reset [5]

General strobes [236]

112 HmcSPi Protocol Decision after Power-on reseton power up both types of modes are active and listening

a decision to select the desired sPI protocol is made on the first occurrence of sen or sClk following a hard reset after which the protocol is fixed and only changeable by cycling the power oFF and on

a If a rising edge on sen is detected first HMC Mode is selectedb If a rising edge on sClk is detected first open mode is selected

113 Serial Port Hmc mode - Single PllHMC Mode (legacy Mode) serial port operation can only address and talk to a single Pll and is compatible with most Hittite Plls and Plls with Integrated VCos

the HMC Mode protocol shown in Figure 24 and Figure 25 is designed for a 4 wire interface with a fixed protocol featuring

a 1 readWrite bitb 6 address bitsc 24 data bitsd 3 wire for Write only 4 wire for readWrite capability



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HMC1035LP6GEv010712


1131 Hmc mode - Serial Port Write operationaVDD = DVDD = 33V plusmn5 aGnD = DGnD = 0V

SPi Hmc mode - Write timing characteristicsParameter Conditions Min Typ Max Units

t1 sen to sClk setup time 8 ns

t2 sDI to sClk setup time 3 ns

t3 sClk to sDI hold time 3 ns

t4 sen low duration 20 ns

t5 sCk to sen fall 10 ns

Max serial port Clock speed 50 MHz

a typical HMC Mode WrIte cycle is shown in Figre 24

a the Master (host) both asserts sen (serial Port enable) and clears sDI to indicate a WrIte cycle followed by a rising edge of sCk

b the slave (synthesizer) reads sDI on the 1st rising edge of sCk after sen sDI low indi cates a Write cycle (Wr)

c Host places the six address bits on the next six falling edges of sCk MsB firstd slave shifts the address bits in the next six rising edges of sCk (2-7)e Host places the 24 data bits on the next 24 falling edges of sCk MsB firstf slave shifts the data bits on the next 24 rising edges of sCk (8-31)g the data is registered into the chip on the 32nd rising edge of sCkh sen is cleared after a minimum delay of t5 this completes the write cycle

Figure 24 HMC Mode - Serial Port Timing Diagram Write

1132 Hmc mode - Serial Port reaD operationa typical HMC Mode reaD cycle is shown in Figure 25

a the Master (host) asserts both sen (serial Port enable) and sDI to indicate a reaD cycle followed by a rising edge sClk note the lock Detect (lD) function is usually multiplexed onto the lD_sDo pin It is suggested that lD only be considered valid when sen is low In fact lD will not toggle until the first active data bit toggles on lD_sDo and will be restored immediately after the trailing edge of the lsB of serial data out as shown in Figure 25

b the slave (HMC1035lP6Ge) reads sDI on the 1st rising edge of sClk after sen sDI high initiates the reaD cycle (rD)



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15

HMC1035LP6GEv010712


c Host places the six address bits on the next six falling edges of sClk MsB first

d slave registers the address bits on the next six rising edges of sClk (2-7)

e slave switches from lock Detect and places the requested 24 data bits on sD_lDo on the next 24 rising edges of sCk (8-31) MsB first

f Host registers the data bits on the next 24 falling edges of sCk (8-31)

g slave restores lock Detect on the 32nd rising edge of sCk

h De-assertion of sen completes the cycle

SPi Hmc mode - read timing characteristicsParameter Conditions Min Typ Max Units





t5 sClk to sDo delay82ns+02

nspFns

t6 recovery time 10 ns

Figure 25 HMC Mode - Serial Port Timing Diagram - READ

114 Serial Port open modethe serial Port open Mode shown in Figure 26 and Figure 27 features

a Compatibility with general serial port protocols that use shift and strobe approach to communication

b Compatible with Hittite Pll with Integrated VCo solutions useful to address multiple chips of various types from a single serial port bus

the open Mode protocol has the following general features

a 3-bit chip address can address up to 8 devices connected to the serial bus

b Wide compatibility with multiple protocols from multiple vendors



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HMC1035LP6GEv010712


c simultaneous Writeread during the sPI cycle

d 5-bit address space

e 3 wire for Write only capability 4 wire for readWrite capability

Hittite Plls with integrated VCos support open Mode some legacy Pll and microwave Plls with integrated VCos only support HMC Mode Consult the relevant data sheets for details

typical serial port operation can be run with sClk at speeds up to 50 MHz

1141 open mode - Serial Port Write operationaVDD = DVDD = 3V plusmn5 aGnD = DGnD = 0V

SPi open mode - Write timing characteristicsParameter Conditions Min Typ Max Units

t1 sDI setup time to sClk rising edge 3 ns

t2 sClk rising edge to sDI hold time 3 ns


t4 sen high duration 10 ns

t5 sClk 32 rising edge to sen rising edge 10 ns



a typical WrIte cycle is shown in Figure 26

a the Master (host) places 24-bit data d23d0 MsB first on sDI on the first 24 falling edges of sClk

b the slave (HMC1035lP6Ge) shifts in data on sDI on the first 24 rising edges of sClk

c Master places 5-bit register address to be written to r4r0 MsB first on the next 5 falling edges of sClk (25-29)

d slave shifts the register bits on the next 5 rising edges of sClk (25-29)

e Master places 3-bit chip address a2a0 MsB first on the next 3 falling edges of sClk (30-32) Hittite reserves chip address a2a0 = 000 for all rF Pll with Integrated VCos

f slave shifts the chip address bits on the next 3 rising edges of sClk (30-32)

g Master asserts sen after the 32nd rising edge of sClk

h slave registers the sDI data on the rising edge of sen

Figure 26 Open Mode - Serial Port Timing Diagram - WRITE



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HMC1035LP6GEv010712


1142 open mode - Serial Port reaD operationa typical reaD cycle is shown in Figure 27

In general in open Mode the lD_sDo line is always active during the WrIte cycle During any open Mode sPI cycle lD_sDo will contain the data from the current address written in reg 00h[73] If reg 00h[73] is not changed then the same data will always be present on lD_sDo when an open Mode cycle is in progress If it is desired to reaD from a specific address it is necessary in the first sPI cycle to write the desired address to reg 00h[73] then in the next sPI cycle the desired data will be available on lD_sDo

an example of the open Mode two cycle procedure to read from any random address is as follows

a the Master (host) on the first 24 falling edges of sClk places 24-bit data d23d0 MsB first on sDI as shown in Figure 27 d23d5 should be set to zero d4d0 = address of the register to be reaD on the next cycle


c Master places 5-bit register address r4r0 (the reaD aDDress register) MsB first on the next 5 falling edges of sClk (25-29) r4r0=00000


e Master places 3-bit chip address a2a0 MsB first on the next 3 falling edges of sClk (30-32)Chip address is always 000 for rF Pll with Integrated VCos




i Master clears sen to complete the address transfer of the two part reaD cycle

j If one does not wish to write data to the chip at the same time as we do the second cycle then it is recommended to simply rewrite the same contents on sDI to register zero on the reaD back part of the cycle

k Master places the same sDI data as the previous cycle on the next 32 falling edges of sClk

l slave (HMC1035lP6Ge) shifts the sDI data on the next 32 rising edges of sClk

m slave places the desired read data (ie data from the address specified in reg 00h[73] of the first cycle) on lD_sDo which automatically switches to sDo mode from lD mode disabling the lD output

m Master asserts sen after the 32nd rising edge of sCk to complete the cycle and revert back to lock Detect on lD_sDo

SPi open mode - read timing characteristicsParameter Conditions Min Typ Max Units





t5 sClk rising edge to sDo time 82ns+02nspF ns

t6 recovery tIme 10 ns

t7 sCk 32 rising edge to sen rising edge 10 ns



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HMC1035LP6GEv010712


1143 HmcSPi open mode reaD operation - 2 cycles

Figure 27 Serial Port Timing Diagram - READ

For more information on using the GPo pin while in sPI open Mode please see section 115



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HMC1035LP6GEv010712


12 configuration at Start-Upto configure the Pll after power up follow the instructions below

1 Configure the reference divider (write to reg 02h) if required

2 Configure the delta-sigma modulator (write to reg 06h) bull Configuration involves selecting the mode of the delta-sigma modulator (Mode a or Mode B)

selection of the delta-sigma modulator seed value and configuration of the delta-sigma modulator clock scheme It is recommended to use the values found in the Hittite Pll evaluation board control software register files

3 Configure the charge pump current and charge pump offset current (write to reg 09h)

4 Configure the VCo subsystem (write to reg 05h for more information see section 131 and ldquoVCo subsystem register Map Detailed writes to the VCo subsystem via Pll reg 05h at start-up are available in the register setting Files found in the Hittite Pll evaluation software received with a product evaluation kit or downloaded from wwwhittitecom

5 Program the frequency of operationbull Program the integer part (write to reg 03h)bull Program the fractional part (write to reg 04h)

6 Configure the VCo output divider if needed in the VCo subsystem via Pll reg 05h

once the HMC1035lP6Ge is configured after startup in most cases the user only needs to change frequencies by writing to reg 03h integer register reg 04h fractional register and reg 05h to change the VCo output divider or doubler setting if needed and possibly adjust the charge pump settings by writing to reg 09h

For detailed and most up-to-date start-up configuration please refer to the appropriate register setting Files found in the Hittite Pll evaluation software received with a product evaluation kit or downloaded from wwwhittitecom

13 Vco Serial Port interface (SPi)the HMC1035lP6Ge communicates with the internal VCo subsystem via an internal 16 bit VCo serial Port (eg see Figure 25) the internal serial port is used to control the step tuned VCo and other VCo subsystem functions such as rF output divider doubler control and rF buffer enable

note that the internal VCo subsystem sPI (VsPI) runs at the rate of the autoCal FsM clock TFSM where the FsM clock frequency cannot be greater than 50 MHz the VsPI clock rate is set by reg 0ah[1413] with a default setting = 1 or XreFP divided by 4

Writes to the VCorsquos control registers are handled indirectly via writes to reg 05h of the Pll a write to Pll reg 05h causes the Pll subsystem to forward the packet MsB first across its internal serial link to the VCo subsystem where it is interpreted

the VCo serial port has the capability to communicate with multiple subsystems inside the IC For this reason each subsystem has a subsystem ID reg 05h[20]

each subsystem has multiple registers to control the functions internal to the subsystem which may be different from one subsystem to the next Hence each subsystem has internal register addresses bits (ldquoreg 05hrdquo63])

Finally the data required to configure each register within the VCo subsystem is contained in reg 05h[157]



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HMC1035LP6GEv010712


131 VSPi Use of reg05hthe packet data written into reg 05h is sub-parsed by logic at the VCo subsystem into the following 3 fields

1 [20] - 3 bits - VCo_ID target subsystem address = 000b

2 [63] - 4 bits - VCo_reGaDDr the internal register address inside the VCo subsystem

3 [157] - 9- bits- VCo_Data data field to write into the VCo register

For example to write 0_1111_1110 into register 2 of the VCo subsystem (VCo_ID = lsquo000rsquob) and set the VCo output divider to divide by 62 the following needs to be written to reg 05h =rsquo0_1111_1110 0010 000rsquo b

During autoCal the autoCal controller only updates the data field of reg 05h the VCo subsystem register address (reg 05h[63]) must be set to 0000 for the autoCal data to be sent to the correct address

VCo subsystem ID and register address are not modified by the autoCal state machine Hence if a manual access is done to a VCo subsystem register the user must reset the register address to zero before a change of frequency which will re-run autoCal

since every write to reg 05h will result in a transfer of data to the VCo subsystem if the VCo subsystem needs to be reset manually it is important to make sure that the VCo switch settings are not changed Hence the switch settings in reg 10h[70] need to be read first and then rewritten to reg 05h[158]

In summary first read ldquoreg 10hrdquo then write to ldquoreg 05hrdquo as follows

reg 10h[70] = vv x yyyyy

reg 05h = vv x yyyyy 0 0000 iii

reg 05h[20] = iii subsystem ID 3 bits (000)

reg 05h[63] = 0000 subsystem register address

reg 05h[7] = 0 calibration tune voltage off

reg 05h[128] = yyyyy VCo caps

reg 05h[13] = x donrsquot care

reg 05h[1514] = vv VCo select

10 Pll register map

11 reg 00h iD register (read only)Bit Type Name Width Default Description

[230] ro chip_ID 24 a7975 HMC832lP6Ge chip ID

12 reg 00h open mode read addressrSt Strobe register (Write only)Bit Type Name Width Default Description

[40] Wo read address 5 -(WrIte onlY) read address for next cycle - open Mode only

[5] Wo soft reset 1 -soft reset - both sPI modes reset (set to 0 for proper operation)

[236] Wo not Defined 18 - not Defined (set to 0 for proper operation)



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HMC1035LP6GEv010712


13 reg 01h rSt register (Default 000002h)

Bit Type Name Width Default Description

[0] rW reserved 1 0 reserved










14 reg 02h refDiV register (Default 000001h)


[130] rW rdiv 14 1

reference Divider rsquorrsquo Value ldquoDivider use also requires refBufen reg08[3]=1and Dividermin 1dmax 16383d

15 reg 03h frequency register - integer Part (Default 000019h)


[180] rW intg 19 25d

VCo Divider Integer part used in all modes)

Fractional Modemin 20dmax 219 -4 = 7FFFCh = 524284d

Integer Modemin 16dmax 219-1 = 7FFFFh = 524287d

16 reg 04h frequency register - fractional Part (Default 000000h)


[230] rW frac 24 0

VCo Divider Fractional part (24-bit unsigned) see Fractional Frequency tuning

Used in Fractional Mode only (nfrac=reg 04h224

min 0dmax 224-1

17 reg 05h Vco SPi register (Default 000000h)


[20] rW VCo subsystem_ID 3 0 Internal VCo subsystem ID

[63] rW VCo subsystem register address 4 0 For interfacing with the VCo please see section 131

[157] rW VCo subsystem data 9 0 Data



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HMC1035LP6GEv010712


notereg 05h is a special register used for indirect addressing of the VCo subsystem Writes to reg 05h are automatically forwarded to the VCo subsystem by the VCo sPI state machine controller

reg05h is a read-Write register However reg05h only holds the contents of the last transfer to the VCo subsystem Hence it is not possible to read the full contents of the VCo subsystem only the content of the last transfer to the VCo subsystem can be read Please take note special considerations for autoCal related to reg 05h

18 reg 06h SD cfg register (Default 200B4ah)


[10] rW seed 2 2

selects the seed in Fractional Mode00 0 seed01 lsb seed02 B29D08h seed03 50F1CDh seednote Writes to this register are stored in the HMC1035lP6Ge and are only loaded into the modulator when a frequency change is executed and if autoseed Reg06h[8] =1



[7] rW frac_bypass 1 0

0 Use Modulator required for Fractional Mode

1 Bypass Modulator required for Integer Mode

note In bypass fractional modulator output is ignored but fractional modulator continues to be clocked if frac_rstb =1 Can be used to test the isolation of the digital fractional modulator from the VCo output in integer mode




[11] rW sD enable 1 1

0 disable frac core use for Integer Mode or Integer Modewith CsP1 enable Frac Core required for Fractional Mode or Integer isolation testingthis register controls whether autoCal starts on an Integer or a Fractional write











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HMC1035LP6GEv010712


19 lock DetectHMC1035lP6Ge features a robust digital lock detect function that provides faster and more accurate lock detect information compared to conventional analog lock detect schemes and offers serial port monitoring of lock detect for visibility into device status from the host controller

Lock Detect Enable Reg 07h[3]=1 is a global enable for all lock detect functions the lock Detect circuit effectively measures the difference between the arrival of the reference and the divided VCo signals at the Phase Detector the arrival time difference must consistently be less than the lock Detect window length to declare lock either signal may arrive first only the difference in arrival times is considered

wincnt_max in Reg 07h[20] defines the number of consecutive counts of the divided VCo that must land inside the lock detect window to declare lock

191 analog or Digital lock Detect

analog lock Detect the lock detect window may be generated by either an analog one shot circuit or a digital one shot based upon an in-ternal timer Clearing reg 07h[6]=0 will result in a fixed analog nominal 10 ns window as shown in Figure 28 below the analog window cannot be used if the PD rate is above 50 MHz or if the charge pump offset is too large If charge pump offset or PD frequency are changed significantly then the lock detect window may need to be adjusted

Figure 28 Lock Detect

192 Digital lock Detect

setting reg 07h[6]=1 will result in a variable length lock detect window based upon an internal digital timer the timer period is set by the number of cycles of the internal lD clock as programmed by reg 07h[97] the lD clock frequen-cy is adjustable by reg 07h[1110] the lD clock signal can be viewed via the GPo test pins

193 Declaration of lock

the lock Detect Flag status is always readable in reg 12h[1] if locked = 1 lock Detect status is also output to the lD_sDo pin according to reg 0Fh[40]=1 again if locked lD_sDo will be high Clearing reg 0Fh[6]=0 will display the lock Detect Flag on lD_sDo except when a serial port read is requested in which case the pin reverts temporar-ily to the serial Data out pin and returns to the lock Detect Flag after the read is completed



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HMC1035LP6GEv010712


194 reg 07h lock Detect register (Default 00014Dh)


[20] rW lkd_wincnt_max 3 5d

lock detect window sets the number of consecutive counts of divided VCo that must land inside the lock Detect Window to declare loCk0 51 322 963 2564 5125 20486 81927 65535

[3] rW enable Internal lock Detect 1 1 1 enabled


[6] rW lock Detect Window type 1 1lock Detection Window timer selection1 Digital programmable timer0 analog one shot nominal 10 ns window

[97] rW lD Digital Window duration 3 2

0 lock Detection - Digital Window Duration0 12 cycle1 1 cycle2 2 cycles3 4 cycles4 8 cycles5 16 cycles6 32 cycles7 64 cycles






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HMC1035LP6GEv010712


110 reg 08h analog en register (Default C1BeFFh)

Bit type name Width Default Description






[5] rW gpo_pad_en 1 1

0 - Pin lD_sDo disabled

1 - and regFh[7]=1 Pin lD_sDo is always on required for use of GPo port

1 - and regFh[7]=0 sPI lDo_sPI is off if unmatched chip address is seen on the sPI allowing a shared sPI with other compatible parts




[9] rW Prescaler Clock enable 1 1 reserved

[10] rWVCo Buffer and PrescalerBias enable

1 1 VCo Buffer and Prescaler Bias enable







[21] rW High Frequency reference 1 0 Program to 1 for Xtal gt 200 MHz





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HMC1035LP6GEv010712


111 charge Pump current SelectionHMC1035lP6Ge features provides a charge pump current with programmable gain this enables the user to refine and maintain optimal Pll loop bandwidth over a wide range of output frequencies and feedback divide ratios

a straight forward method for determining the charge pump gain setting for a fixed loop filter (eg 127 kHz) and reference frequency (eg 50MHz) is to follow the following equation

Icp_up = Icp_dn = 11ma + (23ma ndash 11ma) (Fvco ndash 15 GHz) (3 GHz ndash 15 GHz)

Here charge pump current (Icp) is linearly modified to compensate for the feedback divide ratio (n) as it scales with VCo output frequency (Fvco)

the charge pump current is set by register configuration (reg_09h [60] and reg_09h [137])

charge Pump Phase offset ndash fractional mode

the HMC1035lP6Ge provides a programmable charge pump phase offset feature to aid in minimizing integer boundary spurs and maintain low in-band phase noise while the Pll is in Fractional Mode of operation

Phase offset is achieved by introducing a constant ldquoleakagerdquo current into the loop filter the amount of leak-age current that is recommended is related to the charge pump gain (Icp) and the PFD comparison frequency (Fcomp) by the following equation(s)

tcomp = 1 FcompI_leak = (25x10-9 + 4tvco) Icp tcomp

Where tvco is the rF period at the input of the feedback dividerIcp is the selected charge pump current

leakage (I_leak) can be applied with either positive or negative current driven into the loop filter (ldquouprdquo or ldquodownrdquo respectively) Up leakage is recommended for the HMC1035lP6Ge

leakage magnitude and direction are set through registers reg_09h [2014] and reg_09h [22] respectively



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HMC1035LP6GEv010712


112 reg 09h charge Pump register (Default 403264h)


[60] rW CP Dn Gain 7100d64h

Charge Pump Dn Gain Control 20 microaradicstepaffects fractional phase noise and lock detect settings0d = 0 microa1d = 20 microa2d = 40 microa127d = 254ma

[137] rW CP UP Gain 7100d64h

Charge Pump UP Gain Control 20 microa per stepaffects fractional phase noise and lock detect settings0d = 0 microa1d = 20 microa2d = 40 microa127d = 254ma

[2014] rW offset Magnitude 7 0

Charge Pump offset Control 5 microastepaffects fractional phase noise and lock detect settings0d = 0 microa1d = 5 microa2d = 10 microa127d = 635 microa

[21] rW offset UP enable 1 0 recommended setting = 0

[22] rW offset Dn enable 1 1 recommended setting = 1 in Fractional Mode 0 otherwise


113 reg 0ah Vco autocal configuration register (Default 002205h)


[20] rW Vtune resolution 3 5

r Divider Cycles0 - 11 - 22 - 43 - 84 - 325 - 646 - 1287 - 256




[10] rW Force Curve 1 0 Force curve sent during tuning tune from reg5

[11] rW Bypass VCo tuning 1 0 Bypass VCo tuning

[12] rW no VsPI trigger 1 0 Donrsquot trigger a transfer on writes to reg 05h

[1413] rW FsMVsPI Clock select 2 1

set the autoCal FsM and VsPI Clock (50 MHz maximum)0 Input Crystal reference1 Input Crystal reference42 Input Crystal reference163 Input Crystal reference32





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HMC1035LP6GEv010712


114 reg 0Bh PD register (Default 0F8061h)


[20] rW PD_del_sel 3 1 sets PD reset path delay (recommended setting 001)



[5] rW PD_up_en 1 1 enables the PD UP output

[6] rW PD_dn_en 1 1 enables the PD Dn output

[87] rW CsP Mode 2 0

Cycle slip Prevention Modeextra current is driven into the loop filter when the phase error is larger than0 Disabled1 54ns2 144ns3 241nsthis delay varies by +- 10 with temperature and +- 12 with process

[9] rW Force CP UP 1 0 Forces CP UP output on - Use for test only

[10] rW Force CP Dn 1 0 Forces CP Dn output on - Use for test only

[11] rW reservedl 1 0 reserved







115 exact frequency modeHittitersquos family of clock generation products have a unique feature called exact frequency mode which allows nearly arbitrary frequency conversion or ldquogearrdquo ratios

there are 5 registers which control the 3 frequency dividers in the part and thus the overall frequency translation ratio

1) reference Divider (r) ndash Pll register 2 - takes in up to 350MHz reference and optionally divides down to lt 100MHz for the PFD comparison rate

2) VCo n-Divider (nDIV) ndash Integer (Pll reg 3) + Fractional section (Pll reg 4) accepts values from 16 to 525287 in integer mode or 200 to 2422840 in fractional mode

3) VCo output Divider (noUt) ndash VCo register 2

the output frequency is given byGear ratio = (1r) (nDIV) (1noUt)

since the Pll supports a fractional division ratio n can be further broken down into a fraction n = (Mn)

to achieve a certain multiplication ratio we recommend the following procedure ndash along with a worked example

example assume we want a multiplication ratio of Mn = 944255 with an input frequency of 16804MHz-thus fout ~ 622MHz



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29

HMC1035LP6GEv010712


1) Calculate noUt Determine the fundamental frequency of the VCo relative to your desired output frequency the VCo cores run internally from 15 to 3GHz

a since the VCo output divider is only capable of even division ratios there is a factor of lsquo2rsquo in the calculation

b noUt = 2floor(fmax(2fout)) eg noUt = 2 floor ( 3G 2622M ) noUt=2 floor (241hellip )noUt = 2 2noUt = 4

so the VCo will run at ~ 4 622 MHz

2) Calculate rDIV Determine if the rdivider needs to be used to keep the PFD rate under its limit and if so its value

a the PFD comparison rate can be as high as 100MHz to avoid a 2 stage locking process we rec-ommend running the PFD below 70MHz

b r = ceiling ( fpfd_max freference )eg r = ceiling ( 16804MHz 70 MHz)r = ceiling ( 24 )r = 3

so the PFD comparison rate will be 16804MHz 3 or ~ 56MHz

3) Calculate nDIV We have now determined an r and noUt value which keep the Pll in a valid operating condi-tion and we are left to choose the fractional division ratio nDIV which provides the desired gear ratio

a Calculate the desired nDIV value (which could be a fraction) such that your overall gear ratio is maintained

i (M n)_desired = (1r) nDIV (1noUt)ii nDIV = (M n)_desired r noUteg nDIV = (944 255 ) 3 4nDIV = 7728 255b reduce the fraction into a integer + fractional portioneg nDIV = 7728 255nDIV = 30 + 78255nDIV = 30 + 2685 = nInt + (nUM Den)nDIV = ~ 30 + 0306hellipc Confirm that the minimum divide ratio limit is respected In fractional mode the minimum divide ratio

is 200 in integer mode it is 16 If nDIV is too low increase the reference divide ratio (step 2b) and recalculate For example doubling the reference divide ratio r will double the corresponding nDIV setting

eg In this example nDIV of ~ 303 is gt 200 so it is accetptable and r of 3 is okay

4) Calculate the Integer and approximate Fractional setpoint to implement nDIV calculated in step 3examplenint = floor (nDIV)nint = 30nfrac = ceil(2^24 (nDIV-nint))nfrac = ceiling(16777216 2685) = ceiling(5131854306) = 5131854 dec

5) note that the 24-bit quantized nDIV ratio = 30 + (5131854 16777216) has a slight frequency offset of ~23Hz relative to the desired ratio of 30 + 2685 to eliminate this offset and generate the exact multiplication ratio the user desires set the exact frequency counter (reG0Ch) to the reduced denominator as calculated in step 3b exact Frequency Counter = Den (from step 3b) eg set register 0Ch = 85 dec



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HMC1035LP6GEv010712


1151 reg 0ch exact frequency mode register (Default 000000h)


[130] rW number of Channels per Fpd 14 0

Comparison Frequency divided by the Correction rate Must be an integer Frequencies at exactly the correction rate will have zero frequency error0 Disabled1 Disabled216383d (3FFFh)



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HMC1035LP6GEv010712


116 gPo_lDSPo registerHMC1035lP6Ge features a GPo (General Purpose output) that enables users to control and read various states of the device including Pll and VCo properties

the HMC1035lP6Ge shares the lD_sDo (lock-Detectserial Data out) pin to perform various functions It is driv-en by a tri-state CMos driver with ~200 Ω rout In its default configuration after power-on-reset the output driver is disabled and only drives during appropriately addressed sPI reads this allows it to share the output with other devices on the same bus to monitor any of the GPo signals including lock Detect set reg 0Fh[7] = 1 to keep the sDo driver always on this stops the lDo driver from tristating and means that the sDo line cannot be shared with

other devices the signals available on the GPo are selected by changing ldquoGPo selectrdquo reg 0Fh[40]

1161 reg 0fh gPo_lDSPo register (Default 000001h)


[40] rW gpo_select 5 1d

signal selected here is output to sDo pin when enabled

0 Data from reg0F[5]1 lock Detect output 2 lock Detect trigger3 lock Detect Window output4 ring osc test5 Pullup Hard from CsP6 PullDn hard from CsP7 reserved8 reference Buffer output9 ref Divider output10 VCo divider output 11 Modulator Clock from VCo divider12 auxiliary Clock13 aux sPI Clock14 aux sPI enable15 aux sPI Data out16 PD Dn17 PD UP18 sD3 Clock Delay19 sD3 Core Clock20 autostrobe Integer Write21 autostrobe Frac Write22 autostrobe aux sPI23 sPI latch enable24 VCo Divider sync reset25 seed load strobe26-29 not Used30 sPI output Buffer en31 soft rstB

[5] rW GPo test Data 1 0 1 - GPo test Data

[6] rW Prevent automux sDo 1 01- outputs GPo data only0 - automuxes between sDo and GPo data

[7] rW lDo Driver always on 1 01- lD_sDo Pin Driver always on0 - lD_sDo Pin driver only on during sPI read cycle

[8] rW Disable PFet 1 0 program to 0

[9] rW Disable nFet 1 0 program to 0



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32

HMC1035LP6GEv010712


117 reg 10h Vco tune register (Default 000020h)


[70] ro VCo switch setting 8 32

read only register Indicates the VCo switch setting selected by the autoCal state machine to yield the nearest free running VCo frequency to the desired operating frequency not valid when reg10h[8] = 1 autoCal Busy note if a manual change is done to the VCo switch settings this register will not indicate the current VCo switch position 0 = highest frequency1 = 2nd highest256 = lowest frequencynote VCo subsystems may not use all the MsBs in which case the unused bits are donrsquot care

[8] ro autoCal Busy 1 0Busy when autoCal state machine is searching for the nearest switch setting to the requested frequency

118 reg 11h Sar register

(Default 007FFFh)


[180] ro sar error Mag Counts 19 219-1 sar error Magnitude Counts

[19] ro sar error sign 1 0 sar error sign 0=+ve 1=-ve

119 reg 12h gPo2 register (Default 000000h)


[0] ro GPo 1 0 GPo state

[1] ro lock Detect 1 0lock Detect status1 = locked0 = Unlocked

120 reg 13h BiSt register(Default 000000h)


[150] ro reserved 19 4697d reserved

[16] ro reserved 1 0 reserved



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33

HMC1035LP6GEv010712


20 Vco Subsystem register mapPlease note that the VCo subsystem uses indirect addressing via reg 05h For more detailed information on how to write to the VCo subsystem please see section VCo subsystem register Map

21 Vco_reg 00h tuningBit Type Name Width Default Description

[0] Wo Cal 1 0VCo tune voltage is redirected to a temperature compensated calibration voltage

[81] Wo CaPs 8 16

VCo sub-band selection 0 - max frequency1111 1111 - min frequencynot all sub-bands are used on the various products

22 Vco_reg 01h enablesBit Type Name Width Default Description

[0] Wo Master enable VCo subsystem 1 1 0 - all VCo subsystem blocks off

[1] Wo VCo enable 1 1 enables VCos

[2] Wo Pll Buffer enable 1 1 enables Pll Buffer to n Divider

[3] Wo Io Master enable 1 1enables output stage and the output Divider It does not enabledisable the VCo

[4] Wo spare 1 1 donrsquot care

[5] Wo output stage enable 1 1 output stage enable

[76] Wo reserved 2 2 reserved

[8] Wo donrsquot care 1 1 donrsquot care



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34

HMC1035LP6GEv010712


For example to disable the output stage of the VCo subsystem of the HMC1035lP6Ge bit 5 in VCo_reg 01h needs to be cleared If the other bits are left unchanged then lsquo1 1101 1111rsquo needs to be written into VCo_reg 01h the VCo subsystem register is accessed via a write to Pll subsystemreg 05h = lsquo1 1101 1111 0001 000rsquo = eF88h

reg 05h[20] = 000 VCo subsystem ID 0reg 05h[63] = 0001 VCo subsystem register addressreg 05h[7] = 1 Master enablereg 05h[8] = 1 VCo enablereg 05h[9] = 1 Pll Buffer enablereg 05h[10] = 1 Io Master enablereg 05h[11] = 1 reservedreg 05h[12] = 0 Disable the output stagereg 05h[1413] = lsquo01rsquob reg 05h[15] = 1 donrsquot care

23 Vco_reg 02h BiasesBit Type Name Width Default Description

[50] Wo rF Divide ratio 6 1

0 - Mute 1 - Fo2 - Fo23 - invalid defaults to 24 - Fo45 - invalid defaults to 46 - Fo660 - Fo6061 - invalid defaults to 6062 - Fo62gt 62 - invalid defaults to 62


[8] Wo Donrsquot Care 1 0 Donrsquot Care

For example to write 0_1111_1110 into VCo_reg 03h VCo subsystem (VCo_ID = lsquo000rsquob) and set the VCo output divider to divide by 62 the following needs to be written to reg 05h =rsquo0_1111_1110 0010 000rsquo b

reg 05h[20] = 00 subsystem ID 0reg 05h[63] = 0010 VCo register address 2dreg 05h167] = 0_1111_1110 Divide by 62 max output rF gain

Hmc1035lP6ge Power versus Performance Priority modesthe HMC1035lP6Ge is designed with 2 major configuration options Power Priority and Performance Priority the Power Priority setting reduces the current consumption of the part whereas the Performance Priority setting improves the Jitter and Phase noise performance the settings are selected via the appropriate sPI registers VCo_reg 03h [10]

the ldquoPower Priority Moderdquo is used in order to reduce the current consumption from 237 ma to 173 ma such as may be required in power sensitive applications where the lowest phase noise performance may not be critical the Power Priority mode does not cause a reduction on the output signal power but it degrades the phase noise and thus jitter performance

In order to realize the best phase noise and jitter performance the HMC1035lP6Ge should be operated in the ldquoPerformance Priority Moderdquo By invoking this mode the phase noise will improve or decrease by 10 dB resulting in a -163 dBcHz floor the ldquoPerformance Priority Moderdquo is optimal in driving the sample clock inputs of aDCDaCrsquos and high speed serDes reference clock inputs where jitter performance is of utmost importance

the Power versus Performance Priority mode is set by the VCo_reg03h bits [10] and the default condition is Power Priority Mode bit set to a logic 1



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HMC1035LP6GEv010712


24 Vco_reg 03h configBit Type Name Width Default Description

[10] Wo Power- Performance Priroirty 2 2

selects output noise floor performance level at a cost of increased current consumption01 Power Priority

lowest Current Consumption 11 Performance Priority

Best Phase noise other states (00 and 10) not supported

[2] Wo rF_P output enable 1 0logic 1 enables the output on rF_P pin

required for differential operation or single-ended output on rF_P pin

[3] Wo rF_n output enable 1 0logic 1 enables the output on rF_n pin

required for differential operation or single-ended output on rF_n pin

[4] Wo Internal termination enable 1 1logic 1 enables the internal bias termination is used for lVDs level outputs set to logic 0 for external termination

[5] WoIncrease Internal output resistance

1 0logic 1 increases internal output termination by ~ 15 Ω on each pin (rF_n and rF_P)


[87] Wo Mute Mode 2 1

Defines when the Mute Function is enabled (the output is muted)

bull00 Mute enabled when divide ratio (VCo_reg 02h[50] = 0

bull01 During VCo Calibration (bull10 During VCo Calibration or when lock Detect

GPo output is off (For more information see section

GPo_lDsPo registerbull11 Mute always on

25 Vco_reg 04h calBias

specified performance is only guaranteed with the required settings in this table other settings are not supported








26 Vco_reg05h cf_calBit Type Name Width Default Description








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HMC1035LP6GEv010712


27 Vco_reg06h mSB calBit Type Name Width Default Description






28 Vco_reg 07h mSB calBit Type Name Width Default Description

[30] Wo output stage Gain Control 40001

0000 -gt output = 690 mV 0001 -gt output = 780 mV 0010 -gt output = 900 mV0011 -gt output = 980 mV0100 -gt output = 1100 mV0101 -gt output = 1260 mV0110 -gt output = 1400 mV0111 -gt output = 1590 mV1000 -gt output = 1810 mV1001 -gt output = 1980 mV1010 -gt output = 2250 mV1011 -gt output = 2560 mV1100 -gt Invalid1110 -gt Invalid1111 -gt Invalid





note all reserved bits should be programmed to default conditions



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HMC1035LP6GEv010712


Hmc1035lP6ge application informationthe HMC1035lP6Ge features a flexible output Frequency range (25 MHz to 2500 MHz) industry leading phase noise and phase jitter performance excellent noise floor (lt-162 dBcHz) and a high level of integration HMC1035lP6Ge is ideal as a high frequency low jitter processor clock a clock source for high-frequency data converters or as a reference oscillator for Physical layer Devices (PHY)

the HMC1035lP6Ge can also be used as an lo for 10G40G100G optical modules and transponders as a reference clock for 10G40G100G line cards and for jitter attenuation and frequency translation synchronous ethernet sonetsDH and otn applications often require jitter attenuation and frequency translation on the recovered line clock

Figure 29 HMC1035LP6GE in a typical transmit chain



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HMC1035LP6GEv010712


Hmc1035lP6ge application informationthe HMC1035lP6Ge can also be used as an lo for 10G optical modules and transponders (Figure 30) as a reference clock for 1G10G line cards (Figure 31) and for jitter attenuation and frequency translation (Figure 32)

synchronous ethernet sonetsDH and otn applications often require jitter attenuation and frequency translation on the recovered line clock

Figure 30 HMC1035LP6GE used as a local oscillator (LO) for 10G modulestransponders

Figure 31 HMC1035LP6GE used as a reference clock for 1G10G line cards



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HMC1035LP6GEv010712


Hmc1035lP6ge application information

Figure 32 HMC1035LP6GE used in a jitter attenuation application for Synchronous Ethernet amp Line Timing



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HMC1035LP6GEv010712


line and reference clock rate

OTN Line Rates (Gbps) Typical Reference Clock Rates (MHz)

otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425

Typical Applications

Features

Functional Diagram

General Description

Performance Characteristics

Figure of Merit

Loop Filter Configuration Table

Absolute Maximum Ratings

Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB

Evaluation PCB Schematic

Evaluation Order Information

jitter attenuation application for Synchronous Ethernet amp Line Timing

reference clock for 1G10G line cards

local oscillator (LO) for 10G modulestransponders

HMC Mode - Serial Port Timing Diagram - WRITE

SPI HMC Mode - Read Timing Characteristics

Serial Port Timing Diagram - READ

Electrical Specifications

RF Output Characteristics

VCO Output Divider

PLL RF Divider Characteristics

Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit

HMC1035LP6GE used in a jitter attenuation application for Synchronous Ethernet amp Line Timing



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HMC1035LP6GEv010712


general Description

the HMC1035lP6Ge is a low-noise wide-band 33 V clock generator IC with a fractional-n Phase locked loop (Pll) that features an integrated Voltage Controlled oscillator (VCo) the device provides differential clock outputs between 25 MHz and 2500 MHz range the HMC1035lP6Ge features a low noise Phase Detector (PD) and Delta-sigma modulator capable of operating at up to 100 MHz which permits wider loop-bandwidths and excellent spurious performance

the HMC1035lP6Ge features industry leading phase noise and jitter performance across the operating range that enable it to improve link level jitter performance Bit-error-rates (Ber) and eye diagram metrics the superior noise floor (lt-162 dBcHz) makes the HMC1035lP6Ge an ideal source for a variety of applications ndashsuch as clock references for high speed data converters physical layer devices (PHY) serializerdeserializer (serDes) circuits FPGas and processors the HMC1035lP6Ge can also be used as an lo for 10G40G100G optical modules and transponders as well as primary reference clock for 10G40G100G line cards and for jitter attenuation and frequency translation

the differential output of the HMC1035lP6Ge can be set to either external termination which could be used for lVPeCl operation or Internal termination for operation in an lVDs compatible mode or lVPeCl see Figure 18 additionally an ouput swing adjustment makes the device flexible and compatible with a wide variety of signal level requirements the output can be internally terminated to reduce component count and cost or could be terminated externally using standard lVPeCl termination methods such as Figure 21 an output Mute function allows the user to shut off the outputs such as may be required for board testing or debugging the lVPeCllVDs amplitude select and output Mute function are all programmed sPI serial programming

the HMC1035lP6Ge is designed to select between a Power Priority or a Performance Priority mode the Power Priority setting reduces the current consumption of the part whereas the Performance Priority setting improves the Jitter and Phase noise performance

the 24 bit Delta-sigma Modulator further enhances Hittitersquos exact Frequency Mode which enables users to generate output frequencies with 0 Hz frequency error in many applications



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HMC1035LP6GEv010712



















lVDs Mode 12 mV

lVPeCl Mode 20 V








20 524283












1 kHz -143 dBcHz



Logic Inputs


levels40 50 60 DVDD







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HMC1035LP6GEv010712




+ 33V supplies



315 33 35 V


+33V








termination173 ma


termination221 ma













107 fs


97 fs



125 fs


110 fs





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HMC1035LP6GEv010712



-180

-170

-160

-150

-140

-130

-120

-110

-100

1 10 100 1000 10000 100000

625 MHz_LVDS

625 MHz_LVPECL

2500 MHz_LVDS

2500 MHz_LVPECL

OFFSET(KHz)

PH

AS

E N

OIS

E(d

BcH

z)

-180

-170

-160

-150

-140

-130

-120

-110

-100

1 10 100 1000 10000 100000

625 MHz_LVDS

625 MHz_LVPECL

2500 MHz_LVDS

2500 MHz_LVPECL

OFFSET(KHz)

PH

AS

E N

OIS

E(d

BcH

z)

-180

-170

-160

-150

-140

-130

-120

-110

-100

1 10 100 1000 10000 100000


OFFSET(KHz)

PH

AS

E N

OIS

E(d

BcH

z)

-180

-170

-160

-150

-140

-130

-120

-110

-100

1 10 100 1000 10000 100000

62208 MHz_LVDS

62208 MHz_LVPECL

2500 MHz_LVDS

2500 MHz_LVPECL

OFFSET(KHz)

PH

AS

E N

OIS

E(d

BcH

z)

40

60

80

100

120

140

160

LVDS_PWR_PRI

LVDS_PERF_PRI

LVPECL_PWR_PRI

LVPECL_PWR_PRI

INT

EG

RA

TE

D R

MS

JIT

TE

R (

fs)

625

FREQUENCY (MHz)

2500

-180

-160

-140

-120

-100

-80

1 10 100 1000 10000 100000

XO

OCXO

OFFSET(KHz)

PH

AS

E N

OIS

E(d

BcH

z)









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HMC1035LP6GEv010712


-200

-150

-100

-50

0

50

100

150

200

-50 0 50 100 150 200 250 300

TIME( (uS)

PH

AS

E E

RR

OR

(D

EG

RE

E)

200

400

600

800

1000

1200

1400

100 1000

LVDS_PWR_PRI

LVDS_PERF_PRI

LVPECL_PWR_PRI

LVPECL_PERF_PRI

FRQUENCY (MHz)

Vp

pd

(m

V)

3000


40

60

80

100

120

140

160

LVDS_PWR_PRI

LVDS_PERF_PRI

LVPECL_PWR_PRI

LVPECL_PWR_PRI

INT

EG

RA

TE

D R

MS

JIT

TE

R (

fs)

250062208

FREQUENCY (MHz)

-50 0 50 100 150 200 250 300

TIME( (uS)

FR

EQ

UE

NC

Y E

RR

OR

(H

z)

2 109

60

80

100

120

140

160


RIS

E T

IME

(p

s)

250062208

FREQUENCY (MHz)

60

80

100

120

140

160


FA

LL

TIM

E (

ps)

250062208

FREQUENCY (MHz)








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7

HMC1035LP6GEv010712



C1 (pF)

C2 (nF)

C3 (pF)

C4 (pF)

r2 (Ω)

r3 (Ω)

r4 (Ω)

loop Filter Design

127 390 10 82 82 750 300 300

75 270 27 200 390 430 390 390


100

120

140

160

180

200

220


IDD(m

A)

Fo16 Fo4Fo8 FoFo2

FREQUENCY


47

48

49

50

51

52

LVDS_PWR_PRI

LVDS_PERF_PRI

LVPECL_PWR_PRI

LVPECL_PERF_PRI

DU

TY

CY

CL

E (

)

250062208

FREQUENCY (MHz)

-1500

-1000

-500

0

500

1000

1500

0 05 1 15 2 25 3

LVDS PERF PRI

LVDS PWR PRI

LVPECL PERF PRI

LVPECL PWR PRI

TIME (ns)

Vp

pd

(m

V)





500

1000

1500

2000

2500

3000

0 2 4 6 8 10

Vp

pd

(m

V)

27C

-40C

85C

GAIN SETTING STEP



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8

HMC1035LP6GEv010712


outline Drawing

notes


sIlICon IMPreGnateD










-03V to +36V





10 degCW

reflow soldering








Package information



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9

HMC1035LP6GEv010712


Pin Descriptions



2 5 6 8 9 11 - 14 18 - 22 24

26 34 37 38nC





















40 BIas





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HMC1035LP6GEv010712







evaluation PcB



evaluation kit


ekIt01-HMC1035lP6Ge


eVal01-HMC1035lP6G

ekIt01-HMC1035lP6G





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HMC1035LP6GEv010712










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12

HMC1035LP6GEv010712










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HMC1035LP6GEv010712


11 Serial Port







Multi-UserOpen Mode

reaDChip ID24-bits

Chip ID 24-bits

WRITEsoft reset

General strobes











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HMC1035LP6GEv010712




















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15

HMC1035LP6GEv010712














nspFns











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16

HMC1035LP6GEv010712




























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17

HMC1035LP6GEv010712





























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18

HMC1035LP6GEv010712







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19

HMC1035LP6GEv010712




















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20

HMC1035LP6GEv010712



















10 Pll register map









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HMC1035LP6GEv010712
















[130] rW rdiv 14 1




[180] rW intg 19 25d






[230] rW frac 24 0



min 0dmax 224-1








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HMC1035LP6GEv010712






[10] rW seed 2 2























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HMC1035LP6GEv010712














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24

HMC1035LP6GEv010712
















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25

HMC1035LP6GEv010712






























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26

HMC1035LP6GEv010712
















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27

HMC1035LP6GEv010712
















r Divider Cycles0 - 11 - 22 - 43 - 84 - 325 - 646 - 1287 - 256













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HMC1035LP6GEv010712































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29

HMC1035LP6GEv010712



















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30

HMC1035LP6GEv010712








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31

HMC1035LP6GEv010712

















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32

HMC1035LP6GEv010712








(Default 007FFFh)














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33

HMC1035LP6GEv010712





[81] Wo CaPs 8 16













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34

HMC1035LP6GEv010712

















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35

HMC1035LP6GEv010712






































Clo

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or

s -

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t

36

HMC1035LP6GEv010712


















Clo

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or

s -

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37

HMC1035LP6GEv010712







Clo

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or

s -

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t

38

HMC1035LP6GEv010712








Clo

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39

HMC1035LP6GEv010712






Clo

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40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




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3

HMC1035LP6GEv010712



















lVDs Mode 12 mV

lVPeCl Mode 20 V








20 524283












1 kHz -143 dBcHz



Logic Inputs


levels40 50 60 DVDD







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4

HMC1035LP6GEv010712




+ 33V supplies



315 33 35 V


+33V








termination173 ma


termination221 ma













107 fs


97 fs



125 fs


110 fs





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5

HMC1035LP6GEv010712



-180

-170

-160

-150

-140

-130

-120

-110

-100

1 10 100 1000 10000 100000

625 MHz_LVDS

625 MHz_LVPECL

2500 MHz_LVDS

2500 MHz_LVPECL

OFFSET(KHz)

PH

AS

E N

OIS

E(d

BcH

z)

-180

-170

-160

-150

-140

-130

-120

-110

-100

1 10 100 1000 10000 100000

625 MHz_LVDS

625 MHz_LVPECL

2500 MHz_LVDS

2500 MHz_LVPECL

OFFSET(KHz)

PH

AS

E N

OIS

E(d

BcH

z)

-180

-170

-160

-150

-140

-130

-120

-110

-100

1 10 100 1000 10000 100000


OFFSET(KHz)

PH

AS

E N

OIS

E(d

BcH

z)

-180

-170

-160

-150

-140

-130

-120

-110

-100

1 10 100 1000 10000 100000

62208 MHz_LVDS

62208 MHz_LVPECL

2500 MHz_LVDS

2500 MHz_LVPECL

OFFSET(KHz)

PH

AS

E N

OIS

E(d

BcH

z)

40

60

80

100

120

140

160

LVDS_PWR_PRI

LVDS_PERF_PRI

LVPECL_PWR_PRI

LVPECL_PWR_PRI

INT

EG

RA

TE

D R

MS

JIT

TE

R (

fs)

625

FREQUENCY (MHz)

2500

-180

-160

-140

-120

-100

-80

1 10 100 1000 10000 100000

XO

OCXO

OFFSET(KHz)

PH

AS

E N

OIS

E(d

BcH

z)









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6

HMC1035LP6GEv010712


-200

-150

-100

-50

0

50

100

150

200

-50 0 50 100 150 200 250 300

TIME( (uS)

PH

AS

E E

RR

OR

(D

EG

RE

E)

200

400

600

800

1000

1200

1400

100 1000

LVDS_PWR_PRI

LVDS_PERF_PRI

LVPECL_PWR_PRI

LVPECL_PERF_PRI

FRQUENCY (MHz)

Vp

pd

(m

V)

3000


40

60

80

100

120

140

160

LVDS_PWR_PRI

LVDS_PERF_PRI

LVPECL_PWR_PRI

LVPECL_PWR_PRI

INT

EG

RA

TE

D R

MS

JIT

TE

R (

fs)

250062208

FREQUENCY (MHz)

-50 0 50 100 150 200 250 300

TIME( (uS)

FR

EQ

UE

NC

Y E

RR

OR

(H

z)

2 109

60

80

100

120

140

160


RIS

E T

IME

(p

s)

250062208

FREQUENCY (MHz)

60

80

100

120

140

160


FA

LL

TIM

E (

ps)

250062208

FREQUENCY (MHz)








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HMC1035LP6GEv010712



C1 (pF)

C2 (nF)

C3 (pF)

C4 (pF)

r2 (Ω)

r3 (Ω)

r4 (Ω)

loop Filter Design

127 390 10 82 82 750 300 300

75 270 27 200 390 430 390 390


100

120

140

160

180

200

220


IDD(m

A)

Fo16 Fo4Fo8 FoFo2

FREQUENCY


47

48

49

50

51

52

LVDS_PWR_PRI

LVDS_PERF_PRI

LVPECL_PWR_PRI

LVPECL_PERF_PRI

DU

TY

CY

CL

E (

)

250062208

FREQUENCY (MHz)

-1500

-1000

-500

0

500

1000

1500

0 05 1 15 2 25 3

LVDS PERF PRI

LVDS PWR PRI

LVPECL PERF PRI

LVPECL PWR PRI

TIME (ns)

Vp

pd

(m

V)





500

1000

1500

2000

2500

3000

0 2 4 6 8 10

Vp

pd

(m

V)

27C

-40C

85C

GAIN SETTING STEP



Clo

Ck

Ge

ne

rat

or

s -

sM

t

8

HMC1035LP6GEv010712


outline Drawing

notes


sIlICon IMPreGnateD










-03V to +36V





10 degCW

reflow soldering








Package information



Clo

Ck

Ge

ne

rat

or

s -

sM

t

9

HMC1035LP6GEv010712


Pin Descriptions



2 5 6 8 9 11 - 14 18 - 22 24

26 34 37 38nC





















40 BIas





Clo

Ck

Ge

ne

rat

or

s -

sM

t

10

HMC1035LP6GEv010712







evaluation PcB



evaluation kit


ekIt01-HMC1035lP6Ge


eVal01-HMC1035lP6G

ekIt01-HMC1035lP6G





Clo

Ck

Ge

ne

rat

or

s -

sM

t

11

HMC1035LP6GEv010712










Clo

Ck

Ge

ne

rat

or

s -

sM

t

12

HMC1035LP6GEv010712










Clo

Ck

Ge

ne

rat

or

s -

sM

t

13

HMC1035LP6GEv010712


11 Serial Port







Multi-UserOpen Mode

reaDChip ID24-bits

Chip ID 24-bits

WRITEsoft reset

General strobes











Clo

Ck

Ge

ne

rat

or

s -

sM

t

14

HMC1035LP6GEv010712




















Clo

Ck

Ge

ne

rat

or

s -

sM

t

15

HMC1035LP6GEv010712














nspFns











Clo

Ck

Ge

ne

rat

or

s -

sM

t

16

HMC1035LP6GEv010712




























Clo

Ck

Ge

ne

rat

or

s -

sM

t

17

HMC1035LP6GEv010712





























Clo

Ck

Ge

ne

rat

or

s -

sM

t

18

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

19

HMC1035LP6GEv010712




















Clo

Ck

Ge

ne

rat

or

s -

sM

t

20

HMC1035LP6GEv010712



















10 Pll register map









Clo

Ck

Ge

ne

rat

or

s -

sM

t

21

HMC1035LP6GEv010712
















[130] rW rdiv 14 1




[180] rW intg 19 25d






[230] rW frac 24 0



min 0dmax 224-1








Clo

Ck

Ge

ne

rat

or

s -

sM

t

22

HMC1035LP6GEv010712






[10] rW seed 2 2























Clo

Ck

Ge

ne

rat

or

s -

sM

t

23

HMC1035LP6GEv010712














Clo

Ck

Ge

ne

rat

or

s -

sM

t

24

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

25

HMC1035LP6GEv010712






























Clo

Ck

Ge

ne

rat

or

s -

sM

t

26

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

27

HMC1035LP6GEv010712
















r Divider Cycles0 - 11 - 22 - 43 - 84 - 325 - 646 - 1287 - 256













Clo

Ck

Ge

ne

rat

or

s -

sM

t

28

HMC1035LP6GEv010712































Clo

Ck

Ge

ne

rat

or

s -

sM

t

29

HMC1035LP6GEv010712



















Clo

Ck

Ge

ne

rat

or

s -

sM

t

30

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

31

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

32

HMC1035LP6GEv010712








(Default 007FFFh)














Clo

Ck

Ge

ne

rat

or

s -

sM

t

33

HMC1035LP6GEv010712





[81] Wo CaPs 8 16













Clo

Ck

Ge

ne

rat

or

s -

sM

t

34

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

35

HMC1035LP6GEv010712






































Clo

Ck

Ge

ne

rat

or

s -

sM

t

36

HMC1035LP6GEv010712


















Clo

Ck

Ge

ne

rat

or

s -

sM

t

37

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

ne

rat

or

s -

sM

t

4

HMC1035LP6GEv010712




+ 33V supplies



315 33 35 V


+33V








termination173 ma


termination221 ma













107 fs


97 fs



125 fs


110 fs





Clo

Ck

Ge

ne

rat

or

s -

sM

t

5

HMC1035LP6GEv010712



-180

-170

-160

-150

-140

-130

-120

-110

-100

1 10 100 1000 10000 100000

625 MHz_LVDS

625 MHz_LVPECL

2500 MHz_LVDS

2500 MHz_LVPECL

OFFSET(KHz)

PH

AS

E N

OIS

E(d

BcH

z)

-180

-170

-160

-150

-140

-130

-120

-110

-100

1 10 100 1000 10000 100000

625 MHz_LVDS

625 MHz_LVPECL

2500 MHz_LVDS

2500 MHz_LVPECL

OFFSET(KHz)

PH

AS

E N

OIS

E(d

BcH

z)

-180

-170

-160

-150

-140

-130

-120

-110

-100

1 10 100 1000 10000 100000


OFFSET(KHz)

PH

AS

E N

OIS

E(d

BcH

z)

-180

-170

-160

-150

-140

-130

-120

-110

-100

1 10 100 1000 10000 100000

62208 MHz_LVDS

62208 MHz_LVPECL

2500 MHz_LVDS

2500 MHz_LVPECL

OFFSET(KHz)

PH

AS

E N

OIS

E(d

BcH

z)

40

60

80

100

120

140

160

LVDS_PWR_PRI

LVDS_PERF_PRI

LVPECL_PWR_PRI

LVPECL_PWR_PRI

INT

EG

RA

TE

D R

MS

JIT

TE

R (

fs)

625

FREQUENCY (MHz)

2500

-180

-160

-140

-120

-100

-80

1 10 100 1000 10000 100000

XO

OCXO

OFFSET(KHz)

PH

AS

E N

OIS

E(d

BcH

z)









Clo

Ck

Ge

ne

rat

or

s -

sM

t

6

HMC1035LP6GEv010712


-200

-150

-100

-50

0

50

100

150

200

-50 0 50 100 150 200 250 300

TIME( (uS)

PH

AS

E E

RR

OR

(D

EG

RE

E)

200

400

600

800

1000

1200

1400

100 1000

LVDS_PWR_PRI

LVDS_PERF_PRI

LVPECL_PWR_PRI

LVPECL_PERF_PRI

FRQUENCY (MHz)

Vp

pd

(m

V)

3000


40

60

80

100

120

140

160

LVDS_PWR_PRI

LVDS_PERF_PRI

LVPECL_PWR_PRI

LVPECL_PWR_PRI

INT

EG

RA

TE

D R

MS

JIT

TE

R (

fs)

250062208

FREQUENCY (MHz)

-50 0 50 100 150 200 250 300

TIME( (uS)

FR

EQ

UE

NC

Y E

RR

OR

(H

z)

2 109

60

80

100

120

140

160


RIS

E T

IME

(p

s)

250062208

FREQUENCY (MHz)

60

80

100

120

140

160


FA

LL

TIM

E (

ps)

250062208

FREQUENCY (MHz)








Clo

Ck

Ge

ne

rat

or

s -

sM

t

7

HMC1035LP6GEv010712



C1 (pF)

C2 (nF)

C3 (pF)

C4 (pF)

r2 (Ω)

r3 (Ω)

r4 (Ω)

loop Filter Design

127 390 10 82 82 750 300 300

75 270 27 200 390 430 390 390


100

120

140

160

180

200

220


IDD(m

A)

Fo16 Fo4Fo8 FoFo2

FREQUENCY


47

48

49

50

51

52

LVDS_PWR_PRI

LVDS_PERF_PRI

LVPECL_PWR_PRI

LVPECL_PERF_PRI

DU

TY

CY

CL

E (

)

250062208

FREQUENCY (MHz)

-1500

-1000

-500

0

500

1000

1500

0 05 1 15 2 25 3

LVDS PERF PRI

LVDS PWR PRI

LVPECL PERF PRI

LVPECL PWR PRI

TIME (ns)

Vp

pd

(m

V)





500

1000

1500

2000

2500

3000

0 2 4 6 8 10

Vp

pd

(m

V)

27C

-40C

85C

GAIN SETTING STEP



Clo

Ck

Ge

ne

rat

or

s -

sM

t

8

HMC1035LP6GEv010712


outline Drawing

notes


sIlICon IMPreGnateD










-03V to +36V





10 degCW

reflow soldering








Package information



Clo

Ck

Ge

ne

rat

or

s -

sM

t

9

HMC1035LP6GEv010712


Pin Descriptions



2 5 6 8 9 11 - 14 18 - 22 24

26 34 37 38nC





















40 BIas





Clo

Ck

Ge

ne

rat

or

s -

sM

t

10

HMC1035LP6GEv010712







evaluation PcB



evaluation kit


ekIt01-HMC1035lP6Ge


eVal01-HMC1035lP6G

ekIt01-HMC1035lP6G





Clo

Ck

Ge

ne

rat

or

s -

sM

t

11

HMC1035LP6GEv010712










Clo

Ck

Ge

ne

rat

or

s -

sM

t

12

HMC1035LP6GEv010712










Clo

Ck

Ge

ne

rat

or

s -

sM

t

13

HMC1035LP6GEv010712


11 Serial Port







Multi-UserOpen Mode

reaDChip ID24-bits

Chip ID 24-bits

WRITEsoft reset

General strobes











Clo

Ck

Ge

ne

rat

or

s -

sM

t

14

HMC1035LP6GEv010712




















Clo

Ck

Ge

ne

rat

or

s -

sM

t

15

HMC1035LP6GEv010712














nspFns











Clo

Ck

Ge

ne

rat

or

s -

sM

t

16

HMC1035LP6GEv010712




























Clo

Ck

Ge

ne

rat

or

s -

sM

t

17

HMC1035LP6GEv010712





























Clo

Ck

Ge

ne

rat

or

s -

sM

t

18

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

19

HMC1035LP6GEv010712




















Clo

Ck

Ge

ne

rat

or

s -

sM

t

20

HMC1035LP6GEv010712



















10 Pll register map









Clo

Ck

Ge

ne

rat

or

s -

sM

t

21

HMC1035LP6GEv010712
















[130] rW rdiv 14 1




[180] rW intg 19 25d






[230] rW frac 24 0



min 0dmax 224-1








Clo

Ck

Ge

ne

rat

or

s -

sM

t

22

HMC1035LP6GEv010712






[10] rW seed 2 2























Clo

Ck

Ge

ne

rat

or

s -

sM

t

23

HMC1035LP6GEv010712














Clo

Ck

Ge

ne

rat

or

s -

sM

t

24

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

25

HMC1035LP6GEv010712






























Clo

Ck

Ge

ne

rat

or

s -

sM

t

26

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

27

HMC1035LP6GEv010712
















r Divider Cycles0 - 11 - 22 - 43 - 84 - 325 - 646 - 1287 - 256













Clo

Ck

Ge

ne

rat

or

s -

sM

t

28

HMC1035LP6GEv010712































Clo

Ck

Ge

ne

rat

or

s -

sM

t

29

HMC1035LP6GEv010712



















Clo

Ck

Ge

ne

rat

or

s -

sM

t

30

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

31

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

32

HMC1035LP6GEv010712








(Default 007FFFh)














Clo

Ck

Ge

ne

rat

or

s -

sM

t

33

HMC1035LP6GEv010712





[81] Wo CaPs 8 16













Clo

Ck

Ge

ne

rat

or

s -

sM

t

34

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

35

HMC1035LP6GEv010712






































Clo

Ck

Ge

ne

rat

or

s -

sM

t

36

HMC1035LP6GEv010712


















Clo

Ck

Ge

ne

rat

or

s -

sM

t

37

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

ne

rat

or

s -

sM

t

5

HMC1035LP6GEv010712



-180

-170

-160

-150

-140

-130

-120

-110

-100

1 10 100 1000 10000 100000

625 MHz_LVDS

625 MHz_LVPECL

2500 MHz_LVDS

2500 MHz_LVPECL

OFFSET(KHz)

PH

AS

E N

OIS

E(d

BcH

z)

-180

-170

-160

-150

-140

-130

-120

-110

-100

1 10 100 1000 10000 100000

625 MHz_LVDS

625 MHz_LVPECL

2500 MHz_LVDS

2500 MHz_LVPECL

OFFSET(KHz)

PH

AS

E N

OIS

E(d

BcH

z)

-180

-170

-160

-150

-140

-130

-120

-110

-100

1 10 100 1000 10000 100000


OFFSET(KHz)

PH

AS

E N

OIS

E(d

BcH

z)

-180

-170

-160

-150

-140

-130

-120

-110

-100

1 10 100 1000 10000 100000

62208 MHz_LVDS

62208 MHz_LVPECL

2500 MHz_LVDS

2500 MHz_LVPECL

OFFSET(KHz)

PH

AS

E N

OIS

E(d

BcH

z)

40

60

80

100

120

140

160

LVDS_PWR_PRI

LVDS_PERF_PRI

LVPECL_PWR_PRI

LVPECL_PWR_PRI

INT

EG

RA

TE

D R

MS

JIT

TE

R (

fs)

625

FREQUENCY (MHz)

2500

-180

-160

-140

-120

-100

-80

1 10 100 1000 10000 100000

XO

OCXO

OFFSET(KHz)

PH

AS

E N

OIS

E(d

BcH

z)









Clo

Ck

Ge

ne

rat

or

s -

sM

t

6

HMC1035LP6GEv010712


-200

-150

-100

-50

0

50

100

150

200

-50 0 50 100 150 200 250 300

TIME( (uS)

PH

AS

E E

RR

OR

(D

EG

RE

E)

200

400

600

800

1000

1200

1400

100 1000

LVDS_PWR_PRI

LVDS_PERF_PRI

LVPECL_PWR_PRI

LVPECL_PERF_PRI

FRQUENCY (MHz)

Vp

pd

(m

V)

3000


40

60

80

100

120

140

160

LVDS_PWR_PRI

LVDS_PERF_PRI

LVPECL_PWR_PRI

LVPECL_PWR_PRI

INT

EG

RA

TE

D R

MS

JIT

TE

R (

fs)

250062208

FREQUENCY (MHz)

-50 0 50 100 150 200 250 300

TIME( (uS)

FR

EQ

UE

NC

Y E

RR

OR

(H

z)

2 109

60

80

100

120

140

160


RIS

E T

IME

(p

s)

250062208

FREQUENCY (MHz)

60

80

100

120

140

160


FA

LL

TIM

E (

ps)

250062208

FREQUENCY (MHz)








Clo

Ck

Ge

ne

rat

or

s -

sM

t

7

HMC1035LP6GEv010712



C1 (pF)

C2 (nF)

C3 (pF)

C4 (pF)

r2 (Ω)

r3 (Ω)

r4 (Ω)

loop Filter Design

127 390 10 82 82 750 300 300

75 270 27 200 390 430 390 390


100

120

140

160

180

200

220


IDD(m

A)

Fo16 Fo4Fo8 FoFo2

FREQUENCY


47

48

49

50

51

52

LVDS_PWR_PRI

LVDS_PERF_PRI

LVPECL_PWR_PRI

LVPECL_PERF_PRI

DU

TY

CY

CL

E (

)

250062208

FREQUENCY (MHz)

-1500

-1000

-500

0

500

1000

1500

0 05 1 15 2 25 3

LVDS PERF PRI

LVDS PWR PRI

LVPECL PERF PRI

LVPECL PWR PRI

TIME (ns)

Vp

pd

(m

V)





500

1000

1500

2000

2500

3000

0 2 4 6 8 10

Vp

pd

(m

V)

27C

-40C

85C

GAIN SETTING STEP



Clo

Ck

Ge

ne

rat

or

s -

sM

t

8

HMC1035LP6GEv010712


outline Drawing

notes


sIlICon IMPreGnateD










-03V to +36V





10 degCW

reflow soldering








Package information



Clo

Ck

Ge

ne

rat

or

s -

sM

t

9

HMC1035LP6GEv010712


Pin Descriptions



2 5 6 8 9 11 - 14 18 - 22 24

26 34 37 38nC





















40 BIas





Clo

Ck

Ge

ne

rat

or

s -

sM

t

10

HMC1035LP6GEv010712







evaluation PcB



evaluation kit


ekIt01-HMC1035lP6Ge


eVal01-HMC1035lP6G

ekIt01-HMC1035lP6G





Clo

Ck

Ge

ne

rat

or

s -

sM

t

11

HMC1035LP6GEv010712










Clo

Ck

Ge

ne

rat

or

s -

sM

t

12

HMC1035LP6GEv010712










Clo

Ck

Ge

ne

rat

or

s -

sM

t

13

HMC1035LP6GEv010712


11 Serial Port







Multi-UserOpen Mode

reaDChip ID24-bits

Chip ID 24-bits

WRITEsoft reset

General strobes











Clo

Ck

Ge

ne

rat

or

s -

sM

t

14

HMC1035LP6GEv010712




















Clo

Ck

Ge

ne

rat

or

s -

sM

t

15

HMC1035LP6GEv010712














nspFns











Clo

Ck

Ge

ne

rat

or

s -

sM

t

16

HMC1035LP6GEv010712




























Clo

Ck

Ge

ne

rat

or

s -

sM

t

17

HMC1035LP6GEv010712





























Clo

Ck

Ge

ne

rat

or

s -

sM

t

18

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

19

HMC1035LP6GEv010712




















Clo

Ck

Ge

ne

rat

or

s -

sM

t

20

HMC1035LP6GEv010712



















10 Pll register map









Clo

Ck

Ge

ne

rat

or

s -

sM

t

21

HMC1035LP6GEv010712
















[130] rW rdiv 14 1




[180] rW intg 19 25d






[230] rW frac 24 0



min 0dmax 224-1








Clo

Ck

Ge

ne

rat

or

s -

sM

t

22

HMC1035LP6GEv010712






[10] rW seed 2 2























Clo

Ck

Ge

ne

rat

or

s -

sM

t

23

HMC1035LP6GEv010712














Clo

Ck

Ge

ne

rat

or

s -

sM

t

24

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

25

HMC1035LP6GEv010712






























Clo

Ck

Ge

ne

rat

or

s -

sM

t

26

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

27

HMC1035LP6GEv010712
















r Divider Cycles0 - 11 - 22 - 43 - 84 - 325 - 646 - 1287 - 256













Clo

Ck

Ge

ne

rat

or

s -

sM

t

28

HMC1035LP6GEv010712































Clo

Ck

Ge

ne

rat

or

s -

sM

t

29

HMC1035LP6GEv010712



















Clo

Ck

Ge

ne

rat

or

s -

sM

t

30

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

31

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

32

HMC1035LP6GEv010712








(Default 007FFFh)














Clo

Ck

Ge

ne

rat

or

s -

sM

t

33

HMC1035LP6GEv010712





[81] Wo CaPs 8 16













Clo

Ck

Ge

ne

rat

or

s -

sM

t

34

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

35

HMC1035LP6GEv010712






































Clo

Ck

Ge

ne

rat

or

s -

sM

t

36

HMC1035LP6GEv010712


















Clo

Ck

Ge

ne

rat

or

s -

sM

t

37

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

ne

rat

or

s -

sM

t

6

HMC1035LP6GEv010712


-200

-150

-100

-50

0

50

100

150

200

-50 0 50 100 150 200 250 300

TIME( (uS)

PH

AS

E E

RR

OR

(D

EG

RE

E)

200

400

600

800

1000

1200

1400

100 1000

LVDS_PWR_PRI

LVDS_PERF_PRI

LVPECL_PWR_PRI

LVPECL_PERF_PRI

FRQUENCY (MHz)

Vp

pd

(m

V)

3000


40

60

80

100

120

140

160

LVDS_PWR_PRI

LVDS_PERF_PRI

LVPECL_PWR_PRI

LVPECL_PWR_PRI

INT

EG

RA

TE

D R

MS

JIT

TE

R (

fs)

250062208

FREQUENCY (MHz)

-50 0 50 100 150 200 250 300

TIME( (uS)

FR

EQ

UE

NC

Y E

RR

OR

(H

z)

2 109

60

80

100

120

140

160


RIS

E T

IME

(p

s)

250062208

FREQUENCY (MHz)

60

80

100

120

140

160


FA

LL

TIM

E (

ps)

250062208

FREQUENCY (MHz)








Clo

Ck

Ge

ne

rat

or

s -

sM

t

7

HMC1035LP6GEv010712



C1 (pF)

C2 (nF)

C3 (pF)

C4 (pF)

r2 (Ω)

r3 (Ω)

r4 (Ω)

loop Filter Design

127 390 10 82 82 750 300 300

75 270 27 200 390 430 390 390


100

120

140

160

180

200

220


IDD(m

A)

Fo16 Fo4Fo8 FoFo2

FREQUENCY


47

48

49

50

51

52

LVDS_PWR_PRI

LVDS_PERF_PRI

LVPECL_PWR_PRI

LVPECL_PERF_PRI

DU

TY

CY

CL

E (

)

250062208

FREQUENCY (MHz)

-1500

-1000

-500

0

500

1000

1500

0 05 1 15 2 25 3

LVDS PERF PRI

LVDS PWR PRI

LVPECL PERF PRI

LVPECL PWR PRI

TIME (ns)

Vp

pd

(m

V)





500

1000

1500

2000

2500

3000

0 2 4 6 8 10

Vp

pd

(m

V)

27C

-40C

85C

GAIN SETTING STEP



Clo

Ck

Ge

ne

rat

or

s -

sM

t

8

HMC1035LP6GEv010712


outline Drawing

notes


sIlICon IMPreGnateD










-03V to +36V





10 degCW

reflow soldering








Package information



Clo

Ck

Ge

ne

rat

or

s -

sM

t

9

HMC1035LP6GEv010712


Pin Descriptions



2 5 6 8 9 11 - 14 18 - 22 24

26 34 37 38nC





















40 BIas





Clo

Ck

Ge

ne

rat

or

s -

sM

t

10

HMC1035LP6GEv010712







evaluation PcB



evaluation kit


ekIt01-HMC1035lP6Ge


eVal01-HMC1035lP6G

ekIt01-HMC1035lP6G





Clo

Ck

Ge

ne

rat

or

s -

sM

t

11

HMC1035LP6GEv010712










Clo

Ck

Ge

ne

rat

or

s -

sM

t

12

HMC1035LP6GEv010712










Clo

Ck

Ge

ne

rat

or

s -

sM

t

13

HMC1035LP6GEv010712


11 Serial Port







Multi-UserOpen Mode

reaDChip ID24-bits

Chip ID 24-bits

WRITEsoft reset

General strobes











Clo

Ck

Ge

ne

rat

or

s -

sM

t

14

HMC1035LP6GEv010712




















Clo

Ck

Ge

ne

rat

or

s -

sM

t

15

HMC1035LP6GEv010712














nspFns











Clo

Ck

Ge

ne

rat

or

s -

sM

t

16

HMC1035LP6GEv010712




























Clo

Ck

Ge

ne

rat

or

s -

sM

t

17

HMC1035LP6GEv010712





























Clo

Ck

Ge

ne

rat

or

s -

sM

t

18

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

19

HMC1035LP6GEv010712




















Clo

Ck

Ge

ne

rat

or

s -

sM

t

20

HMC1035LP6GEv010712



















10 Pll register map









Clo

Ck

Ge

ne

rat

or

s -

sM

t

21

HMC1035LP6GEv010712
















[130] rW rdiv 14 1




[180] rW intg 19 25d






[230] rW frac 24 0



min 0dmax 224-1








Clo

Ck

Ge

ne

rat

or

s -

sM

t

22

HMC1035LP6GEv010712






[10] rW seed 2 2























Clo

Ck

Ge

ne

rat

or

s -

sM

t

23

HMC1035LP6GEv010712














Clo

Ck

Ge

ne

rat

or

s -

sM

t

24

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

25

HMC1035LP6GEv010712






























Clo

Ck

Ge

ne

rat

or

s -

sM

t

26

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

27

HMC1035LP6GEv010712
















r Divider Cycles0 - 11 - 22 - 43 - 84 - 325 - 646 - 1287 - 256













Clo

Ck

Ge

ne

rat

or

s -

sM

t

28

HMC1035LP6GEv010712































Clo

Ck

Ge

ne

rat

or

s -

sM

t

29

HMC1035LP6GEv010712



















Clo

Ck

Ge

ne

rat

or

s -

sM

t

30

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

31

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

32

HMC1035LP6GEv010712








(Default 007FFFh)














Clo

Ck

Ge

ne

rat

or

s -

sM

t

33

HMC1035LP6GEv010712





[81] Wo CaPs 8 16













Clo

Ck

Ge

ne

rat

or

s -

sM

t

34

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

35

HMC1035LP6GEv010712






































Clo

Ck

Ge

ne

rat

or

s -

sM

t

36

HMC1035LP6GEv010712


















Clo

Ck

Ge

ne

rat

or

s -

sM

t

37

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

ne

rat

or

s -

sM

t

7

HMC1035LP6GEv010712



C1 (pF)

C2 (nF)

C3 (pF)

C4 (pF)

r2 (Ω)

r3 (Ω)

r4 (Ω)

loop Filter Design

127 390 10 82 82 750 300 300

75 270 27 200 390 430 390 390


100

120

140

160

180

200

220


IDD(m

A)

Fo16 Fo4Fo8 FoFo2

FREQUENCY


47

48

49

50

51

52

LVDS_PWR_PRI

LVDS_PERF_PRI

LVPECL_PWR_PRI

LVPECL_PERF_PRI

DU

TY

CY

CL

E (

)

250062208

FREQUENCY (MHz)

-1500

-1000

-500

0

500

1000

1500

0 05 1 15 2 25 3

LVDS PERF PRI

LVDS PWR PRI

LVPECL PERF PRI

LVPECL PWR PRI

TIME (ns)

Vp

pd

(m

V)





500

1000

1500

2000

2500

3000

0 2 4 6 8 10

Vp

pd

(m

V)

27C

-40C

85C

GAIN SETTING STEP



Clo

Ck

Ge

ne

rat

or

s -

sM

t

8

HMC1035LP6GEv010712


outline Drawing

notes


sIlICon IMPreGnateD










-03V to +36V





10 degCW

reflow soldering








Package information



Clo

Ck

Ge

ne

rat

or

s -

sM

t

9

HMC1035LP6GEv010712


Pin Descriptions



2 5 6 8 9 11 - 14 18 - 22 24

26 34 37 38nC





















40 BIas





Clo

Ck

Ge

ne

rat

or

s -

sM

t

10

HMC1035LP6GEv010712







evaluation PcB



evaluation kit


ekIt01-HMC1035lP6Ge


eVal01-HMC1035lP6G

ekIt01-HMC1035lP6G





Clo

Ck

Ge

ne

rat

or

s -

sM

t

11

HMC1035LP6GEv010712










Clo

Ck

Ge

ne

rat

or

s -

sM

t

12

HMC1035LP6GEv010712










Clo

Ck

Ge

ne

rat

or

s -

sM

t

13

HMC1035LP6GEv010712


11 Serial Port







Multi-UserOpen Mode

reaDChip ID24-bits

Chip ID 24-bits

WRITEsoft reset

General strobes











Clo

Ck

Ge

ne

rat

or

s -

sM

t

14

HMC1035LP6GEv010712




















Clo

Ck

Ge

ne

rat

or

s -

sM

t

15

HMC1035LP6GEv010712














nspFns











Clo

Ck

Ge

ne

rat

or

s -

sM

t

16

HMC1035LP6GEv010712




























Clo

Ck

Ge

ne

rat

or

s -

sM

t

17

HMC1035LP6GEv010712





























Clo

Ck

Ge

ne

rat

or

s -

sM

t

18

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

19

HMC1035LP6GEv010712




















Clo

Ck

Ge

ne

rat

or

s -

sM

t

20

HMC1035LP6GEv010712



















10 Pll register map









Clo

Ck

Ge

ne

rat

or

s -

sM

t

21

HMC1035LP6GEv010712
















[130] rW rdiv 14 1




[180] rW intg 19 25d






[230] rW frac 24 0



min 0dmax 224-1








Clo

Ck

Ge

ne

rat

or

s -

sM

t

22

HMC1035LP6GEv010712






[10] rW seed 2 2























Clo

Ck

Ge

ne

rat

or

s -

sM

t

23

HMC1035LP6GEv010712














Clo

Ck

Ge

ne

rat

or

s -

sM

t

24

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

25

HMC1035LP6GEv010712






























Clo

Ck

Ge

ne

rat

or

s -

sM

t

26

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

27

HMC1035LP6GEv010712
















r Divider Cycles0 - 11 - 22 - 43 - 84 - 325 - 646 - 1287 - 256













Clo

Ck

Ge

ne

rat

or

s -

sM

t

28

HMC1035LP6GEv010712































Clo

Ck

Ge

ne

rat

or

s -

sM

t

29

HMC1035LP6GEv010712



















Clo

Ck

Ge

ne

rat

or

s -

sM

t

30

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

31

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

32

HMC1035LP6GEv010712








(Default 007FFFh)














Clo

Ck

Ge

ne

rat

or

s -

sM

t

33

HMC1035LP6GEv010712





[81] Wo CaPs 8 16













Clo

Ck

Ge

ne

rat

or

s -

sM

t

34

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

35

HMC1035LP6GEv010712






































Clo

Ck

Ge

ne

rat

or

s -

sM

t

36

HMC1035LP6GEv010712


















Clo

Ck

Ge

ne

rat

or

s -

sM

t

37

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

ne

rat

or

s -

sM

t

8

HMC1035LP6GEv010712


outline Drawing

notes


sIlICon IMPreGnateD










-03V to +36V





10 degCW

reflow soldering








Package information



Clo

Ck

Ge

ne

rat

or

s -

sM

t

9

HMC1035LP6GEv010712


Pin Descriptions



2 5 6 8 9 11 - 14 18 - 22 24

26 34 37 38nC





















40 BIas





Clo

Ck

Ge

ne

rat

or

s -

sM

t

10

HMC1035LP6GEv010712







evaluation PcB



evaluation kit


ekIt01-HMC1035lP6Ge


eVal01-HMC1035lP6G

ekIt01-HMC1035lP6G





Clo

Ck

Ge

ne

rat

or

s -

sM

t

11

HMC1035LP6GEv010712










Clo

Ck

Ge

ne

rat

or

s -

sM

t

12

HMC1035LP6GEv010712










Clo

Ck

Ge

ne

rat

or

s -

sM

t

13

HMC1035LP6GEv010712


11 Serial Port







Multi-UserOpen Mode

reaDChip ID24-bits

Chip ID 24-bits

WRITEsoft reset

General strobes











Clo

Ck

Ge

ne

rat

or

s -

sM

t

14

HMC1035LP6GEv010712




















Clo

Ck

Ge

ne

rat

or

s -

sM

t

15

HMC1035LP6GEv010712














nspFns











Clo

Ck

Ge

ne

rat

or

s -

sM

t

16

HMC1035LP6GEv010712




























Clo

Ck

Ge

ne

rat

or

s -

sM

t

17

HMC1035LP6GEv010712





























Clo

Ck

Ge

ne

rat

or

s -

sM

t

18

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

19

HMC1035LP6GEv010712




















Clo

Ck

Ge

ne

rat

or

s -

sM

t

20

HMC1035LP6GEv010712



















10 Pll register map









Clo

Ck

Ge

ne

rat

or

s -

sM

t

21

HMC1035LP6GEv010712
















[130] rW rdiv 14 1




[180] rW intg 19 25d






[230] rW frac 24 0



min 0dmax 224-1








Clo

Ck

Ge

ne

rat

or

s -

sM

t

22

HMC1035LP6GEv010712






[10] rW seed 2 2























Clo

Ck

Ge

ne

rat

or

s -

sM

t

23

HMC1035LP6GEv010712














Clo

Ck

Ge

ne

rat

or

s -

sM

t

24

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

25

HMC1035LP6GEv010712






























Clo

Ck

Ge

ne

rat

or

s -

sM

t

26

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

27

HMC1035LP6GEv010712
















r Divider Cycles0 - 11 - 22 - 43 - 84 - 325 - 646 - 1287 - 256













Clo

Ck

Ge

ne

rat

or

s -

sM

t

28

HMC1035LP6GEv010712































Clo

Ck

Ge

ne

rat

or

s -

sM

t

29

HMC1035LP6GEv010712



















Clo

Ck

Ge

ne

rat

or

s -

sM

t

30

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

31

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

32

HMC1035LP6GEv010712








(Default 007FFFh)














Clo

Ck

Ge

ne

rat

or

s -

sM

t

33

HMC1035LP6GEv010712





[81] Wo CaPs 8 16













Clo

Ck

Ge

ne

rat

or

s -

sM

t

34

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

35

HMC1035LP6GEv010712






































Clo

Ck

Ge

ne

rat

or

s -

sM

t

36

HMC1035LP6GEv010712


















Clo

Ck

Ge

ne

rat

or

s -

sM

t

37

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

ne

rat

or

s -

sM

t

9

HMC1035LP6GEv010712


Pin Descriptions



2 5 6 8 9 11 - 14 18 - 22 24

26 34 37 38nC





















40 BIas





Clo

Ck

Ge

ne

rat

or

s -

sM

t

10

HMC1035LP6GEv010712







evaluation PcB



evaluation kit


ekIt01-HMC1035lP6Ge


eVal01-HMC1035lP6G

ekIt01-HMC1035lP6G





Clo

Ck

Ge

ne

rat

or

s -

sM

t

11

HMC1035LP6GEv010712










Clo

Ck

Ge

ne

rat

or

s -

sM

t

12

HMC1035LP6GEv010712










Clo

Ck

Ge

ne

rat

or

s -

sM

t

13

HMC1035LP6GEv010712


11 Serial Port







Multi-UserOpen Mode

reaDChip ID24-bits

Chip ID 24-bits

WRITEsoft reset

General strobes











Clo

Ck

Ge

ne

rat

or

s -

sM

t

14

HMC1035LP6GEv010712




















Clo

Ck

Ge

ne

rat

or

s -

sM

t

15

HMC1035LP6GEv010712














nspFns











Clo

Ck

Ge

ne

rat

or

s -

sM

t

16

HMC1035LP6GEv010712




























Clo

Ck

Ge

ne

rat

or

s -

sM

t

17

HMC1035LP6GEv010712





























Clo

Ck

Ge

ne

rat

or

s -

sM

t

18

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

19

HMC1035LP6GEv010712




















Clo

Ck

Ge

ne

rat

or

s -

sM

t

20

HMC1035LP6GEv010712



















10 Pll register map









Clo

Ck

Ge

ne

rat

or

s -

sM

t

21

HMC1035LP6GEv010712
















[130] rW rdiv 14 1




[180] rW intg 19 25d






[230] rW frac 24 0



min 0dmax 224-1








Clo

Ck

Ge

ne

rat

or

s -

sM

t

22

HMC1035LP6GEv010712






[10] rW seed 2 2























Clo

Ck

Ge

ne

rat

or

s -

sM

t

23

HMC1035LP6GEv010712














Clo

Ck

Ge

ne

rat

or

s -

sM

t

24

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

25

HMC1035LP6GEv010712






























Clo

Ck

Ge

ne

rat

or

s -

sM

t

26

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

27

HMC1035LP6GEv010712
















r Divider Cycles0 - 11 - 22 - 43 - 84 - 325 - 646 - 1287 - 256













Clo

Ck

Ge

ne

rat

or

s -

sM

t

28

HMC1035LP6GEv010712































Clo

Ck

Ge

ne

rat

or

s -

sM

t

29

HMC1035LP6GEv010712



















Clo

Ck

Ge

ne

rat

or

s -

sM

t

30

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

31

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

32

HMC1035LP6GEv010712








(Default 007FFFh)














Clo

Ck

Ge

ne

rat

or

s -

sM

t

33

HMC1035LP6GEv010712





[81] Wo CaPs 8 16













Clo

Ck

Ge

ne

rat

or

s -

sM

t

34

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

35

HMC1035LP6GEv010712






































Clo

Ck

Ge

ne

rat

or

s -

sM

t

36

HMC1035LP6GEv010712


















Clo

Ck

Ge

ne

rat

or

s -

sM

t

37

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

ne

rat

or

s -

sM

t

10

HMC1035LP6GEv010712







evaluation PcB



evaluation kit


ekIt01-HMC1035lP6Ge


eVal01-HMC1035lP6G

ekIt01-HMC1035lP6G





Clo

Ck

Ge

ne

rat

or

s -

sM

t

11

HMC1035LP6GEv010712










Clo

Ck

Ge

ne

rat

or

s -

sM

t

12

HMC1035LP6GEv010712










Clo

Ck

Ge

ne

rat

or

s -

sM

t

13

HMC1035LP6GEv010712


11 Serial Port







Multi-UserOpen Mode

reaDChip ID24-bits

Chip ID 24-bits

WRITEsoft reset

General strobes











Clo

Ck

Ge

ne

rat

or

s -

sM

t

14

HMC1035LP6GEv010712




















Clo

Ck

Ge

ne

rat

or

s -

sM

t

15

HMC1035LP6GEv010712














nspFns











Clo

Ck

Ge

ne

rat

or

s -

sM

t

16

HMC1035LP6GEv010712




























Clo

Ck

Ge

ne

rat

or

s -

sM

t

17

HMC1035LP6GEv010712





























Clo

Ck

Ge

ne

rat

or

s -

sM

t

18

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

19

HMC1035LP6GEv010712




















Clo

Ck

Ge

ne

rat

or

s -

sM

t

20

HMC1035LP6GEv010712



















10 Pll register map









Clo

Ck

Ge

ne

rat

or

s -

sM

t

21

HMC1035LP6GEv010712
















[130] rW rdiv 14 1




[180] rW intg 19 25d






[230] rW frac 24 0



min 0dmax 224-1








Clo

Ck

Ge

ne

rat

or

s -

sM

t

22

HMC1035LP6GEv010712






[10] rW seed 2 2























Clo

Ck

Ge

ne

rat

or

s -

sM

t

23

HMC1035LP6GEv010712














Clo

Ck

Ge

ne

rat

or

s -

sM

t

24

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

25

HMC1035LP6GEv010712






























Clo

Ck

Ge

ne

rat

or

s -

sM

t

26

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

27

HMC1035LP6GEv010712
















r Divider Cycles0 - 11 - 22 - 43 - 84 - 325 - 646 - 1287 - 256













Clo

Ck

Ge

ne

rat

or

s -

sM

t

28

HMC1035LP6GEv010712































Clo

Ck

Ge

ne

rat

or

s -

sM

t

29

HMC1035LP6GEv010712



















Clo

Ck

Ge

ne

rat

or

s -

sM

t

30

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

31

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

32

HMC1035LP6GEv010712








(Default 007FFFh)














Clo

Ck

Ge

ne

rat

or

s -

sM

t

33

HMC1035LP6GEv010712





[81] Wo CaPs 8 16













Clo

Ck

Ge

ne

rat

or

s -

sM

t

34

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

35

HMC1035LP6GEv010712






































Clo

Ck

Ge

ne

rat

or

s -

sM

t

36

HMC1035LP6GEv010712


















Clo

Ck

Ge

ne

rat

or

s -

sM

t

37

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

ne

rat

or

s -

sM

t

11

HMC1035LP6GEv010712










Clo

Ck

Ge

ne

rat

or

s -

sM

t

12

HMC1035LP6GEv010712










Clo

Ck

Ge

ne

rat

or

s -

sM

t

13

HMC1035LP6GEv010712


11 Serial Port







Multi-UserOpen Mode

reaDChip ID24-bits

Chip ID 24-bits

WRITEsoft reset

General strobes











Clo

Ck

Ge

ne

rat

or

s -

sM

t

14

HMC1035LP6GEv010712




















Clo

Ck

Ge

ne

rat

or

s -

sM

t

15

HMC1035LP6GEv010712














nspFns











Clo

Ck

Ge

ne

rat

or

s -

sM

t

16

HMC1035LP6GEv010712




























Clo

Ck

Ge

ne

rat

or

s -

sM

t

17

HMC1035LP6GEv010712





























Clo

Ck

Ge

ne

rat

or

s -

sM

t

18

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

19

HMC1035LP6GEv010712




















Clo

Ck

Ge

ne

rat

or

s -

sM

t

20

HMC1035LP6GEv010712



















10 Pll register map









Clo

Ck

Ge

ne

rat

or

s -

sM

t

21

HMC1035LP6GEv010712
















[130] rW rdiv 14 1




[180] rW intg 19 25d






[230] rW frac 24 0



min 0dmax 224-1








Clo

Ck

Ge

ne

rat

or

s -

sM

t

22

HMC1035LP6GEv010712






[10] rW seed 2 2























Clo

Ck

Ge

ne

rat

or

s -

sM

t

23

HMC1035LP6GEv010712














Clo

Ck

Ge

ne

rat

or

s -

sM

t

24

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

25

HMC1035LP6GEv010712






























Clo

Ck

Ge

ne

rat

or

s -

sM

t

26

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

27

HMC1035LP6GEv010712
















r Divider Cycles0 - 11 - 22 - 43 - 84 - 325 - 646 - 1287 - 256













Clo

Ck

Ge

ne

rat

or

s -

sM

t

28

HMC1035LP6GEv010712































Clo

Ck

Ge

ne

rat

or

s -

sM

t

29

HMC1035LP6GEv010712



















Clo

Ck

Ge

ne

rat

or

s -

sM

t

30

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

31

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

32

HMC1035LP6GEv010712








(Default 007FFFh)














Clo

Ck

Ge

ne

rat

or

s -

sM

t

33

HMC1035LP6GEv010712





[81] Wo CaPs 8 16













Clo

Ck

Ge

ne

rat

or

s -

sM

t

34

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

35

HMC1035LP6GEv010712






































Clo

Ck

Ge

ne

rat

or

s -

sM

t

36

HMC1035LP6GEv010712


















Clo

Ck

Ge

ne

rat

or

s -

sM

t

37

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

ne

rat

or

s -

sM

t

12

HMC1035LP6GEv010712










Clo

Ck

Ge

ne

rat

or

s -

sM

t

13

HMC1035LP6GEv010712


11 Serial Port







Multi-UserOpen Mode

reaDChip ID24-bits

Chip ID 24-bits

WRITEsoft reset

General strobes











Clo

Ck

Ge

ne

rat

or

s -

sM

t

14

HMC1035LP6GEv010712




















Clo

Ck

Ge

ne

rat

or

s -

sM

t

15

HMC1035LP6GEv010712














nspFns











Clo

Ck

Ge

ne

rat

or

s -

sM

t

16

HMC1035LP6GEv010712




























Clo

Ck

Ge

ne

rat

or

s -

sM

t

17

HMC1035LP6GEv010712





























Clo

Ck

Ge

ne

rat

or

s -

sM

t

18

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

19

HMC1035LP6GEv010712




















Clo

Ck

Ge

ne

rat

or

s -

sM

t

20

HMC1035LP6GEv010712



















10 Pll register map









Clo

Ck

Ge

ne

rat

or

s -

sM

t

21

HMC1035LP6GEv010712
















[130] rW rdiv 14 1




[180] rW intg 19 25d






[230] rW frac 24 0



min 0dmax 224-1








Clo

Ck

Ge

ne

rat

or

s -

sM

t

22

HMC1035LP6GEv010712






[10] rW seed 2 2























Clo

Ck

Ge

ne

rat

or

s -

sM

t

23

HMC1035LP6GEv010712














Clo

Ck

Ge

ne

rat

or

s -

sM

t

24

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

25

HMC1035LP6GEv010712






























Clo

Ck

Ge

ne

rat

or

s -

sM

t

26

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

27

HMC1035LP6GEv010712
















r Divider Cycles0 - 11 - 22 - 43 - 84 - 325 - 646 - 1287 - 256













Clo

Ck

Ge

ne

rat

or

s -

sM

t

28

HMC1035LP6GEv010712































Clo

Ck

Ge

ne

rat

or

s -

sM

t

29

HMC1035LP6GEv010712



















Clo

Ck

Ge

ne

rat

or

s -

sM

t

30

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

31

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

32

HMC1035LP6GEv010712








(Default 007FFFh)














Clo

Ck

Ge

ne

rat

or

s -

sM

t

33

HMC1035LP6GEv010712





[81] Wo CaPs 8 16













Clo

Ck

Ge

ne

rat

or

s -

sM

t

34

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

35

HMC1035LP6GEv010712






































Clo

Ck

Ge

ne

rat

or

s -

sM

t

36

HMC1035LP6GEv010712


















Clo

Ck

Ge

ne

rat

or

s -

sM

t

37

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

ne

rat

or

s -

sM

t

13

HMC1035LP6GEv010712


11 Serial Port







Multi-UserOpen Mode

reaDChip ID24-bits

Chip ID 24-bits

WRITEsoft reset

General strobes











Clo

Ck

Ge

ne

rat

or

s -

sM

t

14

HMC1035LP6GEv010712




















Clo

Ck

Ge

ne

rat

or

s -

sM

t

15

HMC1035LP6GEv010712














nspFns











Clo

Ck

Ge

ne

rat

or

s -

sM

t

16

HMC1035LP6GEv010712




























Clo

Ck

Ge

ne

rat

or

s -

sM

t

17

HMC1035LP6GEv010712





























Clo

Ck

Ge

ne

rat

or

s -

sM

t

18

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

19

HMC1035LP6GEv010712




















Clo

Ck

Ge

ne

rat

or

s -

sM

t

20

HMC1035LP6GEv010712



















10 Pll register map









Clo

Ck

Ge

ne

rat

or

s -

sM

t

21

HMC1035LP6GEv010712
















[130] rW rdiv 14 1




[180] rW intg 19 25d






[230] rW frac 24 0



min 0dmax 224-1








Clo

Ck

Ge

ne

rat

or

s -

sM

t

22

HMC1035LP6GEv010712






[10] rW seed 2 2























Clo

Ck

Ge

ne

rat

or

s -

sM

t

23

HMC1035LP6GEv010712














Clo

Ck

Ge

ne

rat

or

s -

sM

t

24

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

25

HMC1035LP6GEv010712






























Clo

Ck

Ge

ne

rat

or

s -

sM

t

26

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

27

HMC1035LP6GEv010712
















r Divider Cycles0 - 11 - 22 - 43 - 84 - 325 - 646 - 1287 - 256













Clo

Ck

Ge

ne

rat

or

s -

sM

t

28

HMC1035LP6GEv010712































Clo

Ck

Ge

ne

rat

or

s -

sM

t

29

HMC1035LP6GEv010712



















Clo

Ck

Ge

ne

rat

or

s -

sM

t

30

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

31

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

32

HMC1035LP6GEv010712








(Default 007FFFh)














Clo

Ck

Ge

ne

rat

or

s -

sM

t

33

HMC1035LP6GEv010712





[81] Wo CaPs 8 16













Clo

Ck

Ge

ne

rat

or

s -

sM

t

34

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

35

HMC1035LP6GEv010712






































Clo

Ck

Ge

ne

rat

or

s -

sM

t

36

HMC1035LP6GEv010712


















Clo

Ck

Ge

ne

rat

or

s -

sM

t

37

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

ne

rat

or

s -

sM

t

14

HMC1035LP6GEv010712




















Clo

Ck

Ge

ne

rat

or

s -

sM

t

15

HMC1035LP6GEv010712














nspFns











Clo

Ck

Ge

ne

rat

or

s -

sM

t

16

HMC1035LP6GEv010712




























Clo

Ck

Ge

ne

rat

or

s -

sM

t

17

HMC1035LP6GEv010712





























Clo

Ck

Ge

ne

rat

or

s -

sM

t

18

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

19

HMC1035LP6GEv010712




















Clo

Ck

Ge

ne

rat

or

s -

sM

t

20

HMC1035LP6GEv010712



















10 Pll register map









Clo

Ck

Ge

ne

rat

or

s -

sM

t

21

HMC1035LP6GEv010712
















[130] rW rdiv 14 1




[180] rW intg 19 25d






[230] rW frac 24 0



min 0dmax 224-1








Clo

Ck

Ge

ne

rat

or

s -

sM

t

22

HMC1035LP6GEv010712






[10] rW seed 2 2























Clo

Ck

Ge

ne

rat

or

s -

sM

t

23

HMC1035LP6GEv010712














Clo

Ck

Ge

ne

rat

or

s -

sM

t

24

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

25

HMC1035LP6GEv010712






























Clo

Ck

Ge

ne

rat

or

s -

sM

t

26

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

27

HMC1035LP6GEv010712
















r Divider Cycles0 - 11 - 22 - 43 - 84 - 325 - 646 - 1287 - 256













Clo

Ck

Ge

ne

rat

or

s -

sM

t

28

HMC1035LP6GEv010712































Clo

Ck

Ge

ne

rat

or

s -

sM

t

29

HMC1035LP6GEv010712



















Clo

Ck

Ge

ne

rat

or

s -

sM

t

30

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

31

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

32

HMC1035LP6GEv010712








(Default 007FFFh)














Clo

Ck

Ge

ne

rat

or

s -

sM

t

33

HMC1035LP6GEv010712





[81] Wo CaPs 8 16













Clo

Ck

Ge

ne

rat

or

s -

sM

t

34

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

35

HMC1035LP6GEv010712






































Clo

Ck

Ge

ne

rat

or

s -

sM

t

36

HMC1035LP6GEv010712


















Clo

Ck

Ge

ne

rat

or

s -

sM

t

37

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

ne

rat

or

s -

sM

t

15

HMC1035LP6GEv010712














nspFns











Clo

Ck

Ge

ne

rat

or

s -

sM

t

16

HMC1035LP6GEv010712




























Clo

Ck

Ge

ne

rat

or

s -

sM

t

17

HMC1035LP6GEv010712





























Clo

Ck

Ge

ne

rat

or

s -

sM

t

18

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

19

HMC1035LP6GEv010712




















Clo

Ck

Ge

ne

rat

or

s -

sM

t

20

HMC1035LP6GEv010712



















10 Pll register map









Clo

Ck

Ge

ne

rat

or

s -

sM

t

21

HMC1035LP6GEv010712
















[130] rW rdiv 14 1




[180] rW intg 19 25d






[230] rW frac 24 0



min 0dmax 224-1








Clo

Ck

Ge

ne

rat

or

s -

sM

t

22

HMC1035LP6GEv010712






[10] rW seed 2 2























Clo

Ck

Ge

ne

rat

or

s -

sM

t

23

HMC1035LP6GEv010712














Clo

Ck

Ge

ne

rat

or

s -

sM

t

24

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

25

HMC1035LP6GEv010712






























Clo

Ck

Ge

ne

rat

or

s -

sM

t

26

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

27

HMC1035LP6GEv010712
















r Divider Cycles0 - 11 - 22 - 43 - 84 - 325 - 646 - 1287 - 256













Clo

Ck

Ge

ne

rat

or

s -

sM

t

28

HMC1035LP6GEv010712































Clo

Ck

Ge

ne

rat

or

s -

sM

t

29

HMC1035LP6GEv010712



















Clo

Ck

Ge

ne

rat

or

s -

sM

t

30

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

31

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

32

HMC1035LP6GEv010712








(Default 007FFFh)














Clo

Ck

Ge

ne

rat

or

s -

sM

t

33

HMC1035LP6GEv010712





[81] Wo CaPs 8 16













Clo

Ck

Ge

ne

rat

or

s -

sM

t

34

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

35

HMC1035LP6GEv010712






































Clo

Ck

Ge

ne

rat

or

s -

sM

t

36

HMC1035LP6GEv010712


















Clo

Ck

Ge

ne

rat

or

s -

sM

t

37

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

ne

rat

or

s -

sM

t

16

HMC1035LP6GEv010712




























Clo

Ck

Ge

ne

rat

or

s -

sM

t

17

HMC1035LP6GEv010712





























Clo

Ck

Ge

ne

rat

or

s -

sM

t

18

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

19

HMC1035LP6GEv010712




















Clo

Ck

Ge

ne

rat

or

s -

sM

t

20

HMC1035LP6GEv010712



















10 Pll register map









Clo

Ck

Ge

ne

rat

or

s -

sM

t

21

HMC1035LP6GEv010712
















[130] rW rdiv 14 1




[180] rW intg 19 25d






[230] rW frac 24 0



min 0dmax 224-1








Clo

Ck

Ge

ne

rat

or

s -

sM

t

22

HMC1035LP6GEv010712






[10] rW seed 2 2























Clo

Ck

Ge

ne

rat

or

s -

sM

t

23

HMC1035LP6GEv010712














Clo

Ck

Ge

ne

rat

or

s -

sM

t

24

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

25

HMC1035LP6GEv010712






























Clo

Ck

Ge

ne

rat

or

s -

sM

t

26

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

27

HMC1035LP6GEv010712
















r Divider Cycles0 - 11 - 22 - 43 - 84 - 325 - 646 - 1287 - 256













Clo

Ck

Ge

ne

rat

or

s -

sM

t

28

HMC1035LP6GEv010712































Clo

Ck

Ge

ne

rat

or

s -

sM

t

29

HMC1035LP6GEv010712



















Clo

Ck

Ge

ne

rat

or

s -

sM

t

30

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

31

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

32

HMC1035LP6GEv010712








(Default 007FFFh)














Clo

Ck

Ge

ne

rat

or

s -

sM

t

33

HMC1035LP6GEv010712





[81] Wo CaPs 8 16













Clo

Ck

Ge

ne

rat

or

s -

sM

t

34

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

35

HMC1035LP6GEv010712






































Clo

Ck

Ge

ne

rat

or

s -

sM

t

36

HMC1035LP6GEv010712


















Clo

Ck

Ge

ne

rat

or

s -

sM

t

37

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

ne

rat

or

s -

sM

t

17

HMC1035LP6GEv010712





























Clo

Ck

Ge

ne

rat

or

s -

sM

t

18

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

19

HMC1035LP6GEv010712




















Clo

Ck

Ge

ne

rat

or

s -

sM

t

20

HMC1035LP6GEv010712



















10 Pll register map









Clo

Ck

Ge

ne

rat

or

s -

sM

t

21

HMC1035LP6GEv010712
















[130] rW rdiv 14 1




[180] rW intg 19 25d






[230] rW frac 24 0



min 0dmax 224-1








Clo

Ck

Ge

ne

rat

or

s -

sM

t

22

HMC1035LP6GEv010712






[10] rW seed 2 2























Clo

Ck

Ge

ne

rat

or

s -

sM

t

23

HMC1035LP6GEv010712














Clo

Ck

Ge

ne

rat

or

s -

sM

t

24

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

25

HMC1035LP6GEv010712






























Clo

Ck

Ge

ne

rat

or

s -

sM

t

26

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

27

HMC1035LP6GEv010712
















r Divider Cycles0 - 11 - 22 - 43 - 84 - 325 - 646 - 1287 - 256













Clo

Ck

Ge

ne

rat

or

s -

sM

t

28

HMC1035LP6GEv010712































Clo

Ck

Ge

ne

rat

or

s -

sM

t

29

HMC1035LP6GEv010712



















Clo

Ck

Ge

ne

rat

or

s -

sM

t

30

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

31

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

32

HMC1035LP6GEv010712








(Default 007FFFh)














Clo

Ck

Ge

ne

rat

or

s -

sM

t

33

HMC1035LP6GEv010712





[81] Wo CaPs 8 16













Clo

Ck

Ge

ne

rat

or

s -

sM

t

34

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

35

HMC1035LP6GEv010712






































Clo

Ck

Ge

ne

rat

or

s -

sM

t

36

HMC1035LP6GEv010712


















Clo

Ck

Ge

ne

rat

or

s -

sM

t

37

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

ne

rat

or

s -

sM

t

18

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

19

HMC1035LP6GEv010712




















Clo

Ck

Ge

ne

rat

or

s -

sM

t

20

HMC1035LP6GEv010712



















10 Pll register map









Clo

Ck

Ge

ne

rat

or

s -

sM

t

21

HMC1035LP6GEv010712
















[130] rW rdiv 14 1




[180] rW intg 19 25d






[230] rW frac 24 0



min 0dmax 224-1








Clo

Ck

Ge

ne

rat

or

s -

sM

t

22

HMC1035LP6GEv010712






[10] rW seed 2 2























Clo

Ck

Ge

ne

rat

or

s -

sM

t

23

HMC1035LP6GEv010712














Clo

Ck

Ge

ne

rat

or

s -

sM

t

24

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

25

HMC1035LP6GEv010712






























Clo

Ck

Ge

ne

rat

or

s -

sM

t

26

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

27

HMC1035LP6GEv010712
















r Divider Cycles0 - 11 - 22 - 43 - 84 - 325 - 646 - 1287 - 256













Clo

Ck

Ge

ne

rat

or

s -

sM

t

28

HMC1035LP6GEv010712































Clo

Ck

Ge

ne

rat

or

s -

sM

t

29

HMC1035LP6GEv010712



















Clo

Ck

Ge

ne

rat

or

s -

sM

t

30

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

31

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

32

HMC1035LP6GEv010712








(Default 007FFFh)














Clo

Ck

Ge

ne

rat

or

s -

sM

t

33

HMC1035LP6GEv010712





[81] Wo CaPs 8 16













Clo

Ck

Ge

ne

rat

or

s -

sM

t

34

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

35

HMC1035LP6GEv010712






































Clo

Ck

Ge

ne

rat

or

s -

sM

t

36

HMC1035LP6GEv010712


















Clo

Ck

Ge

ne

rat

or

s -

sM

t

37

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

ne

rat

or

s -

sM

t

19

HMC1035LP6GEv010712




















Clo

Ck

Ge

ne

rat

or

s -

sM

t

20

HMC1035LP6GEv010712



















10 Pll register map









Clo

Ck

Ge

ne

rat

or

s -

sM

t

21

HMC1035LP6GEv010712
















[130] rW rdiv 14 1




[180] rW intg 19 25d






[230] rW frac 24 0



min 0dmax 224-1








Clo

Ck

Ge

ne

rat

or

s -

sM

t

22

HMC1035LP6GEv010712






[10] rW seed 2 2























Clo

Ck

Ge

ne

rat

or

s -

sM

t

23

HMC1035LP6GEv010712














Clo

Ck

Ge

ne

rat

or

s -

sM

t

24

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

25

HMC1035LP6GEv010712






























Clo

Ck

Ge

ne

rat

or

s -

sM

t

26

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

27

HMC1035LP6GEv010712
















r Divider Cycles0 - 11 - 22 - 43 - 84 - 325 - 646 - 1287 - 256













Clo

Ck

Ge

ne

rat

or

s -

sM

t

28

HMC1035LP6GEv010712































Clo

Ck

Ge

ne

rat

or

s -

sM

t

29

HMC1035LP6GEv010712



















Clo

Ck

Ge

ne

rat

or

s -

sM

t

30

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

31

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

32

HMC1035LP6GEv010712








(Default 007FFFh)














Clo

Ck

Ge

ne

rat

or

s -

sM

t

33

HMC1035LP6GEv010712





[81] Wo CaPs 8 16













Clo

Ck

Ge

ne

rat

or

s -

sM

t

34

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

35

HMC1035LP6GEv010712






































Clo

Ck

Ge

ne

rat

or

s -

sM

t

36

HMC1035LP6GEv010712


















Clo

Ck

Ge

ne

rat

or

s -

sM

t

37

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

ne

rat

or

s -

sM

t

20

HMC1035LP6GEv010712



















10 Pll register map









Clo

Ck

Ge

ne

rat

or

s -

sM

t

21

HMC1035LP6GEv010712
















[130] rW rdiv 14 1




[180] rW intg 19 25d






[230] rW frac 24 0



min 0dmax 224-1








Clo

Ck

Ge

ne

rat

or

s -

sM

t

22

HMC1035LP6GEv010712






[10] rW seed 2 2























Clo

Ck

Ge

ne

rat

or

s -

sM

t

23

HMC1035LP6GEv010712














Clo

Ck

Ge

ne

rat

or

s -

sM

t

24

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

25

HMC1035LP6GEv010712






























Clo

Ck

Ge

ne

rat

or

s -

sM

t

26

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

27

HMC1035LP6GEv010712
















r Divider Cycles0 - 11 - 22 - 43 - 84 - 325 - 646 - 1287 - 256













Clo

Ck

Ge

ne

rat

or

s -

sM

t

28

HMC1035LP6GEv010712































Clo

Ck

Ge

ne

rat

or

s -

sM

t

29

HMC1035LP6GEv010712



















Clo

Ck

Ge

ne

rat

or

s -

sM

t

30

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

31

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

32

HMC1035LP6GEv010712








(Default 007FFFh)














Clo

Ck

Ge

ne

rat

or

s -

sM

t

33

HMC1035LP6GEv010712





[81] Wo CaPs 8 16













Clo

Ck

Ge

ne

rat

or

s -

sM

t

34

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

35

HMC1035LP6GEv010712






































Clo

Ck

Ge

ne

rat

or

s -

sM

t

36

HMC1035LP6GEv010712


















Clo

Ck

Ge

ne

rat

or

s -

sM

t

37

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

ne

rat

or

s -

sM

t

21

HMC1035LP6GEv010712
















[130] rW rdiv 14 1




[180] rW intg 19 25d






[230] rW frac 24 0



min 0dmax 224-1








Clo

Ck

Ge

ne

rat

or

s -

sM

t

22

HMC1035LP6GEv010712






[10] rW seed 2 2























Clo

Ck

Ge

ne

rat

or

s -

sM

t

23

HMC1035LP6GEv010712














Clo

Ck

Ge

ne

rat

or

s -

sM

t

24

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

25

HMC1035LP6GEv010712






























Clo

Ck

Ge

ne

rat

or

s -

sM

t

26

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

27

HMC1035LP6GEv010712
















r Divider Cycles0 - 11 - 22 - 43 - 84 - 325 - 646 - 1287 - 256













Clo

Ck

Ge

ne

rat

or

s -

sM

t

28

HMC1035LP6GEv010712































Clo

Ck

Ge

ne

rat

or

s -

sM

t

29

HMC1035LP6GEv010712



















Clo

Ck

Ge

ne

rat

or

s -

sM

t

30

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

31

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

32

HMC1035LP6GEv010712








(Default 007FFFh)














Clo

Ck

Ge

ne

rat

or

s -

sM

t

33

HMC1035LP6GEv010712





[81] Wo CaPs 8 16













Clo

Ck

Ge

ne

rat

or

s -

sM

t

34

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

35

HMC1035LP6GEv010712






































Clo

Ck

Ge

ne

rat

or

s -

sM

t

36

HMC1035LP6GEv010712


















Clo

Ck

Ge

ne

rat

or

s -

sM

t

37

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

ne

rat

or

s -

sM

t

22

HMC1035LP6GEv010712






[10] rW seed 2 2























Clo

Ck

Ge

ne

rat

or

s -

sM

t

23

HMC1035LP6GEv010712














Clo

Ck

Ge

ne

rat

or

s -

sM

t

24

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

25

HMC1035LP6GEv010712






























Clo

Ck

Ge

ne

rat

or

s -

sM

t

26

HMC1035LP6GEv010712
















Clo

Ck

Ge

ne

rat

or

s -

sM

t

27

HMC1035LP6GEv010712
















r Divider Cycles0 - 11 - 22 - 43 - 84 - 325 - 646 - 1287 - 256













Clo

Ck

Ge

ne

rat

or

s -

sM

t

28

HMC1035LP6GEv010712































Clo

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s -

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HMC1035LP6GEv010712



















Clo

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HMC1035LP6GEv010712








Clo

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rat

or

s -

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t

31

HMC1035LP6GEv010712

















Clo

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HMC1035LP6GEv010712








(Default 007FFFh)














Clo

Ck

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rat

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s -

sM

t

33

HMC1035LP6GEv010712





[81] Wo CaPs 8 16













Clo

Ck

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rat

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s -

sM

t

34

HMC1035LP6GEv010712

















Clo

Ck

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s -

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t

35

HMC1035LP6GEv010712






































Clo

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rat

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s -

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t

36

HMC1035LP6GEv010712


















Clo

Ck

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rat

or

s -

sM

t

37

HMC1035LP6GEv010712







Clo

Ck

Ge

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rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

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rat

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s -

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23

HMC1035LP6GEv010712














Clo

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HMC1035LP6GEv010712
















Clo

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s -

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25

HMC1035LP6GEv010712






























Clo

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s -

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t

26

HMC1035LP6GEv010712
















Clo

Ck

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rat

or

s -

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t

27

HMC1035LP6GEv010712
















r Divider Cycles0 - 11 - 22 - 43 - 84 - 325 - 646 - 1287 - 256













Clo

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rat

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s -

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HMC1035LP6GEv010712































Clo

Ck

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s -

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HMC1035LP6GEv010712



















Clo

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HMC1035LP6GEv010712








Clo

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s -

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31

HMC1035LP6GEv010712

















Clo

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32

HMC1035LP6GEv010712








(Default 007FFFh)














Clo

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s -

sM

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33

HMC1035LP6GEv010712





[81] Wo CaPs 8 16













Clo

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s -

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34

HMC1035LP6GEv010712

















Clo

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s -

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HMC1035LP6GEv010712






































Clo

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s -

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HMC1035LP6GEv010712


















Clo

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s -

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37

HMC1035LP6GEv010712







Clo

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s -

sM

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38

HMC1035LP6GEv010712








Clo

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rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

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rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

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rat

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s -

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24

HMC1035LP6GEv010712
















Clo

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HMC1035LP6GEv010712






























Clo

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s -

sM

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26

HMC1035LP6GEv010712
















Clo

Ck

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rat

or

s -

sM

t

27

HMC1035LP6GEv010712
















r Divider Cycles0 - 11 - 22 - 43 - 84 - 325 - 646 - 1287 - 256













Clo

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rat

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s -

sM

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28

HMC1035LP6GEv010712































Clo

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HMC1035LP6GEv010712



















Clo

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HMC1035LP6GEv010712








Clo

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31

HMC1035LP6GEv010712

















Clo

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HMC1035LP6GEv010712








(Default 007FFFh)














Clo

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s -

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33

HMC1035LP6GEv010712





[81] Wo CaPs 8 16













Clo

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s -

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34

HMC1035LP6GEv010712

















Clo

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s -

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35

HMC1035LP6GEv010712






































Clo

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s -

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HMC1035LP6GEv010712


















Clo

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s -

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37

HMC1035LP6GEv010712







Clo

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s -

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38

HMC1035LP6GEv010712








Clo

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Ge

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rat

or

s -

sM

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39

HMC1035LP6GEv010712






Clo

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Ge

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rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

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rat

or

s -

sM

t

25

HMC1035LP6GEv010712






























Clo

Ck

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s -

sM

t

26

HMC1035LP6GEv010712
















Clo

Ck

Ge

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rat

or

s -

sM

t

27

HMC1035LP6GEv010712
















r Divider Cycles0 - 11 - 22 - 43 - 84 - 325 - 646 - 1287 - 256













Clo

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Ge

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rat

or

s -

sM

t

28

HMC1035LP6GEv010712































Clo

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rat

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s -

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29

HMC1035LP6GEv010712



















Clo

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s -

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t

30

HMC1035LP6GEv010712








Clo

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s -

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31

HMC1035LP6GEv010712

















Clo

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s -

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HMC1035LP6GEv010712








(Default 007FFFh)














Clo

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Ge

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rat

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s -

sM

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33

HMC1035LP6GEv010712





[81] Wo CaPs 8 16













Clo

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Ge

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rat

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s -

sM

t

34

HMC1035LP6GEv010712

















Clo

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rat

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s -

sM

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35

HMC1035LP6GEv010712






































Clo

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s -

sM

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36

HMC1035LP6GEv010712


















Clo

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rat

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s -

sM

t

37

HMC1035LP6GEv010712







Clo

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s -

sM

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38

HMC1035LP6GEv010712








Clo

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Ge

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rat

or

s -

sM

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39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

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rat

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s -

sM

t

26

HMC1035LP6GEv010712
















Clo

Ck

Ge

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rat

or

s -

sM

t

27

HMC1035LP6GEv010712
















r Divider Cycles0 - 11 - 22 - 43 - 84 - 325 - 646 - 1287 - 256













Clo

Ck

Ge

ne

rat

or

s -

sM

t

28

HMC1035LP6GEv010712































Clo

Ck

Ge

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rat

or

s -

sM

t

29

HMC1035LP6GEv010712



















Clo

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rat

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s -

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t

30

HMC1035LP6GEv010712








Clo

Ck

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rat

or

s -

sM

t

31

HMC1035LP6GEv010712

















Clo

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s -

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32

HMC1035LP6GEv010712








(Default 007FFFh)














Clo

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Ge

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rat

or

s -

sM

t

33

HMC1035LP6GEv010712





[81] Wo CaPs 8 16













Clo

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Ge

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rat

or

s -

sM

t

34

HMC1035LP6GEv010712

















Clo

Ck

Ge

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rat

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s -

sM

t

35

HMC1035LP6GEv010712






































Clo

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Ge

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rat

or

s -

sM

t

36

HMC1035LP6GEv010712


















Clo

Ck

Ge

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rat

or

s -

sM

t

37

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

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rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

ne

rat

or

s -

sM

t

27

HMC1035LP6GEv010712
















r Divider Cycles0 - 11 - 22 - 43 - 84 - 325 - 646 - 1287 - 256













Clo

Ck

Ge

ne

rat

or

s -

sM

t

28

HMC1035LP6GEv010712































Clo

Ck

Ge

ne

rat

or

s -

sM

t

29

HMC1035LP6GEv010712



















Clo

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Ge

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rat

or

s -

sM

t

30

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

31

HMC1035LP6GEv010712

















Clo

Ck

Ge

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rat

or

s -

sM

t

32

HMC1035LP6GEv010712








(Default 007FFFh)














Clo

Ck

Ge

ne

rat

or

s -

sM

t

33

HMC1035LP6GEv010712





[81] Wo CaPs 8 16













Clo

Ck

Ge

ne

rat

or

s -

sM

t

34

HMC1035LP6GEv010712

















Clo

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rat

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s -

sM

t

35

HMC1035LP6GEv010712






































Clo

Ck

Ge

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rat

or

s -

sM

t

36

HMC1035LP6GEv010712


















Clo

Ck

Ge

ne

rat

or

s -

sM

t

37

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

ne

rat

or

s -

sM

t

28

HMC1035LP6GEv010712































Clo

Ck

Ge

ne

rat

or

s -

sM

t

29

HMC1035LP6GEv010712



















Clo

Ck

Ge

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rat

or

s -

sM

t

30

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

31

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

32

HMC1035LP6GEv010712








(Default 007FFFh)














Clo

Ck

Ge

ne

rat

or

s -

sM

t

33

HMC1035LP6GEv010712





[81] Wo CaPs 8 16













Clo

Ck

Ge

ne

rat

or

s -

sM

t

34

HMC1035LP6GEv010712

















Clo

Ck

Ge

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rat

or

s -

sM

t

35

HMC1035LP6GEv010712






































Clo

Ck

Ge

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rat

or

s -

sM

t

36

HMC1035LP6GEv010712


















Clo

Ck

Ge

ne

rat

or

s -

sM

t

37

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

ne

rat

or

s -

sM

t

29

HMC1035LP6GEv010712



















Clo

Ck

Ge

ne

rat

or

s -

sM

t

30

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

31

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

32

HMC1035LP6GEv010712








(Default 007FFFh)














Clo

Ck

Ge

ne

rat

or

s -

sM

t

33

HMC1035LP6GEv010712





[81] Wo CaPs 8 16













Clo

Ck

Ge

ne

rat

or

s -

sM

t

34

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

35

HMC1035LP6GEv010712






































Clo

Ck

Ge

ne

rat

or

s -

sM

t

36

HMC1035LP6GEv010712


















Clo

Ck

Ge

ne

rat

or

s -

sM

t

37

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

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rat

or

s -

sM

t

30

HMC1035LP6GEv010712








Clo

Ck

Ge

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rat

or

s -

sM

t

31

HMC1035LP6GEv010712

















Clo

Ck

Ge

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rat

or

s -

sM

t

32

HMC1035LP6GEv010712








(Default 007FFFh)














Clo

Ck

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rat

or

s -

sM

t

33

HMC1035LP6GEv010712





[81] Wo CaPs 8 16













Clo

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rat

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s -

sM

t

34

HMC1035LP6GEv010712

















Clo

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rat

or

s -

sM

t

35

HMC1035LP6GEv010712






































Clo

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rat

or

s -

sM

t

36

HMC1035LP6GEv010712


















Clo

Ck

Ge

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rat

or

s -

sM

t

37

HMC1035LP6GEv010712







Clo

Ck

Ge

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rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

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rat

or

s -

sM

t

31

HMC1035LP6GEv010712

















Clo

Ck

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rat

or

s -

sM

t

32

HMC1035LP6GEv010712








(Default 007FFFh)














Clo

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Ge

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rat

or

s -

sM

t

33

HMC1035LP6GEv010712





[81] Wo CaPs 8 16













Clo

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Ge

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rat

or

s -

sM

t

34

HMC1035LP6GEv010712

















Clo

Ck

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rat

or

s -

sM

t

35

HMC1035LP6GEv010712






































Clo

Ck

Ge

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rat

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s -

sM

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36

HMC1035LP6GEv010712


















Clo

Ck

Ge

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rat

or

s -

sM

t

37

HMC1035LP6GEv010712







Clo

Ck

Ge

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rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

ne

rat

or

s -

sM

t

32

HMC1035LP6GEv010712








(Default 007FFFh)














Clo

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Ge

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rat

or

s -

sM

t

33

HMC1035LP6GEv010712





[81] Wo CaPs 8 16













Clo

Ck

Ge

ne

rat

or

s -

sM

t

34

HMC1035LP6GEv010712

















Clo

Ck

Ge

ne

rat

or

s -

sM

t

35

HMC1035LP6GEv010712






































Clo

Ck

Ge

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rat

or

s -

sM

t

36

HMC1035LP6GEv010712


















Clo

Ck

Ge

ne

rat

or

s -

sM

t

37

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

ne

rat

or

s -

sM

t

33

HMC1035LP6GEv010712





[81] Wo CaPs 8 16













Clo

Ck

Ge

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rat

or

s -

sM

t

34

HMC1035LP6GEv010712

















Clo

Ck

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rat

or

s -

sM

t

35

HMC1035LP6GEv010712






































Clo

Ck

Ge

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rat

or

s -

sM

t

36

HMC1035LP6GEv010712


















Clo

Ck

Ge

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rat

or

s -

sM

t

37

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

ne

rat

or

s -

sM

t

34

HMC1035LP6GEv010712

















Clo

Ck

Ge

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rat

or

s -

sM

t

35

HMC1035LP6GEv010712






































Clo

Ck

Ge

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rat

or

s -

sM

t

36

HMC1035LP6GEv010712


















Clo

Ck

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rat

or

s -

sM

t

37

HMC1035LP6GEv010712







Clo

Ck

Ge

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rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

ne

rat

or

s -

sM

t

35

HMC1035LP6GEv010712






































Clo

Ck

Ge

ne

rat

or

s -

sM

t

36

HMC1035LP6GEv010712


















Clo

Ck

Ge

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rat

or

s -

sM

t

37

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

ne

rat

or

s -

sM

t

36

HMC1035LP6GEv010712


















Clo

Ck

Ge

ne

rat

or

s -

sM

t

37

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

ne

rat

or

s -

sM

t

37

HMC1035LP6GEv010712







Clo

Ck

Ge

ne

rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

ne

rat

or

s -

sM

t

38

HMC1035LP6GEv010712








Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

ne

rat

or

s -

sM

t

39

HMC1035LP6GEv010712






Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit




Clo

Ck

Ge

ne

rat

or

s -

sM

t

40

HMC1035LP6GEv010712




otU2 10709 66931 16733

otU2e 11095 69344 17336

otU1e 11049 69056 17264

otU2f 11317 70731 17683

otU1f 1127 70438 17609

otU3 43018 268863 67216

otU4 111809 174702

otU4v 127156 198682

SONETSDH

sts-192stM-64 995328 62208 15552

sts-768stM-256 3981312 248832 62208

Ethernet

10Ge lan 103125 15625

10Ge Wan 995328 62208 15552

XaUI (4 x 3125G) 3125 15625

40Ge (4 x 10G) 103125 15625

100Ge (4 x 25G) 2578125 80566 15625

Fibre Channel (FC)

10GFC 1052 16438

16GFC 14025 2125

32GFC 285 425


Features

Functional Diagram

General Description


Figure of Merit



Outline Drawing

Package Information

Pin Descriptions

Evaluation PCB











VCO Output Divider


Phase Detector (PD)

Charge Pump

Logic Inputs

Logic Outputs



Power on Reset

Figure of Merit


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