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Markus Stocklas Digital Vertrieb Agilent Technologies Böblingen HighSpeed aus dem Bereich Oszilloskope & Digitaltechnik

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Page 1: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Markus Stocklas

Digital Vertrieb

Agilent Technologies Böblingen

HighSpeed aus dem Bereich Oszilloskope &

Digitaltechnik

Page 2: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Agilent Oscilloscopes - Industry’s Largest Portfolio

Economy 20MHz – 200MHz

U1600A Series

Handheld

U2700 Series

USB

InfiniiVision 70MHz – 1GHz

7000 Series

3000X Series 6000/6000L Series

Infiniium 600MHz – 80GHz

DCA-X Series

90000 Series

9000 Series

90000 Q-Series

September 1, 2010

Fastest Growing Scope Company

2000X Series

New

New

New

90000 X-Series

Page 3: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Probe amps InfiniiMax III probe

amps – 16 GHz, 20

GHz, 25 GHz, 30 GHz

InfiniiMax III Series Probing System

Precision BNC 50 ohm

adapter

Sampling scope

Adapter

Hi impedance probe

adapter Probe adapters

InfiniiMax III

ZIF (zero

insertion force)

probe head

28 GHz InfiniiMax III

ZIF probe tips

2.92mm /3.5mm/SMA

Probe adapter

28 GHz

Performance verification

& Deskew fixture

Solder-in

Probe head

16 GHz

Probe heads

Browser

30 GHz

• 4 models

• 16 GHz - 30 GHz

• Bandwidth

upgradeable

Page 4: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

The 90000 Q-Series Overview Orderable: February 1st / Public Intro April 11th

DSO/DSA 92004Q 92504Q 93304Q 95004Q 95004Q

2 Channel BW 20 GHz 25 GHz 33 GHz 50 GHz 63 GHz

4 Channel BW 20 GHz 25 GHz 33 GHz 33 GHz 33 GHz

Sample Rate (2/4 ch) 80 / 80 GS 160 / 80 GS

Memory Depth

(Std/Max)

20 Mpts DSO / 50 Mpts DSA to 2 Gpts Max Memory

Depth

Noise at 50 mV/div 0.375% 0.435% 0.502% 1.185% >1.185%

Jitter Measurement

Floor

75 fS

Maximum Probing BW 30 GHz

PrecisionProbe

Enabled

Yes to 63 GHz

Page 5: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

The Q-Series

Upgradable from 20 GHz to 63 GHz in the

following step:

20 to 25 GHz

25 to 33 GHz

33 to 50 GHz

50 to 63 GHz

The 90000 X to Q Series

Upgradable at two bandwidth points:

20 to 20 GHz

33 to 33 GHz

Upgradeability

Page 6: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

InP Benefits

• Captive

process

• High-speed &

high-voltage

• Flat response

• Extensible

InP

Chipset

Trigger IC

ADC Amp

Input Preamp

Sampling DeMux

Probe Amp

Calibration IC

IC Process Performance

Indium Phosphide

Chips

Technology Leveraged from the 90000 X-Series Orderable: February 1st / Public Intro April 11th

Page 7: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Quick Film 3D Packaging

• Custom Agilent

technology

• Exceptional signal

integrity

• Substrate keeps chipset

cool and reliable

InP

Chipset

Trigger IC

ADC Amp

Input Preamp

Sampling DeMux

Probe Amp

Calibration IC

IC Packaging

Technology Leveraged from the 90000 X-Series Orderable: February 1st / Public Intro April 11th

Page 8: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

The World’s Fastest

Most Accurate

Oscilloscope

Differentiating Technology…

• Exclusive 33 GHz InP preamplifier

• Packaged for highest signal integrity

• Pipelined A/D architecture

Enables Differentiating Performance…

• True-analog bandwidth to 63 GHz

• Industry leading low-noise & jitter

• Industry’s only 30 GHz probing system

In The World’s Fastest and Most Accurate Scope

InP

Chipset

Trigger IC

ADC Amp

Input Preamp

Sampling DeMux

Probe Amp

Calibration IC

Technology Leveraged from the 90000 X-Series Orderable: February 1st / Public Intro April 11th

Page 9: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

5.1 ps rise time (20/80)

60 GHz sine wave

First Demonstrated Measurements at > 60 GHz Orderable: February 1st / Public Intro April 11th

Page 10: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Challenges In Digital Design Today

2.5 Gb/s

5 Gb/s

8 Gb/s

2003 2008

2006 2011

2009 2014

PCI Express

10

HIT 2011 Agilent Restricted

March 2011

Higher Data Rates Are Causing Signal

Integrity (SI) Problems: Signal Integrity = Where the electrical properties of the

interconnects can cause significant distortions in digital signals.

• >1 GHz of bandwidth

• <1 ns risetime

• Typically >2 Gb/s data rate with embedded clock

Signal Integrity = Paying attention to RF effects, ie. Impedance

FPGAs Are Commonplace

Standards Evolve Every 2-3 Years:

Page 11: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Page 11

• ‘Jitter ‘ is another word for shaky, quiver,

tremulous… speaks of degree of instability

of location.

• In the Digital Design world, jitter has been

defined as:

The short term phase variation of the

significant instants of a digital signal from

their ideal positions in time.

What is Jitter?

What is an Eye Diagram?

Page 12: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Page 12

How Do Real Time Scopes Measure Jitter on Data?

Jitter

Trend

NRZ

Serial

Data

Recovered

Clock

Jitter

Spectrum

Units in Time

Units in Time

Jitter

Histogram

Page 13: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Page 13

How Do Real Time Scopes Measure Jitter on Data?

Jitter

Trend

NRZ

Serial

Data

Recovered

Clock

Jitter

Spectrum

Units in Time

Units in Time

Jitter

Histogram

Page 14: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Page 14

Where Does Jitter Come From?

Transmitter Receiver

•Thermal Noise (RJ)

•DutyCycle Distortion (DCD)

•Power Supply Noise (RJ, PJ)

•On chip coupling (PJ)

•Lossy interconnect (ISI)

•Impedance mismatches (ISI)

•Crosstalk (PJ)

•Termination Errors (ISI)

•Thermal Noise (RJ)

•DutyCycle Distortion (DCD)

•Power Supply Noise (RJ, PJ)

•On chip coupling (PJ)

Media

Page 15: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Page 15

Single

transition

The EYE Diagram Unit Interval

Overlaid

transitions

Ideal Sampling Point

x = 0

Eye Crossing

Points

x = Tx = 1/2 T

Left Edge Right EdgeNominal

Sampling Point

E1

E0

Oscilloscope Eye

Probability Density Function

The Eye Diagram and Sampling Point

Total Jitter, JPP

Page 16: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Page 16

What is the Eye Diagram?

1 0 0

0 0 1

0 1 0

0 1 1

0 0 0

1 0 1

1 1 0

1 1 1

Superimposed Bit Sequences

Eye Diagrams

ADVA Training 86100C DCA-J Basics

Page 17: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Page 17

Why Do We Care About Jitter?

A low “Signal to Noise Ratio” causes

errors

– Voltage Noise vertical

fluctuations across the sampling

point

– Undesirable Amplitude Modulation

• Jitter describes the same effect but

horizontally – timing noise

– Jitter horizontal fluctuations

across the sampling point

– Undesirable Phase Modulation

• The only reason we analyze jitter is to Limit the Bit Error Ratio!

Page 18: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Page 18

You can’t know unless you measure the Total

Jitter or measure the jitter components!

Which Eye Has Worse Jitter?

A B

Page 19: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Deterministic

Jitter (DJ)

Random

Jitter (RJ)

Inter-symbol

Interference (ISI)

Duty Cycle

Distortion (DCD)

Signal jitter can be composed of several types from several mechanisms

Periodic

Jitter PJ

Data-Correlated Data-Uncorrelated

Total

Jitter (TJ)

jB(t) jUB(t)

jB(t)=A sin(2pft) jB(t)= d

jUB(t)= Gaussian

jB(t)=f(BW, data)

jB(t)

Decomposing Jitter

Page 20: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Agilent

Fixture De-embedding & Equalization

Page 21: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Source of Measurement Inaccuracies

•impedance mismatches

•probing effects

•smaller geometries

•test cables and adapters

•fixturing

•device packaging, etc.

•SCOPE NOISE FLOOR!

There are multiple ways to offset these measurement impairments.

calibration methods

mathematical signal processing

de-embedding/embedding techniques

Scope noise can be amplified

by de-embedding techniques

Page 22: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

PHY PHY

De-embedding – Loss Compensation or

Gain Function (De-convolve)

Tx Rx

Con

ne

cto

r

Con

ne

cto

r

Channel

• Compensate for Probing and Fixture

Loss – Add Margin to Transmitter

Characterization

• PCI Express , SATA, and Custom

• Compliance Requirement for Gen 2, 3 S4P

Page 23: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

PHY PHY

Embedding – Loss Function

(Convolve)

Tx Rx

Con

ne

cto

r

Con

ne

cto

r

Channel

Virtual Probe and De-

emphasis/Equalization

• Simulate Channel Loss on

Signal Measured at Tx

• Simulate Equalization/De-

emphasis at Rx

Virtual Probe

Tx

Signal

Rx

Equalization

TP1

TP2

TP3

TP2 TP3

Connector Pin Rx

TP1

Channel.s4p+

conn.s4p+package.s4p

Page 24: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Waveform Transformation

Waveform Transformation maps an acquired waveform to

another waveform mathematically using a transfer function

model of the customer’s system.

The system may be real using actual customer components or

may be virtual. Components may be described using RLC or

S-Parameters. M

Connector Fixture Cable

Digital Source

Cable

Model

Look Here Look Here Look Here

And Look Here!

Page 25: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Product Briefing for N5465A

InfiniiSim Waveform Transformation Toolset enables our

customers to define the measurement environment to obtain

the best measurement possible.

Listen for these words:

- ‘De-Embedding’

- ‘Fixture Removal’

- ‘Cable Insertion’

- ‘Virtual Probing’

- ‘Probe Loading

compensation’ Measure anywhere!

Page 26: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

<Product> Position versus other Agilent Products

<Visual of where <product> is positioned in product family>

Probe at BGA

Probe at VIA

De-embed Probe

RT BGA = 390 ps

RT VIA = 183 ps

RT De-embed = 175 ps

Page 27: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Serial Data Equalization Software for

Infiniium Series Oscilloscopes

DFE

CTLE

FFE

automatic tap optimization

Up to 40 Tabs

Page 28: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Transmitter De-emphasis

De-emphasis on, measured at receiver

De-emphasis off, measured at receiver

De-emphasis on, measured at transmitter

• We can account for loss through

the channel at the transmitter with

transmitter de-emphasis.

• De-emphasis is also called pre-

emphasis.

• The amount of de-emphasis may

be programmable.

Page 29: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Key measure is eye quality

Unequalized 1Gb/s Unequalized 3Gb/s

Unequalized 8Gb/s Unequalized 5Gb/s

Page 30: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

e(t) is the equalized waveform at time t

r(t-nTD) is the input waveform n tap delays

before the present time

Cn is the nth coefficient (tap)

TD is the tap delay

Each voltage level is multiplied by its corresponding tap value

and then all of these products are summed together to give

the new equalized voltage for the location of interest

Feed-Forward Equalization

Page 31: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Decision Feedback Equalization

V(k) is the correction voltage added to the decision threshold used

when determining the logic value of bit k.

r(t) is the un-

equalized analog

waveform voltage

at time t

s(k – n) is the logic value (either upper

target or lower target) for the bit n tap

delays prior to the current bit

Cn is the nth

coefficient (tap)

Each previous bit used in the algorithm is determined to be either

high or low and is then multiplied by its corresponding tap value.

These voltage/tap products are summed to determine how much

to shift the waveform relative to the logical decision threshold.

Page 32: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Differentiation between FFE & DFE

• Uses voltage levels of the

received waveform associated

with previous and current bits

to correct the voltage level of

the current bit

• 2x taps can open up the eye

dramatically

• Makes logical decisions (zero

or one) and then feeds that

information back to help

determinie whether the current

bit is a 1 or 0.

• The only location of the eye

that a receiver sees is at the

clock (center of the eye).

Page 33: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

N5461A SDE software: Equalization for 5Gb/s

Unequalized(5Gb/s): upper left

FFE: lower middle

• 2 taps

• Eye width of 1/3

DFE: lower right

• 3 taps

• Eye width of 0

FFE DFE

Page 34: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Equalizer Setup Window for FFE and DFE settings

Page 35: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Precision Probe Characterize and correct for cable, switch, and test fixture loss using only an oscilloscope

Page 36: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

The Importance of a Flat Frequency Response

Why do we care about a flat

frequency response?

- The flatter the response the

more accurately the scope will

depict the signal

- Measurements become more

repeatable

Frequency response of the Agilent 90000 X-

Series

Page 37: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Cables and channels are lossy

Response of cable rated to 20 GHz

Notice that the 3dB down

point is actually at 18 GHz

instead of 20 GHz

Bandwidth roll-off means

attenuated signal at high

bandwidth

Frequency response is not

flat

Page 38: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Every input path in a switch can vary

A real life example:

112 different inputs, every

one with slightly different

loss, phase, and response

characteristics

Measurements can from

channel to channel

Technologies continue to

push us to use more inputs

(for example: PCIE gen3

now has 16 inputs)

How much actual bandwidth does this system have?

Page 39: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Customer thought: 12 GHz BW

Actual: 4.5 GHz BW

Every input path in a switch can vary

A real life example:

112 different inputs, every

one with slightly different

loss, phase, and response

characteristics

Measurements can from

channel to channel

Technologies continue to

push us to use more inputs

(for example: PCIE gen3

now has 16 inputs)

Page 40: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Why is this an issue?

Inaccurate, non-repeatable measurements

Solution?

The solution is to:

1. Understand what the characteristic of the system is, and

2. Compensate for this system variation

Page 42: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

How it works

Agilent’s 90000 X-

Series uses its

world class 200

GHz Indium

Phosphide

technology to

provide a <15ps

edge to the

oscilloscope

Calibration edge is

then measured by

the 90000 X-Series

Lo

ssy c

ab

le is

the

n

me

asu

red

aga

inst th

e

“fast e

dge

Fast edge or

Baseline

Edge with

lossy cable

Comparing the

baseline measurement

with the cables

influence, proper

characterization is

done and corrections

can be made

Infiniium’s custom InP

calibration edge

Page 43: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

PrecisionProbe: 3 Easy Steps

1. Measure baseline

2. Measure loss due to cable

3. Save File

Page 44: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Cables: The result

Response of cable

with no correction

Corrected cable response

Applied corrected filter

Page 45: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Cable correction results

Before

PrecisionProbe

After

PrecisionProbe

S21 cable loss is removed

through compensation

Rise Time improves from 67 ps to

21 ps!

Page 46: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Jitter results

Before PrecisionProbe

After PrecisionProbe

S21 cable loss is removed through

compensation

Notice how there is 50% less ISI on the

corrected waveform, resulting in less Total

Jitter

Page 47: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

The real time eye

Results: More margins!

20% less jitter

33% more eye height

Slightly wider eye

Page 48: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Cabled Environment Benefits

By characterizing and

compensating for cable

loss increased margins.

Higher accuracy

Faster than traditional

VNA/de-embedding method

Page 50: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Measuring the Probe

1. Measure baseline

2. Measure loss due to probe

3. Save File

No probe

Probe

Improve your measurement quality

Page 51: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Probe characterization: final results

Transfer function of probe

with no correction

1. Transfer function is now flat for the entire bandwdith of the probe

2. 6dB of loss is now compensated

Page 52: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Summary:

1. Cables, probes, fixtures, switches

are lossy and cause

measurement errors

2. Traditional de-embedding

technology is time-consuming

and equipment intensive.

3. Precision Probe make de-

embedded incredibly simply.

Uncorrected

Corrected

PrecisionProbe will further

increase your margins without

adding significant time or extra

equipment

Page 53: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Protocol Decode on the Infiniium Series USB 2.0 Example

53

The competition has no

equivalent for any of these

Agilent protocol features.

Payload view Header view

With formatted

frame content

Search by

packet type

Jump to

next search

Multi-tab protocol

viewer, time aligned

with analog

Page 54: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Agilent Decode Ease-of-Use Advantage

This button automatically sets up the

scope parameters for your specific

decode. With this Auto Setup button, you

can be decoding data in less than a

minute.

If you want to see what values were set

during the Auto Setup process or if you

want to change certain parameters, use

this Manual Setup button.

Setup multiple decodes simultaneously

and quickly switch back and forth between

them in the Decode Listing window.

Page 55: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Infiniium Protocol Analysis

Timecorrelated

Protocol detailled level

Search and capture

Multi Serial Bus

Colorcoded representation

Available for ALL (most) serial protocolls:

Page 56: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Supports both MSO Digital and Analog Channels I2C + SPI Example

Using MSO

channels for

protocol decode

Using analog

channels for

protocol decode

Page 57: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

View decode in waveform area, or.......

Page 58: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Simultaneous decode of up to 4 Serial Buses

• Protocol trigger/decode sources can come from any of the following:

– 4 analog channels +16 digital + 4 functions + 4 waveform memories

• Anticipated usage primarily for protocols with explicit clocks such as I2C, SPI,

CAN, LIN, MIPI, USB 2.0, RS-232/UART...

Page 59: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

InfiniScan – the real nice way to trigger !!

Apply up to 8 Zone to trigger the signal individually

Trigger on Measurement parameters

Find and trigger non-monotic Edges

Serial Pattern Trigger

Page 60: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

InfiniScan – the real nice way to trigger !!

Page 61: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

• Vinyl record

• Videotape

• Photo Camera

• Cellphone

• CD

• DVD, Blue Ray

• Digital Camera

• Digital Cellphone

1 1 1 1 0 0

1. Analog continues to go digital

2. More integration at lower cost

3. Higher speed and lower power

4. High reliability delivered in less time

Market Trends

Page 62: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Ecosystem

Page 63: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Agilent Digital Test Standards Program

We’re active in standards meetings, workshops, plugfests, and seminars

Our solutions are driven and supported by Agilent experts involved in

international standards committees:

• Joint Electronic Devices Engineering Council (JEDEC)

• PCI Special Interest Group (PCI-SIG®)

• Video Electronics Standards Association (VESA)

• Serial ATA International Organization (SATA-IO)

• USB-Implementers Forum (USB-IF)

• Mobile Industry Processor Interface (MIPI) Alliance

• Optical Internetworking Forum (OIF)

Our customers test with highest confidence and achieve compliance faster

Page 64: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Jim Choate

USB-IF Compliance Committee

USB 3.0 Electrical Test Spec WG

Rick Eads

PCI-Sig Board

Member

Brian Fetz

DisplayPort Phy CTS Editor

VESA Board Member

Min-Jie Chong

SATA/SAS PHY Contributor

MIPI-PHY WG Contributor

The Agilent Pyramid team maintains engagement in the top high tech

standards organizations

Page 64

SATA / SAS Test Challenges

Agilent Restricted

We understand your future requirements, because we help

shape them

Roland Scherzinger

MIPI Contributor

Page 65: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

A Digital system: Serial Data Link

Die Bonding

wire/pins

PC

transmission

line

Standard

connector

PC

transmission

line Cable

Standard

connector

Bonding

wire/pins Die

Life Cycle of a Transported bit…

Starts in here… …and ends in here

March 2011 Page 65

HIT 2011 Agilent Restricted

Page 66: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Bit Error Ratio Testers (BERTs) 86100D Infiniium DCA-X

More Info

A range of essential tools—measurement and

simulation—that will help you cut through the

challenges of gigabit digital designs.

HIT 2011 Agilent Restricted

ADS

EMPro, and

SystemVue

Infiniium 90000 X-Series

ENA-TDR

N1930B Physical Layer

Test System (PLTS)

16900 Series Logic Analyzers

Pulse Pattern Generator

66

www.Agilent.com/find/hsd

Blog: http://Signal-Integrity.TM.Agilent.com

March 2011

Page 67: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

-or- -or-

SuperSpeed Communication – Physical Layer Focus

Super

Speed

Non-

Super

Speed

Super

Speed

Non-

Super

Speed

TX

TX

RX

RX

TX

RX

TX RX RX TX

Point to point communication, concurrent data flow

Low power mode

Link training

Independent clock domains – both using Spread Spectrum Clocking (SSC)

Transmitter (TX)

• De-emphasis

• 8B/10B coding

• Data scrambling

• Insertion of Skip

Cable / Channel

• Backward compatible

• EMI requirements

• Signal integrity requirements

Receiver (RX)

• Channel equalization

• Clock recovery

• Re-timing

(deletion or insertion of

addition Skips)

How to handle USB 3.0 physical

layer test requirements

October 28, 2009

Page 68: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

-or-

Super

Speed

Non-

Super

Speed

RX

TX

TX

RX

-or-

Super

Speed

Non-

Super

Speed

TX

RX

TX

RX

Physical Layer Test Solutions

Trans-

mitter

(TX)

Receiver

(RX) Channel / Cable

• Agilent 90000 series Infiniium

Oscilloscopes

• Agilent U7243A USB 3.0

Transmitter Compliance Test

Software

• Agilent E5071C Network

Analyzer

• 86100C DCA-J TDR

All physical layer tests: test

adapter

• Agilent U7242A USB 3.0 Test

Fixture

How to handle USB 3.0 physical

layer test requirements

October 28, 2009

• Agilent J-BERT N4903B

with

N4916A/B

De-emphasis

Signal

Converter

• Agilent 81250A

ParBERT

• N5990A Automated

Compliance and

Characterization Test

Software

Page 69: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Transmitter Compliance Testing:

Compliance will be measured at the end of the “compliance channel”

SMA termination for TX signals, phase matched SMA cable

Terminate link under test with high speed oscilloscope

Measure transmitted waveform with high speed oscilloscope

Use compliance pattern

1M UI of data

Compute:

eye diagram,

Rj, Dj, Tj@10^-12 BER,

average data rate,

rise/fall time,

Test requirement for SSC Slew Rate

Page 69

USB 3.0 Technical Review

. 2009

SuperSpeed Measurement Requirements

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Page 70

USB 3.0 Technical Review

. 2009

Transmitter test requirements

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Page 71

USB 3.0 Technical Review

. 2009

Compliance Channels

•Compliance Channels are being developed to test

SQ for worst case channel conditions

•Back panel USB route solution

•Channel loss will dominate

•Front Panel USB route solution

•Reflections will dominate losses

Front Panel

Back Panel

Page 72: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Page 72

USB 3.0 Technical Review

. 2009

USB 3.0 Test fixture

Support for Tx and Rx Testing

– SMA edge launch terminations

– SS A and SS B for host, device or cross hub testing

– USB 3.0 Test Fixtures (available now) – Early Customer Needs and Development

72

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Page 73

USB 3.0 Technical Review

. 2009

Normative Transmitter Compliance Test

Setup

DSO 90K

Scope

TP0

Scope SMA

SMA

Scope

Page 74: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Page 74

USB 3.0 Technical Review

. 2009

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Page 75

USB 3.0 Technical Review

. 2009

-0.35

Summary report of testing with Statistics

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Page 76

USB 3.0 Technical Review

. 2009

TX Compliance Test

With USB Org Test Tool

Agilent TX Compliance and Validation

Solution Report Summary

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USB 3.0 Protocol Decode: on scope

Page 77

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Eliminate All Doubt:

5Gb/s Test Signal Example

TP

1 Channe

l

50Ω

50Ω

N4915A-005

Switch

trigger

+

- RX

+

- TX

SS

Tes

t Ada

pter

1

4

3

No SSC, Sj / Rj shown on screen shots

2

How to handle USB 3.0 physical

layer test requirements

October 28, 2009

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Typical SuperSpeed Link Turn-on Sequence

Power-up

Complianc

e

Rx.

Detect.

Reset

Rx.

Detect.

Active

Rx.

Detect.

Reset

Rx.

Detect.

Active

Polling.

LFPS

Polling.

RxEQ

Polling.

Active

Polling.

Config-

uration

Polling.

Idle

Polling.

LFPS

Polling.

RxEQ

Polling.

Active

Polling.

Config-

uration

Polling.

Idle

Loopback

Loopback

Power-up

warm

reset

warm reset

de-assert

termination

detected

LFPS

handshake

TSEQ

transmitted

TS1

received

TS2

received if directed

multiple states

Host

Device

How to handle USB 3.0 physical

layer test requirements

October 28, 2009

LTSSM states:

Page 80: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Characteristical Eye Closure by Sinusoidal Jitter

BER Scan

Eye Diagram

How to handle USB 3.0 physical

layer test requirements

October 28, 2009

Page 81: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

skp skp

s k p skp

s k p s k p

skp skp

skp skp

skp skp

skp skp skp skp

Why is Spread Spectrum Clocking Included in

Receiver Compliance Test? SSC stresses clock recovery and elastic buffer, required for compliance test

Max. SSC deviation is 5000ppm, modulation rate between 30kHz and 33kHz

Nominal data rate: 5Gb/s

Frequency downspread:

5000ppm i.e. 4.975Gb/s

Receiver (RX) elastic buffer

compensates for clock difference

Data with SSC at receiver (RX) pins

-or-

Non-SS

TX

RX SuperSpeed

TX

loop-

back

RX

error

count

read

Original un-modulated data at 5Gb/s

1 1 2

2

Receiver FF

CR

EQ

How to handle USB 3.0 physical

layer test requirements

October 28, 2009

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Characteristical Eye Closure by Random Jitter

BER Scan

Eye Diagram

unbounded Rj

bounded Rj

How to handle USB 3.0 physical

layer test requirements

October 28, 2009

Page 83: HighSpeed aus dem Bereich Oszilloskope...•Typically >2 Gb/s data rate with embedded clock ... Impedance FPGAs Are Commonplace ... another waveform mathematically using a transfer

Hands-on in der Ausstellung

Herzlichen Dank für Ihr Interesse

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Page 84

USB 3.0 Technical Review

. 2009

Thank you for Attending

Questions?