High Speed VLSI Simulator Qi Chen, Pan Zhang Supervisor: Prof. Sourajeet Roy

Department of Computer and Electrical Engineering Colorado State University

Background

References

Objectives

Frequency Domain Analysis

Conclusion

Fall Semester • Design and develop a general purpose circuit

simulator capable of CAD of high-speed interconnect

• Frequency domain and time domain simulation • Single conductor and multi conductor

simulation Spring Semester

• Reduce computation cost by investigating Model Order Reduction(MOR) method

• Reduces the number of unknowns to significantly decrease computation time

Coupled Interconnect Simulation Time Domain Analysis

Model Order Reduction

[1] E. Lelarasmee, A. E. Ruehli, and A. L. Sangiovanni-Vincentelli, “The waveform relaxation method for time-domain analysis of large-scale integrated circuits,” IEEE Trans. CAD Integr. Circuits Syst., vol. 1, no. 3,pp. 131–145, Jul. 1982.

[2] J. White and A. L. Sangiovanni-Vincentelli, Relaxation Techniques for the Simulation of VLSI Circuits. Norwell, MA: Kluwer, 1987.

[3] Roy, Sourajeet. “Chapter 1: Formulation of Network Equations.” 2014 [4] Roy, Sourajeet. “Chapter 3: Numerical Integration Techniques of

Differential Equations.” 2014 [5] Roy, Sourajeet. “Chapter 5 High Speed Interconnects.” 2014

Tools • Programs written in C++ and operates on

CSU’s CRAY supercomputer • Usage of an industry standard, HSPICE, as a

result reference Mathematical Models

• Modified Nodal Analysis • ODE circuit representation and solution • PDE representation of transmission lines

Technical Performance Measurements • Accuracy • CPU time • Stability of the simulation results

Methods

Interconnects • transmission lines, copper wires, and Carbon

nano-tubes • Board to board, chip to chip, PCB, on chip

level High-speed

• High frequency clock rates • Short signal rise-time

Current Challenges • The lack of efficient methods of characterizing

interconnects. No exact time domain solution exists, and is currently done by discretizing PDE to approximate to its ODE representation.

• Distributed element, tradeoffs between CPU cost and accuracy

Mathematical representation • Layout to “Stamp”(MNA/ODE model) • Laplace domain • LU decomposition to solve the equation

Mathematical representation • Using existing models from frequency domain

analysis • Using implicit numerical integration methods

to approximate time domain solution o Backwards Euler method

The coupled multi-conductor circuits are analyzed and simulated in the time domain using the lumped model which is derived from Telegrapher’s partial differential equation with inductive and capacitive coupled effects, and solved using Backward Euler. This part of the solver is tested using the following test module. The coupled voltage is shown below.

V3

𝐺𝐺𝐺𝐺 + 𝐶𝐶𝑑𝑑𝐺𝐺𝑑𝑑𝑑𝑑

= 𝐵𝐵𝐵𝐵, 𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜 𝑠𝑠𝑜𝑜𝑜𝑜𝑠𝑠𝑠𝑠𝑜𝑜 𝐺𝐺 = 𝑄𝑄𝑄𝑄 ,𝑀𝑀𝑀𝑀𝑀𝑀

𝐺𝐺𝑟𝑟𝑄𝑄 + 𝐶𝐶𝑟𝑟𝑑𝑑𝑄𝑄𝑑𝑑𝑑𝑑

= 𝐵𝐵𝑟𝑟𝐵𝐵 dim (𝑄𝑄) ≪ dim (𝐺𝐺)

The objective of developing a general VLSI circuit simulator with ability to perform CAD of high-speed interconnects and optional model order reduction capability have been completed successfully. This will become a continuation project for future senior design teams to implement non-linear circuit simulation and parallel computation.

Original CPU Cost = 1.16 hrs

MOR Reduced CPU Cost = 0.04 hrs

MOR Original CPU Cost = 8.38 hrs

Reduced CPU Cost = 1.21 hrs

Model order reduction method essentially reduces the number of unknowns such as the node voltages and branch currents. This method is used to significantly decrease computation time for both time and frequency domain analysis. It utilizes the projection of matrix onto its Krylov Subspace and finding it’s ortho-normalized matrix Q with reduced number of columns. In this case, we chose the reduced number of columns to be 400 for both the frequency and time domain analysis of the 6 conductor testing module. The reduced CPU cost is shown above.