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High Speed Image Acquisition System for Focal-Plane-Arrays

Doctoral Dissertation Presentation

byYoungjoong Joo

School of Electrical and Computer EngineeringGeorgia Institute of Technology

February 12, 1999

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Outlines

Introduction

Background

Readout system architectures

Compact ovrsampling conversion

Photodetectors

Test

Conclusion and future work

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Introduction

MotivationConventional focal-plane-arrays (FPAs) readout methods

are not suitable for some scientific and engineering

applications.

Low readout speed

1MHz 1000X1000 14 bit images 62THz

Not scalable depending on the readout architecture

Noise sensitive

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Introduction

Objective

Design a new high speed scalable image acquisition system for FPAs.

High frame rates (> 100kfps)

Scalable

Low noise

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Background

A/DConverters

A/DConverters

ReadoutSystems

ReadoutSystems

Photo detectors

DSPDSP

Block diagram

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Photo detectors

Readout/Multiplexer To Preamp, ADC

Photon Flux

Detector Array

Hybrid integration

High responsivity

High fill factor

Substrate must be transparent

Higher fabrication cost

Generate electronic signals and are located at the front end of the image acquisition system.

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Photo detectors

Readout/Multiplexer

Detector /Circuit

Monomaterial integration

Compatibility with integration on-chip electronics

Low cost

Low absorption coefficient

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A/D converters

What is important for the focal-plane-applications?

Size, robustness, variable resolution

Conventional A/D converters

Flash ADC , Successive Approximation ADC

Single slope ADC, Cyclic ADC, Oversampling ADC

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A/D converters

TECHNIQUE BITS POWER AREA ROBUSTNESS SPEED NOISE COMPATIBILITYFlash 8 - 10 High Large Medium High Medium No (linear R)

Succ. App. 10 -12 Medium Medium Low Medium Medium No (linear C)Cyclic 7 Low Small Medium Medium High No (matched C)

Single-slope 10 - 12 Medium Small Low Medium High No (linear C)Oversampling 8 -20 Low Small * High Medium Low Yes (unmatched C)

*) modulator only

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Readout systems

Fast Shift Register ADC DigitalOutput

Focal Plane Arrays

Preamp Filters Amplifiers

Support an optimum interface between the detectors and the following signal processing stage.

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Readout systems

Fast Shift Register

Slow Shift R

egister

ADC DigitalOutput

Focal Plane Arrayw/o ADC

Slow Shift R

egister

DigitalOutput

Focal Plane Arrayw/o ADC

Fast Shift Register

ADCs

Serial readout system Noise reduction Not scalable Slow readout speed

Semi-parallel readout system Increase the readout speed Less sensitive to noise at

the analog signal path

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Readout system architecture

Fully parallel readout system was designed as a scalable FPA readout system

Detectors and ADCs layer DSP layer

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Readout system architecture

Signal path from image detector to signal processor

01010010

01010010

01010010

01010010

Emitter driver

Emitter

Detector

ReceiverComparatorSIMPil processor

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Readout system architecture

Two layer FPA system photomicrograph

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Readout system architecture

1.00E+00

1.00E+02

1.00E+04

1.00E+06

1.00E+08

1.00E+10

1.00E+12

1.00E+14

1.00E+16

0 5 10 15 20Resolution [bit]

Ban

dw

idth

[H

z]

Serial

Semi-parallel

Parallel

1.00E+07

1.00E+08

1.00E+09

1.00E+10

1.00E+11

1.00E+12

1.00E+13

1.00E+14

1.00E+15

1 10 100 1000 10000Array size

Ba

nd

wid

th [

Hz]

Serial

Semi-parallel

Parallel

Readout speed comparison with same ADCs

64

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Readout system architecture

Readout speed comparison with different ADCs

1.00E+06

1.00E+08

1.00E+10

1.00E+12

1.00E+14

0 5 10 15 20

Resolution [bit]

Ban

dw

idth

[H

z]

Serial

Semi-parallel

Parallel

1.00E+06

1.00E+07

1.00E+08

1.00E+09

1.00E+10

1.00E+11

1.00E+12

1.00E+13

1.00E+14

1 10 100 1000 10000Array size

Ban

dw

idth

[H

z]

Serial

Semi-parallel

Parallel

288 X 288 168MHz15bits 4GHz

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Compact oversampling conversion Oversampling ADC

Oversampling converters trade speed for accuracy

Analoginput

Noise shaping

modulator

PCM

Oversampling clockfS

Decimatorand

Digital LPF

Nyquist clockfN1-bit

stream

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Compact oversampling conversion

Quantization noise of oversampling modulatorEach doubling of the sampling frequency decreases the in-band noise by 3 dB.

f0 fS/2

PSD

Freq.

Signal

Quantization noise

f0 fS/2

PSD

Freq.

Signal

In band quantization noise

Removed by low pass filtering

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Compact oversampling conversion Modulation noise of higher order oversampling modulator

Each doubling of the sampling frequency decreases the in-band noise by (3+6n) dB.

f0 fS/2

PSD

Freq.

1st order quantization noise

2nd order quantization noise

Modulation noise

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Compact oversampling conversion Current input oversampling modulator

Oversampling loop linearity is improved. Amplifiers are removed from the feedback. Linear D/A conversion is available.

Analog input Digital output

Current D/A converter

Integrator

Buffer Comparator

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Compact oversampling conversion

Vdd

Vbias

D

M1 M2

M3 M4

detector

Current buffer

Low input impedance

Stabilize the detector bias voltage

2

42

3

31

1

1

m

dd

m

dd

min g

gg

g

gg

gZ

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Compact oversampling conversion

Current D/A converter Integrator

outi

ini

biasi

biasioutv

DDV

1M

2M

3M

4M

5M

6M

7M

8M

GND

Metal 3Metal 2

Metal 1Current in

GND

Current in

Integrator

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Compact oversampling conversion

Comparator (G. M. Yin)

Sampling rate : 100MHz, Input signal : 0.1V 10MHz

Input signalOutput signal

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Compact oversampling conversion

Overall system

V

V

dd

ss

clock1

clock2

detector Vdetector

Current buffer &Photo detector

Integrator &Current DAC

IntegratorComparator

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Compact oversampling conversion

Overall system simulation results

Integrator output voltage

Modulator output

0 5 10 15

x 105

-60

-50

-40

-30

-20

-10

0

10

20

30

Freq.

PDF [dB] 50 kHz input

signal

Modulation noise

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Compact oversampling conversion

Circuit noise attenuation

Delayxi

edi eci

yiwi++

-

111 diciciii eeexy

where, edi = detector, current buffer, and current D/A converter noise and

eci = quantization and comparator noise.

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Compact oversampling conversion

Layouts

To make a large detector, all the effort were applied to design a compact circuit.

Input parts of the circuits were carefully designed not to overlapped with digital lines.

To reduce the offset and improve the switching time of the comparator, all the components were carefully layout to make a matched comparator.

When the capacitor was laid-out, metal 1 and metal 3 layers were connected to the GND to prevent the metal-substrate capacitor.

The latch transistor size was optimized to drive a high capacitor load which is connected to several pixels through a long data line.

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Compact oversampling conversion

Photomicrographs

Detector

Circuits

CapacitorCapacitorPad

Circuits

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Photodetectors

Hybrid detectors

8X8 detectors top contact

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Photodetectors

Monomaterial detectors

Vbias

Vbias

GND

n+

n+

p+ p+ p+

p

n+p+

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Photodetectors

Monomaterial detectors

8X8 detectors test structures emitter driver

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Test Test setup

Arbitrary waveform generator (AWG2041) DC current sources (Keithley SMU 236) Sampling oscilloscope (Tektronix 11403A) Transient capture oscilloscope (Tektronix Multi-function optical meter (Newport 1835-c) Digital data acquisition card (CYDIO 192T) 50MHz 486 processor 233MHz Pentium processor Newport coated ND filters

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Test

Electrical testing– Verify the functionality of the circuit

1.000uA 2.013V

Oscilloscope

DC current source

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Test

Electrical testing results

Input = 0.03A Input = 0.06A

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Test

Slow speed testing setup

multiplexcircuitry

octal latch

shift register

divide by 256

systemclock

data out

AFOSR top chip

PC

Test Board

PCparallelI/O card

divide by 8

PC

FSB

Port A

Port B

Port C

Reset

1 1 2 11 8 6 4 11 2 5 8 11 11 5 11 4 16 10 16 16 16 25 4 10 16 16 16 16 13 5 16 16 16 16 16 13 3 8 16 16 16 10 01 2 2 10 16 11 11 11 0 2 2 6 4 4 1

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Test

Slow speed testing : sampling rate=1MHz

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Test

Uniformity

1 2 3 4 5 6 7 8S1

S4

S7

0

8

16

24

32

40

48

56

64

Output

X

Y

1 2 3 4 5 6 7 8S1

S4

S7

0

8

16

24

32

40

48

56

64

Output

X

Y

Low light intensity High light intensity

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Test

Linearity

64 pixels data 6 bits linearity

0

10

20

30

40

50

60

70

0 20 40 60 80 100 120 140 160 180 200

Light intensity

Out

put

Saturation

0

10

20

30

40

50

60

0 10 20 30 40 50 60 70 80 90 100

Light intensity

Outp

ut

6 bit range

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Test

Nonlinearity The nonlinearity of

the small light intensity was not coming from the FPA system but the optical filter.

The nonlinearity of the high light intensity was coming from the saturation of the system

0

1

2

3

4

5

6

0 0.002 0.004 0.006 0.008 0.01 0.012

Filtering

Me

as

ure

d o

pti

ca

l po

we

r (n

W)

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Ou

tpu

t

Measured data

Test data

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Test

System noiseThe system noise is over than 8 bits.

0.03

0.035

0.04

0.045

0.05

1 8 15 22 29 36 43 50 57 64

Pixel number

Out

put

-0.004

-0.003

-0.002

-0.001

0

0.001

0.002

0.003

0.004

1 8 15 22 29 36 43 50 57 64

Pixel number

No

ise

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High speed testing

To obtain a 8 bit 100kfps image :

oversampling ratio : 26

modulator bandwidth : 2.6 MHz

System bandwidth : 167 MHz

Test

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Modulator

Test

2 MHz 4 MHz

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Output with 2.5MHz system frequency.

Test

Microscope lightRoom light

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Output with 40MHz system frequency.

Test

Microscope lightRoom light

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Output with 100MHz system frequency.

Test

Microscope lightRoom light

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A new high speed readout system for FPAs were designed and tested.

A new readout architecture was designed.

A new current input first-order sigma-delta A/D modulator was designed.

Two kinds of photo detectors were utilized.

Several tests had been done to verify the proposed system.

Conclusion and future works

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To complete the fully parallel readout system for FPAs, two things need to be tested and verified.

Test the speed of the through-wafer optical communication.

Test with a microprocessor.

The focal-plane-array chip and the microprocessor chip need to be stacked and test together.

Conclusion and future works

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Whole system