high speed electronics (in optical communications)

High speed electronics (in optical communications)

SOK-2013 Conference

January 30/31, February 1, 2013

Ljubljana

Franz Dielacher

Marc Tiebout, Rudolf Lachner, Klaus Aufinger, Herbert Knapp, Koen Mertens, Werner Simbuerger

Copyright © Infineon Technologies 2010. All rights reserved. Confidential

OUTLINE

Introduction

¬ Optical communications and drivers

¬ Emerging silicon technologies and design considerations

SiGe:C technology and eWLB package for optical applications

Implementation examples

¬ O/E Module

¬ High-speed AD/DA converters

¬ VCO

Summary and a few statements


Internet connectivity

July, 2010

Copyright © Infineon Technologies 2010. All rights reserved. Confidential 31.01.2013

Optical Fiber • Thin glass wire with higher refractive index in the core to contain and guide the

light

• Typically transmitted at

– 1300 nm: zero dispersion for standard single-mode fibers

– 1550 nm: lowest loss, widely employes in telecommunications

• Advantages:

– Large data rates, e.g. Gbps to Tbps

– Immune to electrical interference

– Low loss → long reach

– Resistant to corrosion

– Small in size

• Disadvantages:

– Expensive to install


Evolution of Optical Links

Set date

Krishnamoorthy et al., "Progress in Low-Pow


Gartner hype cycle

July, 2010

OPTO: many years to mainstream adoption

//upload.wikimedia.org/wikipedia/commons/9/94/Gartner_Hype_Cycle.svg


VCSEL-based Optical Link Structure

Set date

Krishnamoorthy et al., "Progress in Low-Power”

VCSEL: Vertical Cavity Surface Emitting Laser


High Speed Transistor Technologies

10.02.2010


Requirements on Technologies for Optical Transceiver Circuits

Improved RF performance (ft, fmax, rf gain,…)

Lower noise, higher output power

Higher RF integration

more Tx channels

more Rx channels

frequency control and stabilization

Higher logic content

self test

self calibration

surveillance during operation

digital interfaces

Fmax --> 1 THz


Improved Gain/Stage with increased fT/fmax

fop=77 Ghz fmax=250 Ghz

Gain~10dB 0

10

20

30

40

50

0,1 1 10 100 1000

Frequenz [GHz]

Gain

[d

B]

Gain~14dB

fmax=400 Ghz

Gain (dB) ~ -20 dB x log (fop/fmax)

fmax=500 Ghz


fmax (IC)

0

50

100

150

200

250

300

350

400

450

500

0,1 1 10

IC (mA)

fmax (

GH

z)

250 GHz

PDPrel=1.00

WE=0,18µm; LE=2,7µm

400 GHz

PDPrel=0.62

WE=0,12µm LE=2,0µm

0,1 0,2 0,5 1 2 5

Improved performance

@ same current / power consumption

Why will high ft/fmax save power / current ?

PDPrel=relative power*delay product ~ VCC * I / fmax

Lower current / power consumption

@ same performance

Copyright © Infineon Technologies 2010. All rights reserved. Confidential Confidential

Comparision metal losses of CMOS Digital and BiCMOS

M1

M2

M3

M4

M5

M6

M1

M2

M3

M4

M5

M6

Silicon

Tungsten

Copper

Aluminum

Oxide / Nitride

Distance of top metal to ground plane (M1)

130 nm CMOS 130 nm RF BiCMOS

Loss 1.2 dB/mm 0.5 dB/mm

Source: STM


OUTLINE

Introduction





¬ O/E Module


¬ VCO


Copyright © Infineon Technologies 2010. All rights reserved. Confidential July, 2010

Lower Cost & Earlier Time to Market with Si / SiGe Bipolar

100 10

100

1000

ft [GHz]

LG [nm]

CMOS

(0,3µm / 200 Ghz)

Si NPN

SiGe NPN

SiGe:C NPN

250nm

130nm

65nm

32nm 3-4 Gen

16nm

45nm

22nm

65 nm or even 45 nm CMOS would be needed to be comparable to current state-of-the-art SiGe (pure Bipolar or BiCMOS)!

(0,045 µm / 200 Ghz)


Si / SiGe Bipolar versus CMOS

<= 65 nm CMOS would be needed for sufficient fT/fmax

¬ “VHNRE” (very high non recurring engineering cost)

< 30 nm CMOS for fcut-off ~ 400 GHz

Other factors favoring bipolar/ BiCMOS for analog millimeter wave applications:

Lower 1/f noise

Better current drive capability

Better matching

Better linearity

Higher voltage (output power)

July, 2010


BiCMOS and SiGe Roadmap

1

10

100

1980 1985 1990 1995 2000 2005 2010 2015 2020

Year

Ga

te D

ela

y [

ps

]

OXIS3

B6HFC

B7HFC

B7HF200

B7HF500

B7HF700

OXIS3: 75 ps (1985)

B6HF: 25 ps (1993)

B7HFC: 10 ps (2000)

B7HF200: 3.8 ps (2007)

B7HF500: 2.5 ps (2012)

B7HF700: 1.5 ps (2015)


High-Speed SiGe Bipolar Technology

self-aligned SiGe HBT emitter width 0.18 µm

transit frequency 200 GHz

max. oscillation frequency 200 GHz

C-E breakdown voltage 1.8 V

gate delay 3.7 ps

0.1 1 100

40

80

120

160

200206 GHz

VBC

= -1.0 V

VBC

= -0.5 V

VBC

= 0 V

AE = 0.18 x 2.8 µm

2

GHz

mA

fT

IC

Transit Frequency

Ref: T. Meister et al., Infineon, BCTM2003


SiGe:C Technology available components

Three types of npn transistors

Vertical pnp transistor

Varactor

Three resistor types

Two polysilicon resistor types

TaN thin film resistors

MIM capacitor

4 copper metallization layers

Automotive qualified and productive


Photonics integration, Rx+Tx

July, 2010

Young, JSSC, Jan 2010


Chip assemply: high frequency, precision mechanics, heat control

July, 2010

Ref. : M. Möller, Uni Saarland, Micram


The high-speed and RF suited Package Comparison Wirebond BGA/Flip-Chip BGA/WLB

R @ DC 76 mΩ 7.5 mΩ 3.2 mΩ In

ter-

co

nn

ect

R @ 5 GHz

375 mΩ 41 mΩ 15 mΩ

L 1.1 nH 52 pH 18 pH

Package parasitics High Low

Passive Integration in redistribution layers

Package EM co-simulation

BGA Wirebond BGA Flip Chip WLB


Slide 22

“eWLB” embedded wafer-level ballgrid array

Organic

Dielectric

Redistribution

Layer (Cu)

Chip

Metallization

Solder

Ball

300µm


Name N Qmax L(Qmax)

[nH]

f(Qmax)

[GHz]

fres

[GHz]

RDC

[Ohm]

Area

[mm2]

L81 1.5 39 2.8 4.2 14 0.30 0.40

L82 2.5 39 6.3 2.4 7.5 0.53 0.54

L83 3.5 35 12.0 1.9 4.8 0.85 0.74

L84 4.5 31 20 1.4 3.4 1.2 0.97

L85 5.5 28 30 0.96 2.6 1.6 1.23

eWLB

• High-Q single / double layer inductors

L = 0.5 − 35 nH

Q = 20 − 45

Fres = 1 − 35 GHz

• Impact of tolerances

|DW| ,|DH| ≤ 1 µm

|DL| ≤ 1.5%

Parameter Value

Min. line width

[µm] 20

Min. line spacing

[µm] 20

Number of layers 1 − 2

Typical area (1

nH) [mm2]

0.03 −

0.3

Typical area (30

nH) [mm2]

0.6 −

1.2

Nlow = 2.5 Nup = 3 N = 5.5

eWLB Passives: Measurement Results

03.02.2012


Slide 24

Chip / Package Co-Design

Interaction of package metallization and on-chip transmission lines and inductors

EM co-simulation

¬Radiation analysis

¬Tolerance analysis

Thermal management

Constraints on chip size and pad placement


Challenges

Complex geometry of package

¬ Electrically large structures

¬ Many fine details much smaller than wavelength

¬ Consider only the important details

Many parasitic effects present

¬ In the microwave transitions

¬ Reflection, mode conversion, losses

¬ In the full package

¬ Radiation, coupling to other ports

Full wave 3D EM Simulation needed (HFSS, Microwave-studio,…)

Large number of discrete cells needed

July, 2010


OUTLINE

Introduction





¬ O/E Module


¬ VCO



Low input imp.

Diff.

50 Ohm

output

stage I I

QD1 V

QD2 V

QD3 V

QD U

Low noise

TIA

Limiting

Amplifier

Limiting

Amplifier

Output

Buffer

High-Frequency stages

Schematic of a low noise, high gain transimpedance amplifier


Low noise, high gain broadband

transimpedance amplifier

Silicon-Germanium technology

Area: 0.97 x 0.97 mm2

Data rate up to 10.7 Gbit/s

-18dBm optical input sensitivity

High transimpedance: 6 kW

Low Power: 170 mW

Single Power Supply: +5V

Internal DC compensation loop

Fits to low cost TO package

OUT1

IN

OUT2

Transimpedance amplifier


100-Gb/s Broadband Amplifier in SiGe technology

3-dB bandwidth: 62 GHz

Gain: 16 dB

1-dB compr. point (input): -9.5 dBm

3rd-order interc. point (input):2.1 dBm

Eye diagram at 100 Gb/s

Ref.: W. Perndl

X-axis: 5 ps/div,

y-axis:250mV/div


110 GHz Dynamic Frequency Divider in SiGe Bipolar

Ref. H. Knapp et al.



Ref. H. Knapp et al



Ref. H. Knapp et al.


AD- and DA- converters needed

Set date

• Pre-emphasis

• Higher Level QAM/DQPSK

• OFDM

• Multi Format, Adaptive Tx

• Equalization in binary Tx

• Higher Level QAM/DQPSK

• OFDM

• Multi-Format, Adaptive Rx


FOM =

P

4kT BW DR

Speed Resolution Limits ADC

P

2N 2BW

Time interleaved

Flash


High-Speed ADC Trend: Speed vs. Resolution

Set date


Time Interleaved ADC

Enhance Speed

Low Power

Channel Alignment Voff Gain

Jitter

BiCMOS


High-Speed ADC Trend: Energy Efficiency

Set date



Performance overview of high-speed time-interleaved ADCs

10.02.2010


CMOS 65nm flash ADC

6 Bit flash ADC in c65

65 nm CMOS Technology

6 Bit

2 * 3 GSps @ 5 ENOBs

250 mW

Pipelining & ping pong

new bubble sort concept

no boosted switches

Copyright © Infineon Technologies 2010. All rights reserved. Confidential Set date


SiGe BICMOS 22Gs/s DAC Macro

• Transmitter Pre-distortion in 10G eDCO

Technology 0.13 um SiGe BiCMOS

Die area (DAC only) 1.8 x 2.5 mm2

Transistors (DAC only) 569 bipolar

Clock 22GHz

DNL < 0.4LSB

INL < 0.4LSB

SFDR 43 – 35dB up to 8GHz

Settling time 60/40ps @ full/half scale

Glitch energy < 0.5pVs

Power dissipation 1.2W @ 3.3V supply

6-bit DAC performance


Beyond 100 GbE

Set date

• Next step will be 400 GbE

• Data rates up to 448 Gb/s including FEC

• Keet WDM grid -> higher order modulation formats

• DA-converters mandatory in Tx

• Very high bandwidth/ENOB ADCs may become bottleneck again


Low Phase Noise VCO Design

Set date


VCO in SiGe:C Technology

VCO Technology SiGe B7HF200 SiGe B7HF200 VDD 3.3V 3.3V Pout Frequency range 19-22GHz Fc=2.6GHz VCO Phase Noise

minus 136 dBc per Hz at 10 MHz

minus 134 dBc per Hz at 1 MHz


OUTLINE

Introduction





¬ O/E Module


¬ VCO



Summary and some statements

0

2013 2015 2016 2017 2014

• Fiber optics was the only answer and everything else was interim

•SiGe:C and latest CMOS push the limits

• Cisco packs silicon photonics on 3D ICs

• ADCs exploring the limits

http://eetimes.com/ContentEETimes/Images/CiscoSlide.jpg


Sales are deteriorating

Our plan is to invent a kind of thingy, that

everyone wants to buy

So, I have fulfilled my job as visionary leader, how long will you need for yours?

Thank you for your attention

high speed electronics (in optical communications)

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