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Motivation Contributions Circuit Signatures: Snapshot of This Work Recent Work Pubs.

High Sensitivity Signatures for Test andDiagnosis of Analog, Mixed-Signal and

Radio-Frequency Circuits

Ph.D. Dissertation Defense

Suraj SindiaDept. of ECE, Auburn University, AL, USA

June 8, 2013

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Outline

1 Motivation

2 Contributions of This Thesis

3 Circuit Signatures: Snapshot of This Thesis

4 Recent Work

5 Publications

Suraj Sindia 2/ 47


Outline

1 Motivation



4 Recent Work

5 Publications

Suraj Sindia 3/ 47


Conventional Analog Circuit Test

How are analog circuits tested today?

Test programs on Automatic Test Equipment (ATE) arrive atpass/fail decision based on whether Circuit Under Test (CUT)meets all data-sheet specifications.

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High Costs of Conventional Analog Circuit Test

1980 1985 1990 1995 2000 2005 2010 201510

−2

10−1

100

101

102

103

104

Cos

t: C

ents

/10,

000

tran

sist

ors

Manufacturing costAnalog/Mixed−signal test costDigital test cost

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International Technology Roadmap for Semiconductors 1999 & 2009


What is Wrong With Conventional Analog Circuit Test?

Need for unconventional test paradigms for analog circuitsTesting devices for all specifications consumes long testtimes, on expensive test instruments.

Testing some specifications may need multipleconfigurations and complex input stimulus.Today, analog portions of a mixed signal system on chip(SoC) can contribute as much as 50% of total test costthough they occupy less than 5% of silicon area.

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Need for unconventional test paradigms for analog circuits

Testing devices for all specifications consumes long testtimes, on expensive test instruments.

Testing some specifications may need multipleconfigurations and complex input stimulus.

Today, analog portions of a mixed signal system on chip(SoC) can contribute as much as 50% of total test costthough they occupy less than 5% of silicon area.

Suraj Sindia 6/ 47



Need for unconventional test paradigms for analog circuits

Testing devices for all specifications consumes long testtimes, on expensive test instruments.Testing some specifications may need multipleconfigurations and complex input stimulus.

Today, analog portions of a mixed signal system on chip(SoC) can contribute as much as 50% of total test costthough they occupy less than 5% of silicon area.

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R. Wilson, “Under the Lid: Analog test is suddenly the critical ingredient,”Electronics, Design, Strategy, News, Jan 2010.



Need for unconventional test paradigms for analog circuitsTesting devices for all specifications consumes long testtimes, on expensive test instruments.Testing some specifications may need multipleconfigurations and complex input stimulus.Today, analog portions of a mixed signal system on chip(SoC) can contribute as much as 50% of total test costthough they occupy less than 5% of silicon area.

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R. Wilson, “Under the Lid: Analog test is suddenly the critical ingredient,”Electronics, Design, Strategy, News, Jan 2010.


Unconventional Analog Test Paradigms

Key advantage over conventional test: pass/fail decision isarrived at based on a few easily available measurements.

Can be broadly classified into–

Fault model based test techniquesAlternate circuit test techniques

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M. Soma CICC’91, K. Arabi ITC’93, IEEE DTC’92, J. Abraham IEEE DTC’96,S. Sunter VTS’98, J. Savir ITC’03.A. Chatterjee ICCAD’97, VTS’00, Y. Makris VTS’05,’06.




Can be broadly classified into–Fault model based test techniquesAlternate circuit test techniques

Suraj Sindia 7/ 47

M. Soma CICC’91, K. Arabi ITC’93, IEEE DTC’92, J. Abraham IEEE DTC’96,S. Sunter VTS’98, J. Savir ITC’03.A. Chatterjee ICCAD’97, VTS’00, Y. Makris VTS’05,’06.




Can be broadly classified into–Fault model based test techniques

Defects in circuit components are modeled as faults.Test stimulus is geared towards detecting faults in circuitcomponents.Pass/fail decision is based on where component values liew.r.t their fault free range.

Alternate circuit test techniques

Suraj Sindia 7/ 47

M. Soma CICC’91, K. Arabi ITC’93, IEEE DTC’92, J. Abraham IEEE DTC’96,S. Sunter VTS’98, J. Savir ITC’03.

A. Chatterjee ICCAD’97, VTS’00, Y. Makris VTS’05,’06.




Can be broadly classified into–Fault model based test techniquesAlternate circuit test techniques

A regression model relating circuit outputs to specificationsis built.Test stimulus is crafted to maximize correlation of circuitoutput to specification.Pass/fail decision is based on predicted value ofspecification by the regression model.

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M. Soma CICC’91, K. Arabi ITC’93, IEEE DTC’92, J. Abraham IEEE DTC’96,S. Sunter VTS’98, J. Savir ITC’03.

A. Chatterjee ICCAD’97, VTS’00, Y. Makris VTS’05,’06.



But these unconventional test paradigms ...Are rarely used in the industry.

Why?Lack of circuit outputs (or signatures) with

High sensitivity to circuit parameters, andHigh correlation to specifications.

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But these unconventional test paradigms ...Are rarely used in the industry. Why?

Lack of circuit outputs (or signatures) withHigh sensitivity to circuit parameters, andHigh correlation to specifications.

Suraj Sindia 8/ 47


Outline

1 Motivation



4 Recent Work

5 Publications

Suraj Sindia 9/ 47


Principal Contribution of This Work

To design analog circuit test signaturesHigh sensitivity – detects sufficiently small parametricfaults, thus augmenting existing fault model based testschemes

High correlation with circuit specifications – augmentingalternate circuit test schemesSmall area overhead – requires little additional hardwareon chip for production testingLarge number observables – handy in diagnosisSuitable for large class of circuitsAids distinction of small defects from process variation(PV) induced faults – need in advanced tech nodesAmenable to self-test.

Suraj Sindia 10/ 47



To design analog circuit test signaturesHigh sensitivity – detects sufficiently small parametricfaults, thus augmenting existing fault model based testschemesHigh correlation with circuit specifications – augmentingalternate circuit test schemes

Small area overhead – requires little additional hardwareon chip for production testingLarge number observables – handy in diagnosisSuitable for large class of circuitsAids distinction of small defects from process variation(PV) induced faults – need in advanced tech nodesAmenable to self-test.

Suraj Sindia 10/ 47



To design analog circuit test signaturesHigh sensitivity – detects sufficiently small parametricfaults, thus augmenting existing fault model based testschemesHigh correlation with circuit specifications – augmentingalternate circuit test schemesSmall area overhead – requires little additional hardwareon chip for production testing

Large number observables – handy in diagnosisSuitable for large class of circuitsAids distinction of small defects from process variation(PV) induced faults – need in advanced tech nodesAmenable to self-test.

Suraj Sindia 10/ 47



To design analog circuit test signaturesHigh sensitivity – detects sufficiently small parametricfaults, thus augmenting existing fault model based testschemesHigh correlation with circuit specifications – augmentingalternate circuit test schemesSmall area overhead – requires little additional hardwareon chip for production testingLarge number observables – handy in diagnosisSuitable for large class of circuitsAids distinction of small defects from process variation(PV) induced faults – need in advanced tech nodesAmenable to self-test.

Suraj Sindia 10/ 47


In This Dissertation

Main ContributionDesign analog circuit test signatures.

Additional contributionsExtend the use of these signatures for diagnosis ofcomponent faults.

Demonstrate the use of signatures for classifying faultsdue to manufacturing defects from those due to processrelated variations.Evaluate the bounds on minimum achievable defect leveland yield loss resulting from the use of these testsignatures.

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Additional contributionsExtend the use of these signatures for diagnosis ofcomponent faults.Demonstrate the use of signatures for classifying faultsdue to manufacturing defects from those due to processrelated variations.

Evaluate the bounds on minimum achievable defect leveland yield loss resulting from the use of these testsignatures.

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Additional contributionsExtend the use of these signatures for diagnosis ofcomponent faults.Demonstrate the use of signatures for classifying faultsdue to manufacturing defects from those due to processrelated variations.Evaluate the bounds on minimum achievable defect leveland yield loss resulting from the use of these testsignatures.

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A Statement on Methods

Proposed signatures and associated test proceduresAre analyzed theoretically.Validated empirically through simulations on commonanalog circuits such as filters and low noise amplifier.Are additionally validated by conducting hardwaremeasurements on these circuits using NI-ELVISinstrumentation boards.

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NI-ELVIS – National Instruments ELectronic Virtual Instrumentation Suite


Outline

1 Motivation



4 Recent Work

5 Publications

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Test Setups: Unconventional Test Paradigms vs.Proposed

Test setup commonly used in unconventional test paradigms

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Test Setups: Unconventional Test Paradigms vs.Proposed

Proposed test Setup

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Polynomial Coefficient Based Testing

Test Setup

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Taylor series expansion of circuit function about vin = 0

vout = f (vin)

vout = f (0) + f ′(0)1! vin + f ′′(0)

2! v2in + f ′′′(0)

3! v3in + · · ·+ f (n)(0)

n! vnin + · · ·

Ignoring the higher order terms we have

vout ≈ a0 + a1vin + a2v2in + · · ·+ anvn

in

where every ai ∈ < and is bounded between its extreme valuesfor

ai,min < ai < ai,max ∀i 0 ≤ i ≤ n

Suraj Sindia 16/ 47

S. Sindia et. al., GLSVLSI 2009, ATS 2009.



Cascaded amplifiers – quick exampleVdd

R2R1 IM1 IM2

M1 M2

Vin

Vout

Two stage amplifier with 4th degree non-linearity in Vin

vout = a0 + a1vin + a2v2in + a3v3

in + a4v4in

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Polynomial coefficients are related to circuit components

a0 = VDD − R2K(

WL

)2

[(VDD − VT )

2 + R21K 2

(WL

)21 V 4

T−2(VDD − VT )R1

(WL

)1 V 2

T

]

a1 = R2K(

WL

)2

[4R2

1K 2(

WL

)2

1V 3

T + 2(VDD − VT )R1K(

WL

)1

VT

]

a2 = R2K(

WL

)2

[2(VDD − VT )R1K

(WL

)1− 6R2

1K 2(

WL

)2

1V 2

T

]

a3 = 4VT K 3(

WL

)2

1

(WL

)2

2R2

1R2

a4 = −K 3(

WL

)2

1

(WL

)2

2R2

1R2

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MSDF CalculationMinimum Size Detectable Fault(ρ) of a circuit parameter isdefined as its minimum fractional deviation to force at least oneof the polynomial coefficients out of its fault free range

Overview of MSDF calculation of R1 with VDD=1.2V, VT=400mV,

(WL

)1= 1

2

(WL

)2= 20, and K = 100µA/V2

Maximize a0{1.2− R2,nom(1 + y)

(2.56x10−3 + R2

1,nom(1 + x)21.024x10−7

−5.12x10−4R1,nom(1 + x)

)}subject to a1,a2,a3,a4 being in their fault free ranges and

−α ≤ x , y ≤ α

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MSDF Calculation (contd..)Assuming single parametric faults, ρ for R1

ρ = (1− α)1.5 − 1 ≈ 1.5α− 0.375α2

MSDF for Cascaded Amplifier with α = 0.05

Circuit parameter %upside MSDF %downside MSDFResistor R1 10.3 7.4Resistor R2 12.3 8.5

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In a nutshellFind the Vout v/s Vin relationship at DC & and selectedtones

Compute the coefficients of fault-free circuitFault simulate to obtain fault free intervals of each of thesecoefficientsEstimate coefficients of CUT by curve fitting the I/OresponseCompare each of the obtained coefficients with fault-freecircuit rangeClassify CUT as Good or Bad

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In a nutshellFind the Vout v/s Vin relationship at DC & and selectedtonesCompute the coefficients of fault-free circuit

Fault simulate to obtain fault free intervals of each of thesecoefficientsEstimate coefficients of CUT by curve fitting the I/OresponseCompare each of the obtained coefficients with fault-freecircuit rangeClassify CUT as Good or Bad

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In a nutshellFind the Vout v/s Vin relationship at DC & and selectedtonesCompute the coefficients of fault-free circuitFault simulate to obtain fault free intervals of each of thesecoefficientsEstimate coefficients of CUT by curve fitting the I/Oresponse

Compare each of the obtained coefficients with fault-freecircuit rangeClassify CUT as Good or Bad

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In a nutshellFind the Vout v/s Vin relationship at DC & and selectedtonesCompute the coefficients of fault-free circuitFault simulate to obtain fault free intervals of each of thesecoefficientsEstimate coefficients of CUT by curve fitting the I/OresponseCompare each of the obtained coefficients with fault-freecircuit range

Classify CUT as Good or Bad

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In a nutshellFind the Vout v/s Vin relationship at DC & and selectedtonesCompute the coefficients of fault-free circuitFault simulate to obtain fault free intervals of each of thesecoefficientsEstimate coefficients of CUT by curve fitting the I/OresponseCompare each of the obtained coefficients with fault-freecircuit rangeClassify CUT as Good or Bad

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V-Transform Coefficient – An Introduction

Definition

VCi = eγC′i ∀ 0 ≤ i ≤ n

dC′idpj

=

∣∣∣∣dCi

dpj

∣∣∣∣ ∀ 0 ≤ i ≤ n

Ci – ith polyomial coefficientC′i – ith modified polynomial coefficientVCi – ith V-Transform coefficient

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S. Sindia et. al., EWDTS 2009, VTS 2011.


V-Transform Coefficient – Sensitivity Gain

Sensitivity of coefficients

SVCipi

SCipi

=

∣∣∣dCidpi

∣∣∣ γeγC′i • pi

eγC′i

dCidpi• pi

Ci

= γCi

γCi – Increased sensitivity over ordinary polynomial coefficientsγ – Sensitivity parameter that can be chosen according to thedesired degree of sensitivity

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V-transform Coefficient Based Test

Test Set-up

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Let us Generalize

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Generalization – Fault Simulation

1 Start2 Choose frequency for fault simulation3 Apply sweep to input and note corresponding output

voltage levels4 Polynomial Curve fit the obtained I/O data – find the

coefficient values of fault free circuit. Computecorresponding V-Transform coefficients.

5 Simulate for all parametric faults at the simplex ofhypercube

6 Find min-max values of each coefficient (Ci ) fromi = 1 · · ·N across all simulations. Compute theV-Transform coefficient VCi bounds.

7 Repeat process at all chosen frequencies8 Stop

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Generalization – Test Procedure

1 Start

2 Choose a frequency

3 Sweep input and note corresponding output voltage levels

4 Polynomial Curve fit the obtained I/O data. Obtain coefficientsCi ∀ i = 1 · · ·N.

5 Obtain corresponding VCi

6 Consider the coefficient VCi , starting from i = 1 · · ·N

7 |VCi | >∣∣VCi,max

∣∣or |VCi | <∣∣VCi,min

∣∣? Yes or No

8 If Yes, conclude CUT is faulty. If not, repeat the test for nextcoefficient.

9 If all coefficients are inside the bounds, subject CUT to furthertests. Stop

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Results – Benchmark Elliptic Filter

−

+−

+−

+Vout

VinR1

R2

R4

R5

R3 R7

R6

R8

R9

R10

R11 R12

R13

R14

R15

C1

C3

C4

C5

C6 C7

C2

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Results - Curve Fitting at DC

0 1 2 3 4 5−3

−2

−1

0

1

2

3

4

5

Input DC voltage (Vin)

Out

put V

olta

ge(V

out)

Simulated

5th degree polynomial

a5 = 0.039463a4 = −0.50514a3 = 2.1309a2 = −2.5487a1 = −3.498a0 = 4.5341

vout=4.5341−3.498vin−2.5487v2in+2.1309v3

in−0.50514v4in+0.039463v5

in

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Results - V-Transform Coefficients

0 1 2 3 4 50

1000

2000

3000

4000

5000

6000V−Transform Coefficient plot

Input DC Voltage (Vin)

V−

Tra

nsfo

rmed

Out

put V

olta

ge

0 1 2 3 4 5−3

−2

−1

0

1

2

3

4

5

Out

put V

olta

ge (

Vou

t)

Polynomial Coefficient Plot

Input DC Voltage (Vin)

Simulated5th degree polynomial

a5 = 0.039463a4 = −0.50514a3 = 2.1309a2 = −2.5487a1 = −3.498a0 = 4.5341

Vc5 = 1.0402Vc4 = 1.6572Vc3 = 8.4224Vc2 = 12.7904Vc1 = 33.0492Vc0 = 93.1396

VC5 = 1.0402 VC4= 1.6572 VC3

= 8.4224 VC2= 12.7904 VC1

= 33.0492 VC1= 93.1396

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Results at DC - Elliptic Filter

Parameter Combinations Leading to Max Values of V-TransformCoefficients with α = 0.05

Circuit Vc0 Vc1 Vc2 Vc3 Vc4 Vc5

Parameter, (ohm)R1 = 19.6k 18.6k 20.5k 20.5k 20.5k 18.6k 18.6kR2 = 196k 186k 205k 186k 186k 186k 205kR3 = 147k 139k 154k 154k 154k 139k 154k

R4 = 1k 950 1010 1010 1010 1010 1010R5 = 71.5 70 80 80 70 80 70R6 = 37.4k 37.4k 37.4k 37.4k 37.4k 37.4k 37.4kR7 = 154k 161k 161k 146k 161k 146k 146kR11 = 110k 115k 115k 104k 115k 104k 104kR12 = 110k 104k 115k 104k 104k 104k 104k

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Parameter Combinations Leading to Min Values of V-Transformcoefficients with α = 0.05

Circuit Vc0 Vc1 Vc2 Vc3 Vc4 Vc5

Parameter, (ohm)R1 = 19.6k 20.5k 18.6k 18.6k 20.5k 20.5k 20.5kR2 = 196k 205k 186k 205k 205k 205k 186kR3 = 147k 150k 139k 139k 146k 154k 139k

R4 = 1k 1010 950 950 950 950 950R5 = 71.5 80 70 70 80 70 80R6 = 37.4k 39.2k 39.2k 39.2k 39.2k 35.5k 39.2kR7 = 154k 146k 146k 161k 146k 161k 161kR11 = 110k 104k 104k 115k 104k 115k 115kR12 = 110k 115k 104k 115k 115k 115k 115k

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Fault Classification

Motivation1 Semiconductor processes at advanced nodes are subject

to random variabilityPoly/TFR resistance (LER), oxide thickness fluctuation/LERcapacitors (σ ≈ 30%)

2 Faults due to variability can mask or exacerbate failurefrom conventional defect mechanisms.

Dust contamination, Processing Equipment, Materialimpurity, Clean room contamination, Operator imperfection,etc., (Fault sizes > 50%)

3 Distinguishing failure mechanisms between PV andconventional ones can possibly help improve yield.

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Suraj Sindia 34/ 47



R1

m mm sm s CCth

R2

R

G1 G2

C ≶H2H1

Cth

H1: Fault likely due to manufacturing defectH2: Fault likely due to process parameter variation

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Summary of stepsPDF of the coefficients are computed by monte-carlosimulations for fault-freePDF of the coefficients are computed by monte-carlosimulations for faulty circuitsThreshold values of coefficients – Boundaries between PVand manufacturing defects is estimated for each frequencyConfidence of classifying a fault as PV or manufacturingdefect is improved by observing one or more coefficients atmultiple frequencies.

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Confidence of classificationIf Pi is the probability of coefficient being outside its permissibleinterval due to process variation, then we define confidence indiagnosing CUT to be faulty due to PV, C (N is the total numberof coefficients).

C =1

1−i=N∏i=1

(1− Pi)

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Fault detection for some injected faults

Circuit Out of bound Fault Out of bound FaultParameter polynomial detected? V-Transform detected?

coefficient coefficientR1 down 25% a3, a4 Yes Vc0 − Vc4 YesR2 down 30% a2 Yes Vc2 , Vc5 Yes

R3 up 25% a3 Yes Vc1 , Vc2 , Vc3 YesR4 down 30% a0 Yes Vc0 − Vc4 Yes

R5 up 30% a4 Yes Vc0 , Vc4 YesR7 up 10% None PV (C = 200) Vc1 , Vc2 YesR11 up 15% None PV (C = 120) Vc4 , Vc5 Yes

R12 down 15% None PV (C = 90) Vc4 , Vc5 Yes

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Results Not Presented in Today’s Talk

Circuit test using probability moments of the circuit outputas a signature and noise as input.

Parametric and catastrophic fault diagnosis usingV-transform, polynomial and probability moments as circuitsignatures.An analytical bound on defect level and fault coverageachievable using transfer function coefficient based test.Hardware validation of V-transform and polynomialcoefficient based test on a 5th order elliptic filter using NI-ELVIS.

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S. Sindia, et. al., LATW’11, ATS’11



Circuit test using probability moments of the circuit outputas a signature and noise as input.

Parametric and catastrophic fault diagnosis usingV-transform, polynomial and probability moments as circuitsignatures.

An analytical bound on defect level and fault coverageachievable using transfer function coefficient based test.Hardware validation of V-transform and polynomialcoefficient based test on a 5th order elliptic filter using NI-ELVIS.

Suraj Sindia 39/ 47

S. Sindia, et. al., VLSI Design’10, VTS’11, ATS’11



Circuit test using probability moments of the circuit outputas a signature and noise as input.Parametric and catastrophic fault diagnosis usingV-transform, polynomial and probability moments as circuitsignatures.

An analytical bound on defect level and fault coverageachievable using transfer function coefficient based test.

Hardware validation of V-transform and polynomialcoefficient based test on a 5th order elliptic filter using NI-ELVIS.

Suraj Sindia 39/ 47

S. Sindia, et. al., VDAT’09



Circuit test using probability moments of the circuit outputas a signature and noise as input.Parametric and catastrophic fault diagnosis usingV-transform, polynomial and probability moments as circuitsignatures.An analytical bound on defect level and fault coverageachievable using transfer function coefficient based test.

Hardware validation of V-transform and polynomialcoefficient based test on a 5th order elliptic filter using NI-ELVIS.

Suraj Sindia 39/ 47

S. Sindia, et. al., JETTA’11 (spl. issue)



Circuit test using probability moments of the circuit outputas a signature and noise as input.Parametric and catastrophic fault diagnosis usingV-transform, polynomial and probability moments as circuitsignatures.An analytical bound on defect level and fault coverageachievable using transfer function coefficient based test.Hardware validation of V-transform and polynomialcoefficient based test on a 5th order elliptic filter using NI-ELVIS.

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Outline

1 Motivation



4 Recent Work

5 Publications

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Closed Loop Signature Testing

Idea: Applying stimulus based on the response of the CUT to areference signal to enhance correlation of signatures tospecification.

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Results: Open Loop Signature Testing

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Results: Closed Loop Signature Testing

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Results

Comparison of defect level, yield loss, and test time

Test Method Defect Level Yield Loss Test Time (per device)

Actual specification test 0% 0% 15sSignature test in open loop 8% 12% 100ms

Signature test in closed loop 0.8% 1.8% 105ms

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Outline

1 Motivation



4 Recent Work

5 Publications

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PUBLICATIONS

ALL JOURNAL PUBLICATIONS

1 S. Sindia, V. D. Agrawal, V. Singh,“Parametric Fault Testing ofNon-Linear Analog Circuits Based on Polynomial andV-Transform Coefficients,” JETTA, Spl. issue on Mixed SignalTest Techniques.

2 S. Sindia, V. D. Agrawal, V. Singh “Defect Level and FaultCoverage in Coefficient Based Analog Circuit Testing,” JETTALetters.

3 S. Sindia, V. D. Agrawal, “Neural Network Guided Spatial FaultResilience in Array Processors,” To appear, JETTA , Spl. issueon Defect and Fault Tolerance.

4 S. Sindia, V. D. Agrawal, “Testing Analog Circuits Via Momentsas Output Signatures and Random Noise as Input,”Inpreparation IEEE Trans. Comp. Aided Des.

5 S. Sindia, V. D. Agrawal, “Closed Loop Testing of Analog CircuitsVia V-Transform,”In preparation IEEE Trans. Comp. Aided Des.

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ALL CONFERENCE PUBLICATIONS

1 P. Venkataramani, S. Sindia, V. D. Agrawal, “Finding BestVoltage and Frequency to Shorten Power-Constrained TestTime,” VLSI Test Symp., VTS 2013, Berkeley, CA

2 S. Sindia, S. Gao, B. Black, V. D. Agrawal, A. Lim, P. Agrawal,“MobSched: Customizable Scheduler for Mobile CloudComputing,” Proc. of Southeastern. Symp. on Systems Theory,SSST 2013, Waco, TX

3 S. Sindia, V. D. Agrawal, “Analog and RF Circuit Testing”Education Day Talk, VLSI Design and Test Symp., VDAT 2012,Shibpur, India

4 S. Sindia, V. D. Agrawal, V. Singh,“Impact of Process Variationson Computers Used for Image Processing,” Proc. of Int. Symp.on Circuits and Systems, ISCAS 2012, Seoul, South Korea

5 S. Sindia, V. D. Agrawal, “Towards Spatial Fault Resilience inArray Processors,” Proc. of 30th IEEE VLSI Test Symposium,VTS 2012, Maui, HI

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6 S. Sindia, V. D. Agrawal, F. Dai, “All-Digital Replica Techniquesfor Managing Random Mismatch in Time-to-Digital Converters,”Proc. of Southeastern. Symp. on Systems Theory, SSST 2012,Jacksonville, FL

7 S. Sindia, V. D. Agrawal, V. Singh, “Test and Diagnosis of AnalogCircuits using Moment Generating Functions,” Proc. of 20thAsian Test Symposium, ATS 2011, New Delhi, India

8 S. Sindia, V. D. Agrawal, F. Dai, “LNA Test: A PolynomialCoefficient Approach,” Proc. 20th IEEE North Atlantic TestWorkshop, NATW 2011, Lowell, MA

9 S. Sindia, V. D. Agrawal, V. Singh, “Non-Linear Analog CircuitTest using Moment Generating Functions,” Proc. of 12th IEEELatin American Test Workshop, LATW 2011, Porto de Galinhas,Brazil

10 S. Sindia, V. D. Agrawal, V. Singh, “Non-Linear Analog CircuitTest and Diagnosis under Process Variation using V-TransformCoefficients,” Proc. of 29th IEEE VLSI Test Symposium, VTS2011, Dana Point, CA

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11 S. Sindia, V. D. Agrawal, V. Singh, “Distinguishing ProcessVariation Induced Faults from Manufacturing Defects in AnalogICs,” Proc. of 43rd IEEE Southeastern Symposium on SystemTheory, SSST 2011, Auburn, AL

12 S. Sindia, V. Singh, V. D. Agrawal,“Parametric Fault Diagnosis ofNonlinear Analog Circuits using Polynomial Coefficients,” Proc.of 23rd Intl. Conf. on VLSI Design, VLSI 2010, Bangalore, India

13 S. Sindia, V. Singh, V. D. Agrawal,“Multi-Tone Testing of Linearand Nonlinear Analog Circuits using Polynomial Coefficients,”Proc. of 18th Asian Test Symposium, ATS 2009, Taichung,Taiwan

14 S. Sindia, V. Singh, V. D. Agrawal,“V-Transform: An EnhancedPolynomial Coefficient Based DC Test for Non-Linear AnalogCircuits,” Proc. of 7th IEEE East-West Design and TestSymposium, EWDTS 2009, Moscow, Russia

Suraj Sindia 46/ 47


15 S. Sindia, V. Singh, V. D. Agrawal,“Bounds on Defect Level andFault Coverage in Linear Analog Circuit Testing,” Proc. of 13thIEEE/VSI VLSI Design and Test Symposium, VDAT 2009,Bangalore, India

16 S. Sindia, V. Singh, V. D. Agrawal,“Polynomial Coefficient BasedMulti-Tone Test of Analog Circuits,” Proc. of 18th IEEE NorthAtlantic Test Workshop, NATW 2009, Hopewell Jn., NY

17 S. Sindia, V. Singh, V. D. Agrawal,“Polynomial Coefficient BasedDC Testing of Non-Linear Analog Circuits,” Proc. of 19th ACMGreat Lakes Symposium on VLSI, GLSVLSI 2009, Boston, MA

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