high reliability and efﬁciency single-phase

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 5, MAY 2013 2235

High Reliability and Efficiency Single-PhaseTransformerless Inverter for Grid-Connected

Photovoltaic SystemsBin Gu, Student Member, IEEE, Jason Dominic, Jih-Sheng Lai, Fellow, IEEE, Chien-Liang Chen, Member, IEEE,

Thomas LaBella, Student Member, IEEE, and Baifeng Chen, Student Member, IEEE

Abstract—This paper presents a high-reliability single-phasetransformerless grid-connected inverter that utilizes superjunc-tion MOSFETs to achieve high efficiency for photovoltaic appli-cations. The proposed converter utilizes two split ac-coupled in-ductors that operate separately for positive and negative half gridcycles. This eliminates the shoot-through issue that is encounteredby traditional voltage source inverters, leading to enhanced systemreliability. Dead time is not required at both the high-frequencypulsewidth modulation switching commutation and the grid zero-crossing instants, improving the quality of the output ac-currentand increasing the converter efficiency. The split structure of theproposed inverter does not lead itself to the reverse-recovery issuesfor the main power switches and as such superjunction MOSFETscan be utilized without any reliability or efficiency penalties. SinceMOSFETs are utilized in the proposed converter high efficiencycan be achieved even at light load operations achieving a high Cal-ifornia energy commission (CEC) or European union efficiencyof the converter system. It also has the ability to operate at higherswitching frequencies while maintaining high efficiency. The higheroperating frequencies with high efficiency enables reduced coolingrequirements and results in system cost savings by shrinking pas-sive components. With two additional ac-side switches conductingthe currents during the freewheeling phases, the photovoltaic ar-ray is decoupled from the grid. This reduces the high-frequencycommon-mode voltage leading to minimized ground loop leakagecurrent. The operation principle, common-mode characteristic anddesign considerations of the proposed transformerless inverter areillustrated. The total losses of the power semiconductor devices ofseveral existing transformerless inverters which utilize MOSFETsas main switches are evaluated and compared. The experimentalresults with a 5 kW prototype circuit show 99.0% CEC efficiencyand 99.3% peak efficiency with a 20 kHz switching frequency. Thehigh reliability and efficiency of the proposed converter makes itvery attractive for single-phase transformerless photovoltaic in-verter applications.

Index Terms—California energy commission (CEC) efficiency,European union (EU) efficiency, MOSFET inverters, high ef-ficiency, high reliability, transformerless grid-connected photo-voltaic inverter.

Manuscript received April 24, 2012; revised July 4, 2012; accepted August9, 2012. Date of current version November 22, 2012. This work was supportedby the U.S. DOE under Award DE-EE0004681. Recommended for publicationby Associate Editor T. Suntio.

The authors are with Virginia Tech, Blacksburg, VA 24060 USA (e-mail:[email protected]; [email protected]; [email protected]; [email protected];[email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2012.2214237

I. INTRODUCTION

TRANSFORMERLESS photovoltaic (PV) grid-connectedinverters have the advantages of higher efficiency, lower

cost, less complexity, and smaller volume compared to theircounterparts with transformer galvanic isolation [1]–[27]. High-frequency common-mode (CM) voltages must be avoided for atransformerless PV grid-connected inverter because it will leadto a large charge/discharge current partially flowing through theinverter to the ground. This CM ground current will cause anincrease in the current harmonics, higher losses, safety prob-lems, and electromagnetic interference (EMI) issues [28]–[31].For a grid-connected PV system, energy yield and payback timeare greatly dependant on the inverter’s reliability and efficiency,which are regarded as two of the most significant characteristicsfor PV inverters.

In order to minimize the ground leakage current and im-prove the efficiency of the converter system, transformerlessPV inverters utilizing unipolar PWM control have been pre-sented [8]–[27]. The weighted California Energy Commission(CEC) or European Union (EU) efficiencies of most commer-cially available and literature-reported single-phase PV trans-formerless inverters are in the range of 96–98% [18]. Recently,several transformerless inverter topologies have been presentedthat use superjunction MOSFETs devices [11]–[13] as mainswitches to avoid the fixed voltage-drop and the tail-current in-duced turn-off losses of IGBTs to achieve ultra high efficiency(over 98% weighted efficiency).

One commercialized unipolar inverter topology, H5, as shownin Fig. 1(a), solves the ground leakage current issue and uses hy-brid MOSFET and IGBT devices to achieve high efficiency [11].The reported system peak and CEC efficiencies with an 8-kW converter system from the product datasheet is 98.3% and98%, respectively, with 345-V dc input voltage and a 16-kHzswitching frequency. However, this topology has high conduc-tion losses due to the fact that the current must conduct throughthree switches in series during the active phase. Another dis-advantage of the H5 is that the line-frequency switches S1 andS2 cannot utilize MOSFET devices because of the MOSFETbody diode’s slow reverse recovery. The slow reverse recoveryof the MOSFET body diode can induce large turn-on losses, hasa higher possibility of damage to the devices and leads to EMIproblems. Shoot-through issues associated with traditional fullbridge PWM inverters remain in the H5 topology due to the factthat the three active switches are series-connected to the dc bus.

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2236 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 5, MAY 2013

Fig. 1. Single-phase transformerless PV inverters using superjunctionMOSFETs: (a) H5, (b) H6, and (c) dual-paralleled-buck inverters.

Replacing the switch S5 of the H5 inverter with two splitswitches S5 and S6 into two phase legs and adding two free-wheeling diodes D5 and D6 for freewheeling current flows, theH6 topology was proposed in [12]. The H6 inverter can beimplemented using MOSFETs for the line frequency switch-ing devices, eliminating the use of less efficient IGBTs. Thereported peak efficiency and EU efficiency of a 300 W proto-type circuit were 98.3% and 98.1%, respectively, with 180 Vdc input voltage and 30 kHz switching frequency. The fixed-voltage conduction losses of the IGBTs used in the H5 in-verter are avoided in the H6 inverter topology improving ef-ficiency; however, there are higher conduction losses due tothe three series-connected switches in the current path dur-ing active phases. The shoot-through issues due to three activeswitches series connected to the dc-bus still remain in the H6topology. Another disadvantage to the H6 inverter is that whenthe inverter output voltage and current has a phase shift theMOSFET body diodes may be activated. This can cause bodydiode reverse-recovery issues and decrease the reliability of thesystem.

Another high-efficiency transformerless MOSFET invertertopology is the dual-paralleled-buck converter, as shown inFig. 1(c). The dual-parallel-buck converter was inversely de-rived from the dual-boost bridgeless power-factor correction(PFC) circuit in [13]. The dual-paralleled-buck inverter elimi-nates the problem of high conduction losses in the H5 and H6

inverter topologies because there are only two active switches inseries with the current path during active phases. The reportedmaximum and EU efficiencies of the dual-paralleled-buck in-verter using CoolMOS switches and SiC diodes tested on a4.5 kW prototype circuit were 99% and 98.8%, respectively,with an input voltage of 375 V and a switching frequency at16 kHz. The main issue of this topology is that the grid is di-rectly connected by two active switches S3 and S4 , which maycause a grid short-circuit problem, reducing the reliability ofthe topology. A dead time of 500 μs between the line-frequencyswitches S3 and S4 at the zero-crossing instants needed to beadded to avoid grid shoot-through. This adjustment to improvethe system reliability comes at the cost of high zero-crossingdistortion for the output grid current.

One key issue for a high efficiency and reliability transformer-less PV inverter is that in order to achieve high efficiency overa wide load range it is necessary to utilize MOSFETs for allswitching devices. Another key issue is that the inverter shouldnot have any shoot-through issues for higher reliability. In or-der to address these two key issues, a new inverter topology isproposed for single-phase transformerless PV grid-connectedsystems in this paper. The proposed transformerless PV inverterfeatures: 1) high reliability because there are no shoot-throughissues, 2) low output ac current distortion as a result of nodead-time requirements at every PWM switching commutationinstant as well as at grid zero-crossing instants, 3) minimizedCM leakage current because there are two additional ac-sideswitches that decouple the PV array from the grid during thefreewheeling phases, and 4) all the active switches of the pro-posed converter can reliably employ superjunction MOSFETssince it never has the chance to induce MOSFET body diodereverse recovery. As a result of the low conduction and switch-ing losses of the superjunction MOSFETs, the proposed con-verter can be designed to operate at higher switching frequencieswhile maintaining high system efficiency. Higher switching fre-quencies reduce the ac-current ripple and the size of passivecomponents.

Detailed power stage operation principle, PWM scheme,and CM leakage current analysis are described in this paper.The total losses of power devices for several existing MOS-FET inverters are comparatively evaluated. The loss reductionby replacing IGBTs with superjunction MOSFETs as powerswitches for the proposed transformerless inverter is analyzed.To verify the effectiveness and demonstrate the performance ofthe proposed transformerless inverter, a 5 kW prototype cir-cuit was built and tested using two different switching fre-quencies, 20 and 40 kHz. Experimental results show that theproposed inverter topology not only eliminates the issues ofMOSFET body diode reverse recovery, ground leakage current,and shoot-through; it also achieves 99.3% maximum efficiencyand 99.0% CEC efficiency with high-quality output currentwaveforms.

II. PROPOSED TOPOLOGY AND OPERATION ANALYSIS

Fig. 2 shows the circuit diagram of the proposed trans-formerlss PV inverter, which is composed of six MOSFETs

GU et al.: HIGH RELIABILITY AND EFFICIENCY SINGLE-PHASE TRANSFORMERLESS INVERTER 2237

Fig. 2. Proposed high efficiency and reliability PV transformless invertertopology.

Fig. 3. Gating signals of the proposed transformerless PV inverter.

switches (S1–S6), six diodes (D1–D6), and two split ac-coupledinductors L1 and L2 . The diodes D1–D4 perform voltage clamp-ing functions for active switches S1–S4 . The ac-side switch pairsare composed of S5 , D5 and S6 , D6 , respectively, which provideunidirectional current flow branches during the freewheelingphases decoupling the grid from the PV array and minimizingthe CM leakage current. Compared to the HERIC topology [9]the proposed inverter topology divides the ac side into two in-dependent units for positive and negative half cycle. In addi-tion to the high efficiency and low leakage current features, theproposed transformerless inverter avoids shoot-through enhanc-ing the reliability of the inverter. The inherent structure of theproposed inverter does not lead itself to the reverse recoveryissues for the main power switches and as such superjunctionMOSFETs can be utilized without any reliability or efficiencypenalties.

Fig. 3 illustrates the PWM scheme for the proposed inverter.When the reference signal Vcontrol is higher than zero, MOS-FETs S1 and S3 are switched simultaneously in the PWM modeand S5 is kept on as a polarity selection switch in the half gridcycle; the gating signals G2 , G4 , and G6 are low and S2 , S4 ,and S6 are inactive. Similarly, if the reference signal –Vcontrolis higher than zero, MOSFETs S2 and S4 are switched simulta-neously in the PWM mode and S6 is on as a polarity selectionswitch in the grid cycle; the gating signals G1 , G3 , and G5 arelow and S1 , S3 , and S5 are inactive.

Fig. 4 shows the four operation stages of the proposed in-verter within one grid cycle. In the positive half-line grid cycle,the high-frequency switches S1 and S3 are modulated by the si-nusoidal reference signal Vcontrol while S5 remains turned ON.

Fig. 4. Topological stages of the proposed inverter: (a) active stage of positivehalf-line cycle, (b) freewheeling stage of positive half-line cycle, (c) activestage of negative half-line cycle, and (d) freewheeling stage of negative half-linecycle.

When S1 and S3 are ON, diode D5 is reverse-biased, the induc-tor currents of iLo1 and iLo3 are equally charged, and energyis transferred from the dc source to the grid; when S1 and S3are deactivated, the switch S5 and diode D5 provide the inductorcurrent iL1 and iL3 a freewheeling path decoupling the PV panelfrom the grid to avoid the CM leakage current. Coupled-inductorL2 is inactive in the positive half-line grid cycle. Similarly, inthe negative half cycle, S2 and S4 are switched at high fre-quency and S6 remains ON. Freewheeling occurs through S6and D6 .


Fig. 5. Leakage current analysis model for the proposed transformerless PVinverter.

Fig. 6. Simplified CM leakage current analysis model for positive half-linecycle.

III. GROUND LOOP LEAKAGE CURRENT ANALYSIS AND

POWER DEVICES LOSSES CALCULATION AND EVALUATION

A. Ground Loop Leakage Current Analysisfor the Proposed Transformerless Inverter

A galvanic connection between the ground of the grid and thePV array exists in transformerless grid-connected PV systems.Large ground leakage currents may appear due to the high straycapacitance between the PV array and the ground [28]–[31].In order to analyze the ground loop leakage current, Fig. 5shows a model with the phase output points 1, 2, 3, and 4modeled as controlled voltage sources connected to the negativeterminal of the dc bus (N point). Fig. 5 clearly illustrates thestray elements influencing the ground leakage current, whichinclude: 1) the stray capacitance between PV array and groundCPVg ; 2) stray capacitances between the inverter devices andthe ground Cg1 − Cg4 ; and 3) the series impedance between theground connection points of the inverter and the grid Zg . Thedifferential-mode (DM) filter capacitor Cx and the CM filtercomponents LCM , CY 1 , and CY 2 are also shown in the model.

The value of the stray capacitances Cg1 , Cg2 , Cg3 , and Cg4 ofMOSFETs is very low compared with that of CPVg , thereforethe influence of these capacitors on the leakage current can beneglected. It is also noticed that the DM capacitor Cx does notaffect the CM leakage current. Moreover, during the positivehalf-line cycle, switches S2 , S4 , and S6 are kept deactivated;hence the controlled voltage sources V2N and V4N are equalto zero and can be removed. Consequently, a simplified CMleakage current model for the positive half-line cycle is derivedas shown in Fig. 6.

Fig. 7. Simplified single-loop CM model for positive half-line cycle.

With the help of the CM and DM concepts and by intro-ducing the equivalent circuits between N and E, a single-loopmode applicable to the CM leakage current analysis for the pos-itive half-line cycle of the proposed transformerless inverter isobtained, as shown in Fig. 7, with

VCM =V1N + V3N

2(1)

VDM = V1N − V3N . (2)

A total CM voltage VtCM [31] is defined as

VtCM = VCM + VDM · Lo1 − Lo3

2(Lo1 + Lo3)=

V1N + V3N

2

+ (V1N − V3N ) · Lo1 − Lo3

2(Lo1 + Lo3). (3)

It is clear that if the total CM voltage VtCM keeps constant,no CM current flows through the converter. For a well-designedcircuit with symmetrically structured magnetics, normally Lo1is equal to Lo3 . During the active stage of the positive half-linecycle, V1N is equal to Vdc , while V3N is equal to 0. Hence, thetotal CM voltage can be calculated as

VtCM =V1N + V3N

2+ (V1N − V3N ) · Lo1 − Lo3

2(Lo1 + Lo3)=

Vdc

2.

(4)During the freewheeling stage of the positive half-line cycle,

under the condition that S1 and S3 share the dc-link voltageequally when they are simultaneously turned OFF, one can ob-tain

V1N = V3N =Vdc

2. (5)

Therefore, the total CM voltage during the freewheeling stageis calculated as

VtCM =V1N + V3N

2+ (V1N − V3N ) · Lo1 − Lo3

2(Lo1 + Lo3)=

Vdc

2.

(6)Equations (4) and (6) indicate that the total CM voltage keeps

constant in the whole positive half-line cycle. As a result, no CMcurrent is excited. Similarly, during the whole negative half-linecycle, the CM leakage current mode is exactly the same asthe one during the positive half-line cycle; the only differenceis the activation of different devices. The total CM voltage inthe negative half-line cycle is also equal to Vdc /2. Therefore,


TABLE ISPECIFICATIONS AND POWER DEVICES FOR EFFICIENCY EVALUATION

in the whole grid cycle the total CM voltage keeps constant,minimizing CM ground leakage current.

B. Calculation and Comparison of the PowerSemiconductor Device Losses for Several ExistingMOSFET Transformerless Inverters

Since the efficiency of PV transformerless inverters is nor-mally compared by using weighted efficiency concepts, such as“CEC Efficiency” and “EU Efficiency,” it is critical to evaluatepower semiconductor device losses at different load conditionsrather than at nominal load condition when evaluating the effi-ciency of MOSFET transformerless PV inverters. The specifi-cations and power devices for efficiency evaluation of severalexisting MOSFET transformerless PV inverters [11]–[13] andthe proposed inverter are listed in Table I.

The first-order conduction voltage drop models of semicon-ductor devices can be given by

MOSFET : vds(t) = i(t) · Rds (7)

IGBT : vce(t) = Vt + i(t) · Rce (8)

Diode : vak(t) = Vf + i(t) · Rak (9)

where vds is the MOSFET drain–source voltage drop, Rds is theMOSFET drain–source on resistance, vce is the IGBT collector–emitter voltage drop, Vt is the IGBT equivalent voltage dropunder zero current condition, Rce is the IGBT on resistance,vak is the diode anode–cathode voltage drop, Vf is the diodeequivalent voltage drop under zero current condition, and Rak

is diode on resistance; i(t) is the inverter output current andexpressed as

i(t) = Im · sin(ωt) (10)

where Im is the peak inverter output current and ω is the angularfrequency of the inverter output current.

The duty ratios for active-stage devices and zero-stage devicesof unipolar grid-connected PWM inverters are expressed as (11)and (12), respectively

dactive(t) = M sin(ωt) (11)

dzero(t) = 1 − M sin(ωt). (12)

The conduction losses for active-stage MOSFET switches,active-stage IGBT switches, zero-stage MOSFET switches,

zero-stage IGBT switches, and zero-stage diodes can be cal-culated, respectively, from (13) to (17)

Pcon active MOSFET =12π

∫ π

0i(t)vds(t)dactive(t)dωt

= I2m Rds

2M

3π(13)

Pcon active IGBT =12π

∫ π

0i(t)vce(t)dactive(t)dωt

= Im VtM

4+ I2m Rce

2M

3π(14)

Pcon zero MOSFET =12π

∫ π

0i(t)vds(t)dzero(t)dωt

= I2m Rds

(14− 2M

3π

)(15)

Pcon zero IGBT =12π

∫ π

0i(t)vIGBT(t)dzero(t)dωt

= Im Vt

(1π− M

4

)+I2

m Rce

(14− 2M

3π

)

(16)

Pcon zero Diode =12π

∫ π

0i(t)vak(t)(1 − M sin(ωt))dωt

= Im Vf

(1π−M

4

)+I2

m Rak

(14− 2M

3π

).

(17)

For MOSFET devices, the main loss source for switchingtransitions is the capacitive turn-on loss resulting from the dis-charge of the junction capacitor Coss of MOSFETs [36], whichis dependent on the switched dc bus voltage and switching fre-quency. Normally, this capacitive turn-on energy dissipation canbe obtained from the device datasheet. Hence, the switching lossof active-stage MOSFETs can be simply expressed as

Psw active MOSFET = fswEoss(Vds). (18)

Another part of switching losses of active switches is inducedby the diode reverse recovery of the zero-stage diodes. Theswitching energy induced in the main switches during diodereverse recovery period can be approximated as

Ed rr = V dcIL

[(1 +

Irr

2IL

)ta +

Irr

4ILtb

]

= V dcILta + VdcIrr

4(2ta + tb) (19)

where IL is the switched load current, and the definitions ofta , tb , and Irr are shown in Fig. 8.

The switching loss of active-stage switches induced by thediode reverse recovery of the zero-stage devices can be obtainedby the integral of (19) in the whole grid cycle


Fig. 8. Simplified waveforms showing switching losses induced in the mainswitches and diodes during diode reverse recovery.

TABLE IITOTAL LOSSES OF POWER DEVICES AT DIFFERENT CEC OUTPUT POWER

CONDITIONS AT 20 KHZ SWITCHING FREQUENCY

Pd rr =12π

∫ π

0fsw [V dcIm sin(ωt)ta + Vdc

Irr

4(2ta + tb)]dωt

=(

Im taπ

+Irr(2ta + tb)

8

)Vdcfsw . (20)

The third part of the switching losses is the switching lossinduced in the diode during the diode reverse recovery interval,which can be approximated as

Pd sw = fsw (0.5Irr)(0.5Vdc)tb . (21)

By substituting the parameters from the datasheets ofIPW60R041C6 [33], IRGP4063D [34], and APT30DQ60B[35], the total losses calculated for CEC efficiency evaluationfor H5 [11], H6 [12], the dual-paralleled-buck (abbreviated asDPB) [13] transformerless PV inverters and the proposed in-verter are listed in Table II. It can be seen that the total powersemiconductor device losses for H5 is highest due to the IGBT’sfixed voltage-drop. The power devices’ losses of DPB and theproposed inverters are minimum and the proposed inverter canachieve the same high efficiency as the MOSFET DPB inverterin [13].

Fig. 9. Power semicondcutor device losses distribution comparison for H5,H6, DPB, and proposed transformerless PV inverters with 75% of the ratedoutput power.

The power semiconductor device losses distribution for H5,H6, DPB, and proposed inverters at 75% of the rated outputpower condition, which is the most dominant term in CEC ef-ficiency evaluation, is also shown in Fig. 9. It can be seen fromFig. 9 that the switching losses for these four MOSFET in-verters are almost the same. The conduction losses of H5 arehighest because of the IGBT’s fixed voltage drop. The con-duction losses of the H6 inverter are higher than DPB and theproposed inverters because one more switch is in series in thecurrent path during the active stages. The proposed transformer-less inverter can achieve the same high efficiency as the DPBMOSFET inverter in [13]. However, the reliability of the pro-posed converter is greatly enhanced and the quality of outputac current is improved compared to the DPB MOSFET inverterin [13].

C. Loss Reduction With MOSFETs Replacing IGBTsas Power Switches for the Proposed Transformerless Inverter

In order to highlight the advantages of employing superjunc-tion MOSFETs instead of IGBTs as the main switches to achieveultra high efficiency, the loss reduction with MOSFETs replac-ing IGBTs as power switches for the proposed transformerlessinverter is evaluated in this section.

The turn-on and turn-off switching losses for active-stageIGBTs can be calculated as (22) and (23), respectively

Psw on =1

2√

πfswαonIβo n

m kg onVdc

Vtest

Γ ((βon + 1)/2)Γ ((βon/2) + 1)

(22)

Psw off =1

2√

πfswαoff Iβo f f

m kg offVdc

Vtest

Γ ((βoff + 1)/2)Γ ((βoff /2) + 1)

(23)

where Γ(

β off +12

)/Γ

(β off

2 + 1)

= 1√π

∫ π

0 (sin ωt)β off dωt;

kg on is gate drive stiffness factor during turn-on; kg off is gatedrive stiffness factor during turn-off; αon and βon are turn-on


Fig. 10. Power semiconductor device losses distributaion comparion for theproposed inverter using MOSFETs and IGBTs at different output power:(a) 20 kHz switching frequency, and (b) 40 kHz switching frequency.

energy coefficients; αoff and βoff are turn-off energy coeffi-cients; Vdc is the actual switched dc bus voltage; and Vtest

is test voltage for switching energy coefficients on the IGBTdatasheets. αon , βon , αoff , and βoff can be obtained throughMATLAB curve fitting based on the Eon and Eoff of IGBTdatasheet.

The power semiconductor device losses distribution for theproposed inverter with MOSFETs and IGBTs at different CECoutput power with operating switching frequencies of 20 and40 kHz are comparatively illustrated in Fig. 10(a) and (b),respectively. From Fig. 10(b), when IGBTs are employed aspower devices, the total power semiconductor device losses ofthe proposed inverter are already more than 2.4% for all testedpower ranges in CEC efficiency calculation at 40 kHz switch-ing frequency. If other losses such as output inductor loss, gatedrive loss, and control board loss are included, the losses ofthe whole inverter system will be above 3%. As a result, theefficiency of the whole inverter system is less than 97%, whichis relatively low for a transformerless grid-connected PV in-verter. On the other hand, for the MOSFET inverter operatingat 40 kHz switching frequency, the total power semiconductordevice losses are less than 1.2% with the output power higherthan 30% of the rated power and no more than 2.4% even at 10%output power. If other losses are included, the CEC and EU ef-ficiencies of the whole inverter can still achieve an efficiencyover 98%, which is higher than most of the commercially avail-

TABLE IIISPECIFICATIONS AND POWER STAGE DEVICES FOR PROTOTYPE CIRCUIT

able transformerless PV inverters. Hence, a higher switchingfrequency operation can be adopted for the proposed inverterwith superjunction MOSFETs to reduce the output current rip-ple and the size of passive components, while the inverter stillmaintains an high-level system efficiency.

IV. EXPERIMENTAL VERIFICATIONS

A 5 kW prototype circuit has been designed, fabricated, andtested to verify the performance of the proposed transformerlessPV inverter topology.

Fig. 11 describes the block diagram of the complete grid-connected inverter test system. Gi(s) is a quasi-proportional-resonant current controller and Gc (s) is an admittance compen-sator [37]. Specifications of the inverter and the selection ofpower stage devices are shown in Table III. The photograph ofthe test-bed hardware prototype is shown in Fig. 12.

The experimental gating signals in the grid cycle and in thePWM cycle are shown in Fig. 13(a) and (b), respectively. Itcan be seen that the experimental gating signals G1 , G3 , andG5 agree with the analysis results of the PWM scheme and thegating signals of G1 and G3 are synchronized well.

The drain–source voltage waveforms of the switches S1 , S3 ,and S5 in the grid cycle and in the PWM cycle are shown inFig. 14(a) and (b), respectively. The voltage stresses of S1 , S3 ,and S5 are well clamped to the dc bus voltage, 380 V, withoutany voltage overstress. It can be seen from Fig. 14(b) that theswitches S1 and S3 almost evenly share the dc-link voltagewhen they switch OFF simultaneously, effectively minimizingthe ground loop leakage current.

Fig. 15 shows the experimental waveforms of the ground po-tential VEN . It can be seen that the high-ground leakage currentis avoided because the high-frequency voltage of the groundpotential is eliminated at every PWM switching commutationand at zero-crossing instants.


Fig. 11. Block diagram of the complete inverter test system.

Fig. 12. Test-bed hardware prototype.

The experimental waveforms of the grid current ig , the in-ductor currents iLo1 , and iLo2 under the 240 Vrms grid voltageand half-load conditions are shown in Fig. 16. This figure showsthat the proposed inverter presents high-power factor and low-harmonic distortion.

Fig. 17 shows the leakage current test waveforms, the CMleakage current is successfully limited with the peak value59.5 mA and rms value 10.33 mA, which are well below thelimitation requirements of the German standard VDE0126-1-1 [32].

Fig. 18 shows the measured efficiencies as a function of theoutput power for the proposed transformerless PV inverter atswitching frequencies of 20 and 40 kHz. Note that the presentedefficiency diagram covers the losses of the main power stageincluding power semiconductor device losses and output induc-tor losses, but it does not include the power consumption ofcontrol circuit and the associated driver circuit. The maximumexperimental efficiency of the prototype circuit is 99.3% and99.0% with 20 and 40 kHz switching frequency operations, re-

Fig. 13. Switch gating signals: in (a) grid cycle and (b) PWM cycle.

spectively. As shown in (24), the CEC efficiency is calculatedcombining different weighted factors at different output powerlevels

ηCEC = 0.04η10% + 0.05η20% + 0.12η30% + 0.21η50%

+ 0.53η75% + 0.05η100% . (24)

The calculated CEC efficiencies of the proposed transformer-less inverter at 20 and 40 kHz switching frequencies are 99%and 98.8%, respectively. The CEC efficiency at 40 kHz switch-ing frequency is about 0.2% lower than at 20 kHz switchingfrequency operation. However, 40 kHz operation can gain thebenefits of reduced output current ripple and the reduced size ofpassive components.


Fig. 14. Drain–source voltage waveforms of the switches S1 , S3 , and S5 : in(a) grid cycle and (b) in PWM cycle.

Fig. 15. Experimental waveforms of ground potential VEN , grid current, andcurrent of inductor Lo1 .

Fig. 16. Experimental waveforms of grid current and the inductor currentsiLo1 and iLo2 .

Fig. 17. Leakage current test waveforms.

Fig. 18. Measured efficiency as a function of the output power with switchingfrequencies at 20 and 40 kHz.

V. CONCLUSION

A high reliability and efficiency inverter for transformerlessPV grid-connected power generation systems is presented in thispaper. The main characteristics of the proposed transformerlessinverter are summarized as follows:

1) ultra high efficiency can be achieved over a wide outputpower range by reliably employing superjunction MOS-FETs for all switches since their body diodes are neveractivated;

2) no shoot-through issue leads to greatly enhanced reliabil-ity;

3) low ac output current distortion is achieved because deadtime is not needed at PWM switching commutation in-stants and grid-cycle zero-crossing instants;

4) low-ground loop CM leakage current is present as a resultof two additional unidirectional-current switches decou-pling the PV array from the grid during the zero stages;

5) higher switching frequency operation is allowed to reducethe output current ripple and the size of passive compo-nents while the inverter still maintains high efficiency;

6) the higher operating frequencies with high efficiency en-ables reduced cooling requirements and results in systemcost savings by shrinking passive components.

The experimental results tested on a 5 kW hardware prototypeverify the effectiveness of the proposed converter and show99.0% CEC efficiency. With the super high efficiency, low-leakage ground loop CM current, high quality of output currentand greatly enhanced reliability, the proposed topology is veryattractive for transformerless PV inverter applications.

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Bin Gu (S’11) received the B.S. degree from North-east Dianli University, Jilin, China, in 2002, andthe M.S. degree from Zhejiang University, Zhejiang,China, in 2005. He is currently working toward thePh.D. degree at the Future Energy Electronics Cen-ter, Virginia Polytechnic Institute and State Univer-sity (Virginia Tech), Blacksburg.

He was a Project Manager in Shanghai KinwayTechnologies, Inc., from 2005 to 2008, and an R&DEngineer at ABB (Shanghai) Robotics Research Cen-ter from 2008 to 2009. Since 2010, he has also been a

Graduate Research Assistant at Future Energy Electronics Center. His researchinterests include high-frequency soft-switching technique, hybrid-switchingtechnique, modeling and control of grid-tie converters, design of high effi-ciency and compactness power electronics converters for photovoltaic, electricvehicle battery charger, and energy storage applications.

Jason Dominic received the two B.S. degrees in elec-trical and computer engineering from Virginia Poly-technic Institute and State University (Virginia Tech),Blacksburg, in 2012, where he is currently workingtoward the Ph.D. degree at the Future Energy Elec-tronics Center.

Since 2011, he has also been an UndergraduateResearch Assistant at the Future Energy ElectronicsCenter. His research interests include electric vehiclebattery chargers, dc–dc converters, digital systems,magnetic design, and power electronics for photo-

voltaic systems.


Jih-Sheng Lai (S’85–M’89–SM’93–F’07) receivedthe M.S. and Ph.D. degrees in electrical engineeringfrom the University of Tennessee, Knoxville, in 1985and 1989, respectively.

From 1980 to 1983, he was the Head of the Elec-trical Engineering Department, Ming-Chi Institute ofTechnology, New Taipei City, Taiwan, where he initi-ated a power electronics program and received a grantfrom his college and a fellowship from the NationalScience Council to study abroad. In 1986, he becamea Staff Member of the University of Tennessee, where

he taught control systems and energy conversion courses. In 1989, he joinedthe Electric Power Research Institute (EPRI) Power Electronics ApplicationsCenter (PEAC), where he managed EPRI-sponsored power electronics researchprojects. In 1993, he was with the Oak Ridge National Laboratory as the PowerElectronics Lead Scientist, where he initiated a high-power electronics pro-gram and developed several novel high-power converters including multilevelconverters and soft-switching inverters. He is currently the James S. TuckerProfessor and the Director of the Future Energy Electronics Center, VirginiaPolytechnic Institute and State University (Virginia Tech), Blacksburg. He haspublished more than 265 technical papers and two books and received 20 U.S.patents. His main research areas are in high-efficiency power electronics con-versions for high power and energy applications.

Dr. Lai chaired the 2000 IEEE Workshop on Computers in Power Electronics(COMPEL 2000), the 2001 IEEE/DOE Future Energy Challenge, and the 2005IEEE Applied Power Electronics Conference and Exposition (APEC 2005).He received several distinctive awards including the Technical AchievementAward in Lockheed Martin Award Night, the three IEEE IAS Conference PaperAwards, the Best Paper Awards from IECON-97, IPEC-05, and PCC-07. In1996, he joined Virginia Polytechnic Institute and State University, where hisstudent teams won three awards from future energy challenge competitions andthe first place award from TI Enginous Prize Analog Design Competition.

Chien-Liang Chen (S’06–M’11) received the B.S.degree from National Taiwan University of Scienceand Technology, Taipei, Taiwan, in 2002, the M.S. de-gree from National Tsing-Hua University, Hsinchu,Taiwan, in 2004, and the Ph.D. degree from the Vir-ginia Polytechnic Institute and State University (Vir-ginia Tech), Blacksburg, in 2011, all in electrical en-gineering.

In February 2011, he was a Postdoctoral ResearchScholar at Future Energy Electronics Center, VirginiaTech. In July 2012, he joined International Rectifier

as a Senior System Application Engineer, Irvine, CA. His research interests in-clude grid-tie inverters, parallel inverters, mircogrid applications, soft-switchingtechniques, and point of load applications.

Thomas LaBella (S’07) received the B.S. and M.S.degrees in electrical engineering from the VirginiaPolytechnic Institute and State University (VirginiaTech), Blacksburg, in 2009 and 2011, respectively,where he is currently working toward the Ph.D. de-gree in power electronics.

Since 2009, he has also been a Graduate ResearchAssistant with the Future Energy Electronics Center,Virginia Tech. His research interests include powerconditioning system design and control for renewableenergy applications as well as sensorless control of

PM machines for high performance ac drives.

Baifeng Chen (S’11) received the B.S. degreein hydropower and digital engineering from theHuazhong University of Science and Technology,Wuhan, Hubei, China, and the M.S. degree in elec-trical engineering from Wuhan University, Wuhan,China, in 2008 and 2010, respectively. He is currentlyworking toward the Ph.D. degree at the Future EnergyElectronics Center, Virginia Tech, Blacksburg, VA.

Since 2010, he has also been a Graduate ResearchAssistant at Future Energy Electronics Center. Hisresearch interests include soft-switching techniques,

high-efficiency inverters for renewable energy application, and grid-connectedinverter control.

high reliability and efﬁciency single-phase

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