Nano Res.

Electronic Supplementary Material

High-precision transfer-printing and integration of vertically oriented semiconductor arrays for flexible device fabrication

Mark Triplett1,2, Hideki Nishimura4, Matthew Ombaba1, V. J. Logeeswarren1, Matthew Yee1, Kazim G. Polat1,

Jin Y. Oh1, Takashi Fuyuki4, François Léonard3, and M. Saif Islam1 ()

1 Center for Nano and Micro Manufacturing and Department of Electrical and Computer Engineering, University of California, Davis,

CA 95616, USA 2 Department of Physics, University of California, Davis, CA 95616, USA 3 Sandia National Laboratories, Livermore, CA 94551, USA 4 Microelectronic Device Science Laboratory, Nara Institute of Science and Technology, Japan

Supporting information to DOI 10.1007/s12274-014-0462-7

1 Stress simulation considerations

The forces applied to the simulated systems were calculated based on the maximum lateral force required

experimentally during the separation step of the hpVTP process. Figure S1 shows the forces applied during the

separation step for VLS Si nanowires (NWs) and for Si microwires (MWs) (Figs. S1(a) and S1(b), respectively).

For Si NWs a maximum force of F 32 N was required which gives an applied force of 0.2F μN per NW for

81.6 10n parallel NWs (1 in2 mother substrate area). A similar calculation for MWs gives an applied force

of 0.3 mNF .

For the simulation shown in the main text, a maximum stress at the root of the VLS NWs of ~ 8.3 GPa was

observed. This is >10% above a value recreated from the literature [S1], where the bending strength of VLS Si

NWs was empirically determined as a function of aspect ratio. Figure S1(c) shows a plot of this bending

strength including a fit to the data, assuming an exponential trend. Using this fit (empirical data) and the

length/diameter ratio of the VLS NWs used in this study (L/D = 10 μm/0.1 μm = 102), a maximum bending stress

of max = 7.34 GPa was calculated.

Figure S1(d) provides schematic details of the simulation showing meshing and geometrical considerations

as well as the constraints used in the simulation; Table S1 gives details of the parameters used in the simulation.

As seen in the rightmost image, a roller constraint was used on the Si mother substrate’s top surface allowing

the substrate to elastically displace laterally in response to the applied stress on the system without rotational

motion. A fixed constraint was applied to the bottom surface of the PMMA, holding the bottom surface of the

PMMA in place but allowing the remaining volume of the PMMA to continuously deform when stressed.

The possible transferable chip array is determined by the array area density on the mother substrate, the

Address correspondence to sislam@ucdavis.edu

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force required per NW during separation, and the maximum possible applied force by the separation tool.

Given a VLS NW array area density of 1/4 NW·μm–2, a required separation force of per NW of 0.2F μN, and

a maximum separation force tool limit of ~ 200 N, a maximum transferable area > 6 in2 is achievable.

2 Stress at the MW/aluminum interface

The strain experienced by a bent substrate (thickness t) with a radius of curvature R can be approximated by

the simple relation: S = t/2R [S2]. For the circumstances experienced by the flexible MW–polymer composite

and flexible substrate, this relation gives a value for a strain of 5 × 10–3, with an associated stress of (~ 850 MPa),

which is much smaller than the maximum bending stress.

Figure S1 (a) Experimental applied force during separation vs. time for a VLS Si NW array showing the maximum force required for separation. (b) Force vs. time curve for a Si MW array. (c) Plot of the bending strength of VLS Si NWs and fits to the data for empirical and finite element techniques, created from Ref. [S1]. (d) Simulation diagrams: Meshing characteristics used for the simulation, graphic of the model showing the embedded Si MW, and diagram depicting the constraints used for the simulation.

3 Thermionic field emission curve fitting

As seen by the fit in Fig. 4(b) of the main text, the nonlinearity of the observed I–V characteristics can be

accurately modeled by thermionic-field emission (TFE) through Schottky barriers at the contacts to the MW

array. The model is now explained in detail.

Deposited Al contacts typically create Schottky contact to n-type Si due to Fermi level pinning at the surface

of n-type Si, with Schottky barrier heights around 0.6–0.8 eV, depending on the quality of the interface [S3].

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Given these large Schottky barriers it is thus natural to expect that the contacts will dominate the transport. For

low doping levels the dominant current transport mechanism is thermionic emission over the Schottky barrier,

while for very high doping field emission (tunneling) of electrons directly through the barrier at the metal

Fermi level is possible due to the abruptness of the barrier.

Table S1 Stress simulation parameters

Parameter Young’s modulus (Si, PMMA) (GPa)

Poisson’s ratio (Si, PMMA) (N.A.)

Length (NW, MW) (µm)

Diameter (NW, MW) (µm)

Force applied (NW, MW) (N)

Value (170, 2.2) (0.22, 0.38 ) (10, 15) (0.1, 2.0) (0.2 × 10–6, 0.3 × 10–3)

For moderately high doping levels, tunneling of thermally excited electrons at energies between the Fermi

level and the top of the barrier occurs, due to the thinner barriers at higher energies (thermionic-field emission,

TFE). The importance of TFE can be assessed by considering the tunneling energy:

* D

00

s2

NqE

m

For 00

E kT , TFE becomes the most prominent conduction mechanism [S3]. In our study the n-type Si has a

doping level of ND ≈ 1018 cm–3 which gives 00 room

E kT . The system can be considered as metal–semiconductor–

metal layers consisting of n parallel MWs connected to Schottky diodes at the Al contacts as shown in Fig. S2.

When a positive (negative) bias is applied to the metal contact of Schottky diode 1 (D1) it is forward (reverse)

biased and D2 is reverse (forward) biased. The total applied bias is equal to the voltage drop across the two

diodes and across the MW array 1 2 array

V V V V . We can estimate the importance of the voltage drop across

the MWs as follows: for MWs 15 μm in length, 2 μm in diameter, doping of 1018 cm–3, and resistivity

0.02 cm , the voltage drop across the MW array for a current of 1 mA is: Varray = IR/n = 1.3 μV. Since a

current of this magnitude is observed for a voltage of about 0.5 V in the experiments, the voltage drop across

the MWs is about six orders of magnitude lower than the voltage drop across the contacts. We therefore neglect

this contribution in the rest of the calculation.

Figure S2 (a) Representative circuit diagram for the flexible MW devices containing back to back diodes for each Schottky contact and n parallel MW resistor elements. (b) Non-equilibrium band diagram associated with the circuit model and current mechanisms. The model takes into account disparity in barrier heights and contact interface effects.

For the TFE mechanism, the currents flowing through reverse and forward biased Schottky barriers are given

by Eq. (S1) and Eq. (S2), respectively [S3]:

**

Br 0r r r( / ) ( / )BrTFEr 00r r 2

00r

e (e 1)cosh ( / )

q E qVA TJ E q V

k E kT (S1)

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and

**

Bf 0f f 0 f( / ) ( ( )/ ) ( / )00f Bf fTFEf 2

00f

( )e e (e 1)

cosh ( / )n nq kT q E qV En

E q VA TJ

k E kT (S2)

where A** is the effective Richardson constant, T is the temperature, k is Boltzmann’s constant, q is the electron

charge, Br(f )

is the barrier height of the reverse (forward) biased diode, and the remaining constants are given

by

*

D

00r(f ) r(f )

s2

NqhE

m (S3)

0r(f ) 00r(f ) 00r(f )

coth( / )E E E kT (S4)

and

00rr

00r 00r/ tanh( / )

E

E kT E kT (S5)

In Eq. (S3) α is a prefactor added to account for differences in the MW–metal interfaces which are present

due to slight differences in processing for each contact. From current continuity requirements, the current flow

through each diode must be equal [S4]. We therefore have two requirements:

TFEr r TFEf f

( ) ( )J V J V (S6)

and

r f

V V V (S7)

Combining these with Eqs. (S1) and (S2) gives a system of nonlinear equations that needs to be solved for

each value of the applied bias, the solution of which gives values for the voltage drops and the current density

through each contact. A least squares fitting method was used to obtain the parameters for the fit reported in

the main text and listed in Table S2.

Table S2 Fit parameters used for the TFE model and optimal fit values

Parameter B1

(V) B2

(V) ND

(cm–3)

Area = nπ (1 µm)2

(µm2) α1 α2 m* εs

Value 0.81 0.68 1.45 × 1018 7.5 × 105 π 1.95 1.37 0.26 m0 11.9 ε0

References

[S1] Hoffmann, S.; Utke, I.; Moser, B.; Michler, J.; Christiansen, S. H.; Schmidt, V.; Senz, S.; Werner, P.; Gosele, U.; Ballif, C.

Measurement of the bending strength of vapor–liquid–solid grown silicon nanowires. Nano Lett. 2006, 6, 622–625.

[S2] Han, S. T.; Zhou, Y.; Roy, V. A. Towards the development of flexible non-volatile memories. Adv. Mater. 2013, 25, 5425–5449.

[S3] Sze, S. M.; Ng, K. K. Physics of Semiconductor Devices; John Wiley & Sons, Inc., 2007.

[S4] Sze, S. M.; Coleman, D. J.; Loya, A. Current transport in metal–semiconductor–metal (MSM) structures. Solid State Electron.

1971, 14, 1209–1219.