Chapter 4, part 2: Processes and Operating Systems

High Performance Embedded ComputingWayne Wolf

Topics

Operating systems mechanisms and overhead.

Embedded file systems. Concurrent system verification.

General-purpose vs. real-time OS Schedulers have very different goals in real-

time and general-purpose operating systems: Real-time scheduler must meet deadlines. General-purpose scheduler tries to distribute time

equally among processes. Early real-time operating systems:

Hunter/Ready OS for microcontrollers was developed in early 1980s.

Mach ran on VAX, etc., provided real-time characteristics on large platforms.

Memory management

Memory management allows RTOS to run outside applications. Cell phones run downloaded, user-installed

programs. Memory management helps the RTOS

manage a large virtual address space. Flash may be used as a paging device.

Windows CE memory management Flat 32-bit address space. Top 2 GB for kernel.

Statically mapped. Bottom 2 GB for user processes.

WinCE user memory space

64 slots of 32 MB each. Slot 0 is currently

running process. Slots 1-33 are the

processes. 32 processes max.

Object store, memory mapped files, resource mappings.

Slot 0: current process

Slot 1: DLLs

Slot 2: process

Slot 3: process

…

Slots 33-62: object store,memory mapped files

Slot 63: resource mappings

Mechanisms for real time operation Two key mechanisms for real time:

Interrupt handler. Scheduler.

Interrupt handler is part of the priority system. Also introduces overhead.

Scheduler determines ability to meet deadlines.

Interrupt handling in RTOSs

Interrupts have priorities set in hardware. These priorities supersede process priorities of the

processes. We want to spend as little time as possible in the

hardware priority space to avoid interfering with the scheduler.

Two layers of processing: Interrupt service routine (ISR) is dispatched by hardware. Interrupt service thread (IST) is a process.

Spend as little time in the ISR (hardware priorities), do most of the work in the IST (scheduler priorities).

Windows CE interrupts

Two types of ISRs: Static iSRs are built into kernel, one-way

communication to IST. Installable ISR can be dynamically loaded, uses

shared memory to communicate with IST.

Static ISR

Built into the kernel. SHx and MIPS must be written in assembler, limited

register availability. One-way communication from ISR to IST.

Can share a buffer but location must be predefined. Nested ISR support based on CPU, OEM’s

initialization. Stack is provided by the kernel.

Installable ISR

Can be dynamically loaded into kernel. Loads a C DLL. Can use shared memory for communication. ISRs are processed in the order they were

installed. Limited stack size.

WinCE 4.x interrupts

All higherenabled

HW

kernelO

AL

I-ISR

thread

All enabledExcept ID

All enabled

ISH Set event Enable ID

ISR ISR

ISR ISR

IST processing

device

Operating system overhead

Rhodes and Wolf studied context switching overhead using simulation.

Two-CPU system with bus. 100 random task graphs. Varying amounts of slack: none, 10%, 20%,

40%.

OS overhead results

[Rho99] © 1999 IEEE Computer Society

Support for scheduling

Adomat et al.: RTU scheduling accelerator supported up to 3 CPUs, evaluated readiness and priority.

Burleson et al.: Spring scheduling accelerator supported dynamically appearing tasks.

Kohout et al.: RTM scheduler used tree network to sort processes for scheduling.

Interprocess communication

IPC often used for large-scale communication in general-purpose systems.

Mailboxes are specialized memories, used for small, fast transfers.

Multimedia systems can be supported by quality-of-service (QoS) oriented interprocess communication services.

Power management

Advanced Configuration and Power Management (ACPI) standard defines power management levels: G3 mechanical off. G2 soft off. G1 sleeping. G0 working. Legacy state.

Stochastic power management Benini et al. modeled system and workload

as Markov chains. Service requester models workload as a

sequence of service requests. Service provider is a Markov chain whose

probabilities are controlled by power manager commands.

A linear program can find a minimum-power policy that meets performance constraints.

Embedded file systems

Generally means flash memory storage. Many embedded file systems need to be

compatible with PCs. Some file systems are primarily for reading,

others for reading and writing.

Flash memory characteristics

Flash is electrically erasable. Flash memory wears out during writing.

Early memories lasted for 10,000 cycles. Modern memories last for 1 million cycles.

Two types of flash: NOR flash operates similar to RAM. NAND is block oriented, gives more transient

failures. NAND is faster, may dominate in future.

Wear leveling

Flash memory systems move data to equalize wear during writes.

File allocation table gets the most writes---must be moved as well.

Formatting avoids multiple writes to file allocation table.

Virtual mapping

Virtual mapping system stands between file API and physical file system: Schedules erasures. Consolidates data. Identifies bad blocks. Moves data for wear

leveling. Virtual mapping system

keeps a table to translate virtual to physical addresses.

File system

Virtual mapping system

Flash memory

Virtual address

Physical address

Log-structured file system

Stores log of changes to file, not the original file. Also known as journaling. Developed for general-purpose systems, useful

for flash. Journaling Flash File System (JFFS)

maintains consistency during power losses. Yet Another Flash Filing System (YAFFS) is

log-structured file system for NAND flash.

Verification

System design is often specified using an abstract model. Allows verification before implementation. Eliminates unimportant programming details.

Interesting properties: A system is live if it moves through the states. A system is in deadlock if components are waiting

on each other.

Verification properties

Temporal logic is often used to describe system properties. Quantify over time and values.

Linear-time temporal logic models one timeline.

Branching-time temporal logic models a tree of timelines.

Example: []f(x) => f(x) is true at every time.

SPIN

Model checker for distributed software.

Protocols to be verified described in PROMELA language. Systems defined over

infinite input sequences. Combines depth-first

search, automaton reduction, binary decision diagrams, etc. to efficiently search the design space.

[Hol97] © 1997 IEEE

SPIN example

[Hol97] © 1997 IEEE