high performance drive structure

8/17/2019 High Performance Drive Structure

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European

Patent Office

̂ ̂ ^̂ ^̂ ̂ ^̂ ^̂ IÎ ^̂ II ̂ ̂ ̂ ^̂ ^̂ ̂^^ ̂ Î

Office

europeen

des brevets

E P 0 6 9 3 8 2 6 A 1

EUROPEAN PATENT APPLI CATI ON

(43)

Date of

publication:

(51)

|nt C|

e:

H03K 17/691

24.01.1996 Bulletin 1996/04

(21)

Application

number: 95304876.6

(22)

Date of

filing:

12.07.1995

(84)

Designated Contracting

States:

(72)

Inventor:

Timm,

Kenneth John

DE FR GB

Rockwall,

Texas 75087

(US)

(30)

Priority:

20.07.1994 US 278479

(74)

Representative:

Buckley, Christopher

Simon Thirsk

et

al

(71)

Applicant:

AT&T

Corp.

Woodford

Green,

Essex IG8 0TU

(GB)

New

York,

NY 10013-2412

(US)

(54) High per formanc e

drive

structure

for mosfet

power

switches

(57)

A

high performance

isolated

gate

drive circuit for

driving a

MOSFET

(Q1) uses a

MOSFET

pull-down

device

(Q2),

and

provides unusually

low

gate

discharge impedance, exceptionally

fast turn-off of the controlled switch

(Q1 )

and

reduced

power

dissipation

in the overall

gate

drive circuit. It also

provides superior

off-time noise

immunity.

FIG.

3

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Printed

by

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(FR)

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Saint-Denis,

75001 PARIS


2/7

1

EP 0 693 826 A1

2

Description

Field of the Invention

This invention relates

to

MOSFET drive circuits and

in

particular a high performance

isolated

gate

drive cir-

cuit.

Background

of the Invention

In

zero voltage switching (ZVS)

power

converter

topologies,

for

example,

fast turn-off of the

power

MOS-

FET is

very

important.

Power MOSFETs

must

be turned

"off" before their drain-source

capacitance

is

charged

significantly by

the

current

being

commutated "off". Fast

FETturn-on in ZVS

power

convertertopologies

is of less-

er concern

since self -commutation in the

turn-on

process

is inherent in the

operation

of these

topologies.

The

possibility

of

spurious

turn-on

in

high

power

MOSFET

gate

drive circuits becomes of

increasing con-

cern as switching speed and circuit power level grow,

particularly

in

bridge-type topologies. High

current

switching paths

and

parasitic couplings

from

high

volt-

age

commutation

injects spurious voltage spikes

into the

gate

circuits. When the

gates

require

the isolation

pro-

vided

by

transformers,

leakage

inductances inherent in

the

windings

increases the noise

susceptibility problems

as

well

as

reduces

switching speed.

Under

dynamic

op-

erational conditions instantaneous noise levels

may

rise

sufficiently

to turn

the MOSFETs "on"

at

inappropriate

times.

Catastrophic

circuit

failure,

primarily

due

to

cross

conduction,

may

then result.

Summary

of the Invention

According

to

the

invention,

a high performance

iso-

lated

gate

drive circuit for

driving a

MOSFET is

provided

as

claimed in claim

1

.

Brief

Description

of the

Drawing

FIG.

1

is

a

schematic of

a simple prior

art

gate

driver

for

a

power

MOSFET

switch;

FIG. 2 is

a

schematic of

prior

art

circuit

using a bipo-

lar transistor for

driving a

power

MOSFET

switch;

FIG. 3 is

a

schematic of

a

gate

driver for

a

power

MOSFET switch

embodying

the

principles

of the

invention;

and

FIG.

4

is

a

schematic of

a practical

circuit

implemen-

tation of

a

gate

driver for

a

power

MOSFET switch

embodying

the

principles

of the invention.

Detailed

Description

FIG.

1

shows the schematic of

a prior

art

gate-drive

circuit. This circuit exhibits several of the

following

short-

comings.

One

shortcoming

is that the

gate

voltage

rise

and fall times of the

power

MOSFET

Q1

are

slowed

by

the need

to

conduct the

gate

charge through

the

leakage

5

reactance

of the transformer T1

.

An

excess

of

energy

is

wasted

by driving

the

capacitance

of Cin1 both

positive

and

negative

to

the full

extent

of the

input voltage wave-

form. The capacitance Cin1 is generally supplied by the

gate

source parasitic capacitance

of the MOSFET

Q1

.

If

10

needed

a

discrete

capacitance

may

be used for Cin1

.

In

addition the drive circuit

must

be

capable

of

sinking

the

turn-off

current

of the

power

MOSFET

Q1

.

The series

resistor, R1,

included in the drive circuit

serves

two

purposes:

it reduces the

Q

of the

resonant

is

circuit formed

by

the transformer

leakage

inductance

and

gate

input capacitance

Cin1. This reduction is

re-

quired

to

minimize

ringing

of the

gate-drive voltage sig-

nal. It

serves

to

control EMI

generation by slowing

the

turn-on

time of

power

MOSFET

Q1.

This feature is

not

20

needed since this

phenomenon

is

not

an

issue in

reso-

nant switching ZVS topologies.

To

speed

up

the turn-off of

power

MOSFET

Q1,

a

diode CR1 is

placed

in

parallel

with the resistor R1

to

bypass

it. While this does reduce turn-off

time,

the dis-

25

charge

current

slew

rate

(di/dt)

is limited

by

the

leakage

inductance of T1

through

which it flows.

Switching speed

is still

inadequate

and

to

achieve further

improvement

active

pull

down

must

be utilized.

FIG. 2 illustrates

a prior

art

drive

circuit,

using an ac-

30

tive

pull-down bipolar

transistor

Q2,

to

reduce switch-off

time. This circuit also exhibits

some design challenges

as

described below A

bipolar

transistor is

a

very

nonlin-

ear

device,

its

current

gain (hfe)

is

highly dependent on

collector

current.

Toturn

powerMOSFETQI

"off"

rapidly,

35

a large pulse

current

(a

few

amps)

needs

to

be conduct-

ed. A

correspondingly large

base

current

is

required

be-

cause

of the reduced hfe. The drive circuits

must

be

ca-

pable

of

supporting

these

large

currents at

the

cost

of

larger

devices and

higher

power

dissipation. Storage

40

times in

a bipolar

devices

go up

with increased

current

resulting

in less than

expected performance.

A

possibility

of

exceeding

the

bipolar

transistor

Veb(max) rating,

the

reverse

bias

piv,

also exists. The value of R1 needs

to

be

carefully

chosen

on

the basis of

conflicting

device

45

specifications

and

switching speed.

Performance usual-

ly

falls short of what

can

be obtained

by using

the below

circuitry

of the invention.

FIG. 3 shows

a simplified diagram

of

a

drive circuit

embodying

the

principles

of the invention. The

primary

so

and

secondary

transformer

windings

shown connected

with dotted lines

represent

important parasitic

compo-

nents

inherent in the

physical

structures

of the devices.

The drive

signal applied

to

the isolation transformer

T1 is

a rectangular, bipolar

waveform,

and has

an ampli-

55

tude of

typically

1

2

to 1

5V. This

signal

is derived from

a

low

impedance

source,

e.g.

totem-

pole

connected

MOSFETs. To maintain low

impedance

it is desirable

to

have

tight coupling

between the

primary

and

secondary

2


3/7

3

EP 0 693 826 A1

4

circuits. This

can

be

accomplished

with

a unity

turns

ratio CI

transformer and bifilar

windings,

if

permissible.

The drive

waveform

can

be divided into three distinct

regions:

A 1.

first

region

has

a positive polarity

with

an amplitude

of

+Vpk corresponding

to Q1

being

"on". Asecond

region

s

has

a negative polarity

with

amplitude

of

-Vpk corre-

sponding

to Q1

being

"off" and the

gate-source

imped-

ance held low. A third region has a zero amplitude or

"dead-time"

occurring

between the first and second

re-

gions

and

Q1 must

be "off".

10

The drive MOSFET

Q2

exhibits

high

transconduct-

ance (gm)

for all

operational

conditions,

draws

no steady

state

gate

current

and

imposes a

minimum load

on

the

gate

driver circuits. It is therefore able

to

support

large

drain

currents

without

incurring

the base

current

load

15

penalty imposed by bipolar

transistor devices.

With

positive voltage

at

the dotted ends of the

trans-

former T1

,

a pulse

of

current

flows in the

gate

circuit

loop.

This

loop

consists of the

secondary

of T1

,

the

gate

input

capacitance

of

Q1

(Cin1)

and diode CR1. Cin1 is

20

charged to +Vpk turning power MOSFET Q1 "on" when

Vgs(th)

is reached. At this

point,

drive MOSFET

Q2

is

effectively

out

of the circuit.

During

the dead-time

interval,

which

may

be

as

little 2.

as

100nS,

power

MOSFET

Q1 must

"off".

Capacitor

Cin1

25

enters

this time

period

with

an

initial

voltage

of

+Vpk.

When the transformer

secondary voltage drops

to

zero

at

the

beginning

of the dead-time

interval,

the

voltage on

capacitor

Cin

1

causes charge

to

be transferred

to

capac-

3.

itor Cin2.

By design

Cin1

»

Cin2,

so,

while

charge

is

30

shared between the

two

capacitors,

there is little

voltage

droop

and drive MOSFET

Q2

turns"on"

strongly.

Since,

drive MOSFET

Q2's

discharge path bypasses

the leak-

age reactance

of T1

,

the

gate voltage

of

power

MOSFET

Q1

falls

very

rapidly

towards

Vgs(th)2.

Drive MOSFET

35

4.

Q2 must

be

so

chosen that its threshold

voltage, Vgs(th)

2


4/7

5

EP 0 693 826 A1

6

8. A

gate

drive circuit for

a

power

MOSFET

as

claimed

in claim

1,

further

including:

circuitry including a parallel

connected diode

and resistor

(CR3, R3) connecting a

gate

electrode

of the

power

MOSFET

to

the

secondary winding.

s

9. A

gate

drive circuit for

a

power

MOSFET

as

claimed

in claim 1, further including:

a

resistor

(R2) shunting

the drain-source elec-

trodes of the drive MOSFET.

10

15

20

25

30

35

40

45

50

55

4


5/7

EP 0 693 826 A1

FIG.

1

(Prior

a r t )

o p k J 2

- v p k

T1

CR1

R1

J

Cinl

Q1

FIG. 2

(Prior

a r t )

r p k

_ n

0

- v p k

T1

Vs

CI

R1

J

Q2

Q1

5


6/7

EP 0 693 826 A1

FIG.

3

FIG.

4

+vpk

0

-vpk

n

Q1

6


7/7

EP 0 693 826 A1

p

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