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IBM Power and Cooling Technology Symposium

September 20-21st

High Efficiency SMPS with

Digital Loop ControlPresenter: Walter MosaCompany: MagneTek

Welcome

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FE 1U 800-12High Density AC/DC Front-End

Design goals :

- 12V bus output

-800W power output

-20W/cu.in power density

-Wide input range

-Dimensions : Modular, 1U rack

-Analog and/or DSP controller

-Hot plug

- Low cost

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FE 1U 800-12High Density AC/DC Front-End

How to achieve it :

- PFC stage with min. efficiency of 97 % at 220Vac , 94% at 110Vac ; therefore special topology

- DC/DC converter with min. efficiency of 94% ; therefore ZVS topology

- Cooling optimisation and appropriate heat management

- Layout optimisation

- Last generation’s semiconductors utilization

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FE 1U 800-12High Density AC/DC Front-End

Result :

-Efficiency 92%

-Digital Loop Control (DSP)

-Density 20W/inch3

-Input Full range

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Planar Transformer

The transformer features

•Primary side 12 layer PCB, 125micron of base copper

•Secondary side isolated. Copper winding geometry designed for maximum power density .

•Total 6W power losses

•200Khz frequency operation with phase shifted topology and current- doublerrectification.

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PFC stage

Interleaved boost topology allows the following advantages:

-EMI filter volume reduction

-boost inductor volume reduction

-boost inductor split for better heat handling

-low switching losses with high switching frequency

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Boost configuration

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Boost configuration Average Model

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PFC interleaved working principles:• Two stages of standard boost topology run 180° out of phase.• The control circuitry provides to collect the information coming from the bus voltage error signal, the rectified line voltage signal and the voltage feed-forward required by the multiplier stage. • The output signal of the multiplier stage is the input of the current error amplifier, which compares the total actual current level with the desired one• The error signal obtained is used as input to the comparators which sense the currents flowing into both switching mosfets providing in this way balanced currents across the chokes.•Slope compensation is provided on both branches since 50% of duty cycle is exceeded, • Current sensing transformers are used for minimum losses.

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PFC losses calculated :

The components/stages which are responsible of the main losses of the input + boost are :

- input diodes bridge at 800W o/p , 100V input Vac : 16W- PFC switching mosfets : 16W- PFC chokes : 8W- PFC diodes :4W- EMI filter : 4W - various other losses for a total of 54W- these losses drop to 28W at 200Vac input voltage

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DC/DC Schematic

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DC/DC Converter configuration :

Primary Side

•This converter is based on the well known ZVT phase bridge topology.•The pwm controller is Ucc 2895 ; double high side driver are used for switching mosfets. •Switching devices for the bridge are optimised for low gate charge and fast recovery internal diodes.

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DC/DC Converter configuration :

Secondary Side

•The same signals from the bridge are used to drive, through an isolation transformer, the secondary side mosfets, which replace less efficient diodes (using 4 mosfets in parallel for each leg with 3.8mohm Rdson allows to save approx. 25W losses compared to a schottky solution); synchronous rectification is also achieved.•Molypermalloy high flux chokes are connected in a current doubler configuration for low losses and proper thermal management.•Four paralleled mosfets, 1.8mohm Rdson each, perform the or-ing function for hot plug operation•Output capacitors are polymeric type for low ESR•Layout is a key factor for optimal thermal management.

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DC/DC converter losses calculated :The components/stages which are responsible of the main losses of the DC/DC converter are:

- mosfets of full bridge : 8W- mosfets of secondary rectification : 8W- output chokes : 6W- main transformer : 6W- or-ing mosfets : 4W- various other losses for a total of 52W

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•Before releasing prototypes we simulated airflow tostudy where to place the major components.

•The resulting layout permits to have optimum coolingwith difficult boundary condition.

•The worst condition that we have simulated withoutlost in efficiency and without derating is the following:

•Air 50°C, Pressure 1ATM, Output 800W

•Fan utilized NMB 1606KL-04W , CFM 14

Thermal Management

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Thermal Management

The temperature estimated duringour simulation 89,48°C, have beenconfirmed using thermocouple on the phisical prototype.

The main temperature checked was on the Mosfet and the measured temperature at the same worstboundary condition was 91,4°C (+2°C delta).

9,84”

1,65”

2,36”

Air 50°C,

Pressure 1ATM,

Power Output 800W

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• Analog to digital conversion. Signals are converted to digital as soon as practical, this way increasing noise immunity• Configuration parameters. Configuration values are set using data memory instead of passive components (analog power),increasing system reusability and reliability, and reducing the costof power and system’s dimensions.

• Communication. Digital power provide a digital communication interface, enabling a system-level controller to monitor the power supply.• Amount of informations. Digital power will enable the system to be more aware about the power stage, hence increasing system performance and reliability (load sharing), and enabling it to make power policy decisions.

• Complex control algorithms more efficiency. Digital power allow for:Non – linear control Adaptive control Multi-phase control.

Why Digital Control?

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• Choosing control modeWe have chosen Average Current Mode control

• Choosing continuos plant modelWe have chosen a small-signal model of the input booster, that allow for a better performance of the controller when working in discontinuos current mode.

G(s) = Vout(s) / duty(s).

• Compute Discrete Plant ModelPlant Model = S&H + Power Stage + Computational Delay

G(z)= Z{S(s)*G(s)*D(s)}

C(z)Controller

D(s) = exp(-s*Td)Comp. Delay ( Td )

G(s)Plant

S(s) = (1-exp(-s*Ts))/sSampling ( Ts )

+ -

Vref Voute(n) u(n)

Digital PFC Control Design

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• Compute discrete controller C(z)We can now compute the discrete controller for current over the input coil and for voltage on the output capacitor of the booster, selecting each time the right:

• Generic transfer function (es. 2 poles / 2 zeros).• Bandwith.

• Discrete controller SW implementationFrom the discrete transfer function C(z) = U(z) / E(z), we obtain the digital controller:

U(n)= F[U(n-1), U(n-2), …, U(n-k); E(n), E(n-1), …, E(n-j)].

Where:

U(i-k) = U(i)*(z^(-k)),E(i-j) = E(i)*(z^(-j)).

Digital PFC Control Design

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Current Controller Open Loop Bode Diagram

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Voltage Controller Open Voltage Controller Open LoopLoop BodeBode DiagramDiagram

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Err_V

CL

Plant

+-

VoltageController

-+

CurrentController

-+ | . |

duty

I

Vout

VACin

Err_I

1/Vinrms^2

Vref

100-120Hznotch filter

Iref

PFC Controller

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PFC Digital controller

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PH_1

PH_2

Input Signals for PFCPWMs to PFC

PWMs to DC/DC

Input Signals for DC/DC

DSP Schematic

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Scope Plot

V Bulk

V Drain

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Scope Plot

Sampling of DrainCurrent

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V Drain

Total Current of the chokes

Scope Plot

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Thanks

for

your attentionIBM Power and Cooling Technology Symposium

September 20-21st