hierarchical constraint transformation based on geneticadoboli/papers/nagu_integration05.pdf ·...

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3B2v8:06a=w ðDec 5 2003Þ:51cXML:ver:5:0:1 VLSI : 705 Prod:Type:FTP

pp:1223ðcol:fig::NILÞED:VinuthaMB

PAGN:Jay SCAN:V4soft

INTEGRATION, the VLSI journal ] (]]]]) ]]]–]]]

0167-9260/$ -

doi:10.1016/j.

�CorresponE-mail add

acuse.edu (A.

www.elsevier.com/locate/vlsi

ROOFHierarchical constraint transformation based on genetic

optimization for analog system synthesis

Nagu Dhanwadaa, Alex Dobolib,�, Adrian Nunez-Aldanac, Ranga Vemurid

aIBM Microelectronics, Hopewell Junction, NY, 12533, USAbDepartment of Electrical and Computer Engineering, Stony Brook University, Stony Brook, NY, 11794-2350, USAcDepartment of Electrical Engineering and Computer Science, Syracuse University, Syracuse, NY, 13244-0001, USAdDepartment of Electrical and Computer Engineering and Computer Science, University of Cincinnati, Cincinnati, OH

45221-0030, USA

Received 30 August 2004; received in revised form 12 June 2005; accepted 27 July 2005

P

CORRECTEDAbstract

In a top–down analog system design methodology, the task of translating high-level performancespecifications and constraints into component level parameters is termed as constraint transformation. Inthis paper, we presented a genetic optimization based approach to constraint transformation. The salientfeatures of this are a search space profiling technique and a hierarchical two-level genetic optimizationengine. Performance estimation for profiling and hierarchical optimization uses both the performanceequations embedded in an analog performance estimation module as well as detailed SPICE simulation. Wedescribed the constraint transformation method, and each of its constituents. The effectiveness of the two-level hierarchical approach was established by comparing it against a flat non-hierarchical method.Application of the constraint transformation method in the synthesis of design examples was also presentedin the paper.r 2005 Published by Elsevier B.V.

Keywords: Analog synthesis; Constraint transformation; Genetic algorithms

UN

see front matter r 2005 Published by Elsevier B.V.

vlsi.2005.07.003

ding author. Tel.: +1 631 632 1611; fax: +1 631 632 8494.

resses: [email protected] (N. Dhanwada), [email protected] (A. Doboli), [email protected]

Nunez-Aldana), [email protected] (R. Vemuri).

www.elsevier.com/locate/vlsi

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1. Introduction

In a top–down analog system synthesis methodology [1,2], it is necessary to establish amechanism to communicate the performance specifications and constraints of the design elementsemployed at different levels [3]. This task is called constraint transformation [1,4], and is critical intackling large designs by decomposing systems into their building blocks. Constrainttransformation can be performed at different abstraction levels across the design hierarchy.The role of constraint transformation is to map the high-level constraints onto lower levelconstraints at each level of hierarchy. Fig. 1 shows subsequent abstraction levels for the analogdesign process. The system level performance parameters are the constraints like area, power,gain, bandwidth, linearity, and so on, of the overall system. The next level would be thecomponent performance level that refers to individual performances of the components present inthe system level net-list. Following this would be component design parameter abstraction level.This level consists of parameters like the bias currents, gain-w/l ratios, output impedances of thecomponent that would to an extent, fix the transistor level design of the component. Fixing thecomponent design parameters completes the transistor level design of the component to a largedegree. The next level consists of the sizes of transistors in the components. The final level wouldbe the layout level, where the constraints would be on the spacing between devices, symmetry of

UNCORRECTED P

A,Slew

A,BW

A,Gain

A,Power

B,Slew

B,BW

B,Area

B,Power

A,Ibias

A,GainW_L

A,Adm

A,Zout

A,Curr Src

C,Ibias

C,GainW_L

C,Adm

C,Zout

C,Diff Amp

Sys,area, Sys

,power,

Sys,gain, Sys

,BW

ParametersComponent Design

ParametersSystem Performance

Parameters

A

B

C Component Performance

Layout Level

SizesComponent Transistor

Cosntraints

Model

Constraint

Level

Component

Model

Constraint

System Level

Spacing, Alignment,Symmetry

W3, L3,...W1, L1, W2, L2

System

Layout

Fig. 1. Levels of constraint abstraction.

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the devices, etc. The role of a constraint transformation mechanism becomes very crucial withincrease in the circuit size. This is because it would be very hard to design a large system at thetransistor level to meet overall system performance constraints, due to the complexity involved interms of the number of parameters that need to be considered simultaneously.As shown in Fig. 1, a system level constraint model would be one that relates the system

performances with the component level performances. This can be defined by the followingtransformation function:

SP Fðcp1; cp2; cpnÞ,

where cp1; cp2; . . . ; cpn are the n component performance parameters and SP is the set of systemperformance parameters. In a similar way, the component level constraint model refers to one thatrelates component performance parameters to component design parameters. This can also bedefined by a similar function:

CP Gðcd1; cd2; . . . ; cdnÞ,

where cd1; cd2; . . . ; cdn are the component design parameters and CP is the set of componentperformance parameters.With the analog system descriptions moving to higher levels of abstraction [5], there is a clear

need to ensure that the high-level performance specifications be translated into component levelparameters. System level constraint transformation is a challenging task considering the largenumber of involved parameters, the existence of strong, non-linear correlations between designparameters, as well as the large amount of required designer expertise. Given an analog systemlevel net-list, where only the functionality of the components is known, and a set of systemperformance specifications, we present a technique that selects an implementation for thecomponents, and transforms the system level specifications into design parameters for thecomponents. These techniques when used with existing cell-level [6] and layout level design toolswould form an entire design flow for analog systems. Fig. 2 shows such a flow for the design ofanalog systems.We defined the constraint transformation problem in the context of an analog synthesis

environment that transforms behavioral descriptions of analog designs onto a layout [5]. In thisscenario, the task of a constraint transformation mechanism is to translate specifications at higherlevels of abstraction into lower level parameters that can be handled by tools that exist in thesynthesis framework. For performing the transformation, it is necessary to express the high-levelparameters as a function of the lower level parameters [4]. Arsintescu [4] refers to this as thetransformation function. The two main phases of such a constraint transformation process are [7]:
C �
UNGenerating a model relating the performance measures at a given level to lower-level designparameters known as constraint model generation. This phase also computes a transformation

function relating the two sets of higher-level parameters with the lower-level ones.
� Computing values for the component design parameters that satisfy the system levelconstraints, known as constraint allocation or constraint model solving.
In this paper, we focus on a constraint model solving technique that finds values for thecomponent design parameters that satisfy the system level constraints. Constraint model solving is

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System-Level

Topology

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System Area

System Power

System Gain

System Bandwidth

B3.SR, B3.UGFB3.Ibias, B3.ZoutB3.area, B3.pow,

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E.4C.2A1.SR, A1.UGF

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C2.SR, C2.UGFC2.Ibias, C2.ZoutC2.area, C2.pow,

D1.SR, D1.UGFD1.Ibias, D1.ZoutD1.area, D1.pow,

E4.SR, E4.UGFE4.Ibias, E4.ZoutE4.area, E4.pow,

Module Parameters

+ Implementation

Circuit

and Layout

Synthesis

Layout

System Topology System Constraints

Analog System Description + Constraints

Constraint

Transformation

& Module Selection

Fig. 2. A top–down analog system synthesis flow.


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formulated as a search problem, and a genetic algorithm (GA) [13] based optimization engine isused to tackle this. The optimization engine searches the space of component parameters tocompute a component level parameter solution that satisfies system performance constraints. Theoptimizer uses the constraint model to evaluate the quality of solutions generated. The size of theoptimization space involved in the transition from system level performances to componentdesign parameters causes problems to traditional optimization techniques. This necessitatesimprovements to traditional optimization for which we present a hierarchical, profile-basedoptimization method [10,11]. The proposed hierarchical search engine includes two levels: the toplevel performs system level performance allocation, and the bottom level executes componentsynthesis. Two new interval-oriented GA operators are presented for interval crossover andinterval mutation. These operators intelligently guide the search process towards constraintsatisfying solutions.In our work, we used two ways to perform the task of system level constraint model generation

[12]. One approach is based on using a numerical circuit simulator, like SPICE [8]. The other oneuses a hierarchical network covering algorithm in conjunction with analytic performancecomposition equations of basic block configurations (split, cascade, and join). The componentlevel constraint model generation is done using an analog performance estimator [9] that containsanalog circuit performance models at various levels of abstraction. The simulation basedapproach is extremely accurate but requires larger execution times. Therefore, it should be usedfor smaller but tightly coupled circuits operating at high frequencies. The composition basedmethod is less accurate but extremely fast. This makes it suitable for large, loosely coupledsystems working at frequencies up to several hundreds of kHz.There are several important aspects that differentiate the proposed constraint transformation

method from similar work [1,7,4,14]. The proposed algorithms are used for automatic synthesisfrom high-level specifications in VHDL-AMS [5]. Also, techniques are more flexible and easier touse, as they are automated and do not need much designer insight into a system. The system andcomponent profiles used in speeding-up optimization are automatically computed, andhierarchical optimization always considers two levels: the component and the system level.Finally, the proposed algorithms can tackle more diverse systems (including systems with non-linearities), are faster, and offer improved results as compared to basic optimization methods.The paper is organized as follows. The next section discusses related work in the area. The

optimization engine that performs the model solving phase is described in Section 3. We presentexperimental results comparing the hierarchical approach with a flat one to demonstrate itseffectiveness. Finally, we also present results of constraint transformation on a few designexamples.
C
UN2. Related work

In this section we discuss the proposed techniques in relation to some of the significant workson constraint transformation in analog CAD. A top–down design methodology for analogintegrated circuits was presented by Chang et al. in [1]. This consisted of a process involving earlyverification based on behavioral simulation, hierarchical propagation of constraints acrosssuccessive levels of abstraction, and bottom–up design verification. The focus was on defining the

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design methodology itself, and providing support for automatic synthesis. In the work beingpresented we are considering the task of constraint transformation in an automatic synthesisenvironment that accepts high-level language descriptions of analog systems. In the methodologypresented in [1], for the constraint transformation phase, a behavioral or device level simulatorhas to be used to determine the performance variables that can be supported or an explicittransformation function should be defined for each particular situation. The constraint model thatis generated on a case by case basis is solved using optimization tools based on linear and non-linear programming. These linear and non-linear programming based methods would turn out tobe expensive for problems having large number of variables. In the work described here, we usegenetic algorithm (GA) [13] based heuristic optimizers to perform the task of constraint modelsolving, and also present techniques to improve the performance of optimization.Arsintescu [4,7] coined the term constraint transformation, and presented an analytic technique

that performs AC constraint transformation for a class of linear continuous time analog circuits.The focus was on constraint model generation for such circuits based on hierarchical parametermodeling. The circuit transfer function was used to relate circuit performance attributes to designparameters and parasitic constraints. This work assumes that the circuit has been fully designed apriori. It might not be possible to assume this during an automatic synthesis process frombehavior onwards, which is the context of the work being presented in this paper. Also, theconstraint transformation mechanism in the context of a behavioral synthesis environment shouldexplore all possibilities that exist to make the design meet imposed performance constraints. Inour work we do not assume the circuit to be designed fully a priori. The flexibility available inchanging the topologies of the components in a system are also exploited to achieve a particularconstraint transformation.A technique that partitions design constraints was presented by Leenaerts in [14]. This work

introduces a technique for the constraint model solving part in constraint transformation. Anumerical interval solver is used to do this task. This is limited by the solution technique that canhandle linear equations only. As with any analytical technique this method suffers from the curseof dimensionality [13], where it might not scale well for large design problems. In our work wepresent techniques for the entire constraint transformation problem based on heuristic GA basedoptimization techniques that would not face problems associated with analytical methods.A lot of work has been done in automating cell level analog design that results in a sized

transistor net-list for the circuit [6,15–18]. DARWIN [15], uses a genetic algorithm to synthesizeCMOS operational amplifiers. FASY [17] uses a fuzzy-logic based approach to analog circuitsynthesis. As already explained, the proposed constraint transformation methods can be used inconjunction with cell level design tools to complete the analog system synthesis flow shown in Fig.2.
N U3. Constraint transformation method
Many of the design optimization problems suffer from the curse of dimensionality, where theperformance of the optimization method rapidly deteriorates with the increase in the number ofdimensions in the space. Similarly, in our case, the size of the optimization space in thetransforming system performance constraints to component design parameters requires the

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improvements to the basic optimization techniques for constraint model solving. In theoptimization engine, we used techniques based on search space profiling and decomposition (ofthe system into components) to improve the optimization process. We organized the hierarchicaloptimization into two levels: the top level performance allocation GA computes componentperformances that satisfy system level performance constraints. Then, for each component, thedesign parameter ranges satisfying component performance constraints are computed by thelower level component synthesis GAs executing in parallel. Also a part of the optimization engineis a two-level profile based characterization scheme [11] that captures the relationships betweensystem performances, component performances and component design parameters. Without thischaracterization information, the optimization phase would be oblivious to the link between thesystem performance and the actual component design parameters.Consider the example shown in Fig. 3. It consists of a set of cascaded op amps and non-

inverting amps connected in a join configuration with a comparator. The performance of this net-list is evaluated by the system level constraint transformation method. The component levelcharacterization tables are generated a priori for each component assuming different load valuesat its output. Such a table for an op amp is shown in the figure. The system level tables aregenerated dynamically. For example, the system level table of opamp1 gives information abouthow the performance parameters of opamp 1 affect the system performance. This information isused to change the component performance parameters, so that constraint satisfying solutions arereached. The performance allocation GA computes values for opamp1’area, opamp1’ugf,..-ninv1’bw, .. adc1’area (component performance parameters) that satisfy the system levelconstraints (System’area, System’power, and so on). Next, the design parameter ranges for thecomponents (Ibias, Zout, etc.) are computed by the component synthesis GAs executing inparallel.In this context, we describe a two-level hierarchical constraint model solving method. The

integrated problem of translating the system level constraints into component design parametersis split into two levels. The first level computes component performances that satisfy system levelconstraints, thereby partitioning the integrated problem into a set of sub-problems that could besolved individually. At the second level, the problem of computing component design parametersthat satisfy component performance constraints is solved for each of the sub-problems. Fig. 4shows the organization of the two-level optimization engine. In the rest of this section we describethe constituents of this optimization engine.

3.1. Profile based characterization

The characterization information is organized in two levels. The system level characterizationtable generator computes the sensitivities of component level performances to systemperformance. This task is done dynamically because the relationship between the component’sperformance parameters and system performance is dependent on its interaction with the othercomponents in the system net-list. The component level characterization table containsinformation about the sensitivity of component design parameters to component performances.This table is generated once for each component. This kind of a hierarchical organization of thecharacterization information helps in providing a link between the system performance andcomponent design parameters.

NCORRECTED PROOF

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Non Inv amp 1

Non Inv amp 2

Non Inv amp 3

comparator

[cp1,cp2][sp1,sp2]

[cp1,cp2][sp1,sp2]

[cp1,cp2][sp1,sp2]

[cp1,cp2][sp1,sp2]

[cp1,cp2][sp1,sp2]

opamp′power

opamp′UGF

opamp′gain

opamp′slewrate

sys′Power

SYSTEM AREA

SYSTEM POWER

SYSTEM BANDWIDTH

SYSTEM GAIN

SYSTEM SLEWRATE

[d1,d2][p1,p2]

[d1,d2][p1,p2]

[d1,d2][p1,p2]

[d1,d2][p1,p2]

[d1,d2][p1,p2]

[d1,d2][p1,p2]

[d1,d2][p1,p2]

[d1,d2][p1,p2]

[d1,d2][p1,p2]

[d1,d2][p1,p2]

[d1,d2][p1,p2]

opamp′Ibias

opamp′Adm

opamp′gainw_l

opamp′zout

Power

..........IGA 1 IGA n

comp synth comp synth

GA

Perf Allocation

Module PerformanceParameters

Module DesignParameters

System Net-List

Compound Block 1

Compound Block 2 Compound Block 3

Op amp1

System-Level Characterization Table

Component-Level Characterization Table

Op amp 2 Op amp 3

sys′BW sys′Gain sys′SR

UGF slewrate o/p impedance

Fig. 3. Hierarchical constraint transformation example.


U3.1.1. Profile based component level characterizationIn order to select components from a library the synthesis algorithms need to have information

about the performance of these components. For a digital component library such characteriza-tion of performance is not a very complex task because of the number of parameters involved. Thecharacterization information for each component may be stored as a table of area and delay

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Optimization Engine

Component Level

CharacterizationTable

Generator

System Level

Characterization

ModuleSearch

Engine

. . . . . . . . . .comp #1 comp #n

GA

IGA 1Comp Syn Comp Syn

IGA n

Perf Alloc

TableGenerator

Characterization

Fig. 4. Optimization engine.


UNCORRECTED PROvalues indexed on the bit-width of the component [22]. On the contrary, the task of characterizing

an analog component library is complex because of the number of parameters involved and theinteractions between the various design and performance parameters. In the worst case, thecharacterization information for an analog component could be viewed as a large table of valuesfor the design and performance parameters. Such a representation would be hard to generate andcannot be readily used in a meaningful way by an automatic synthesis tool. Thus, from a synthesispoint of view, we need a characterization mechanism that may generate information, which couldbe used effectively by the algorithms in an analog synthesis system. Eckmuller et al. [23] present ahierarchical characterization technique based on numerical simulations for CMOS analog circuitsthat detects and locates bad circuit sizing. This characterization mechanism presented is gearedmore towards assisting the manual design of analog circuits, rather than automatic CAD tools.The characterization method presented here attempts to capture the way in which the

performance parameters of the component change with its design parameters. This is the directionpart of the characterization information, where the direction in which the performanceparameters change with an increase in each of the design parameters, is computed. It is notenough if the direction alone is captured because the direction for each of the performanceparameter need not be monotonic for the entire range of design parameter values. Thus, wecapture the range of design parameter values in which the performance parameter monotonicallyincreases or decreases. That is, in a way we are trying to capture the magnitude and direction inwhich each design parameter affects the performance parameters. Next, we presented thecharacterization table generator.

The characterization table generator. The characterization table generator accepts a set ofstarting interval values for the design parameters of the component being characterized, andgenerates a characterization table of directed intervals. Fig. 5 shows the algorithm for thecharacterization table generator. Initially, the starting values for the design parameters are validdesign points, which would be expanded by the characterization table generator. Depending onthe designer’s choice, performance estimation is based either on the analog componentperformance estimator APE [9] or on a numerical simulator, such as SPICE. For example, tocharacterize the performance of a 3-stage operational amplifier, APE expects as input, the

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Fig. 5. Overall characterization table generation.


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topology for the input stage, gain stage and the output stage, and values for the designparameters, like bias current, output impedance, and differential mode gain. The performanceparameters returned by the estimator comprise of area, power, slew rate, UGF, CMRR, and gain.The characterization information is in the form of a table whose rows are indexed by the design

parameters and whose columns are the performance parameters. The direction in which theperformance parameter (column) changes with increase in the design parameter (row) value isstored in every cell. The direction may be (increase), ! (decrease), or a – (constant). Alsostored is the interval value for the performance parameter and an interval value for the designparameter. If the direction at say, row a and col b is �1, the performance parameter interval value½p; q� and design parameter interval value is ½x; y�. This means that the performance parametervalue decreases in the interval ½p; q� with the design parameter values increasing in the interval½x; y�.The algorithm accepts a set of initial intervals for the design parameters as input and generates

a characterization table, which is of the form described above. Component characterizations arebuilt for different samplings of the output load for a circuit. In the first step, the routineExpandInitialIntervals accepts the initial design parameter intervals as an input and tries toincrease the width of these intervals as much as possible. The method checks for the transistors inthe design going into saturation, or for the violation of some basic conditions governing thefunctionality of the circuit. The routine ExpandInitialIntervals increases the width of the designparameter intervals within these conditions imposed by the estimator. The for loop in thecharacterization table generation algorithm, builds the table row by row. Each iteration of thisloop tries to capture the effect of a single design parameter on the performance parameters. Forthis, all the other design parameters except the current design parameter are set to their minimumvalues and the characterization table row generation procedure is invoked with the current designparameter as the argument.The algorithm for the row generation procedure is shown in Fig. 6. In the procedure

GenCharacTableRow, the design parameter’s value is varied from its minimum value to themaximum value. APE or SPICE are invoked with these design parameters as the arguments. The

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Fig. 6. Characterization table row generation.


UNCORRECTEperformance parameter values returned are checked for monotonicity. As long as the performanceparameter values remain monotonic, the design and performance parameter intervals keepwidening. Once there is a discontinuity in the values of the performance parameters, the interval isclosed and an entry is made in the characterization table. The direction part of the performanceparameter’s interval is set depending on whether the performance parameter value was increasingor decreasing with the increasing design parameter values. This is shown in the else part of the ifstatement that checks for the monotonicity of the performance parameter values.Finally, the row generation procedure computes the directed intervals corresponding to the

current design parameter and all the performance parameters. An entry in the characterizationtable may have many interval values, depending on the direction in which the performanceparameter values vary with changing design parameter values. The next step in thecharacterization table generation procedure is to set all the other design parameter values totheir maximum values and repeat the same process. This generates another characterization table(CTABLE2). This process may be repeated by keeping all the other design parameter values atsome intermediate values between minimum and maximum. The more the number of theseintermediate points the better would be the accuracy of the characterization. This is because doingthis would take into account the relationship between the current design parameter and theperformance parameters at various other points in the parameter space. This process wouldgenerate as many CTABLEs as the number of intermediate points. Finally, all these tables aremerged together to form the characterization table for the component. Merging involvesperforming a union of cells in each of the tables. If the directions in both the cells are the same

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then a union of the corresponding component performance intervals is done. If the directionshappen to be different the cell in the merged table would have a set of directed intervals. Each setcorresponds to a unique direction value. In this case each cell in the merged characterization tablecaptures the relationship between the component design parameters and component performancein different disjoint regions of the component performance space.

3.1.2. System level characterizationThe system level table for each component is generated dynamically. The rows of this table

represent component performances and columns represent system performance. Each entryconsists of a system performance interval, component performance interval and a directionattribute that gives the way in which the system performance changes with the componentperformance increasing in its range. The characterization method can be seen as one of samplingthe search space (component performance space) at different points to generate information aboutthe space that could be used by the search engine. The number of points being sampled dependson the width of the component performance intervals. The characterization method takes only asmall amount of time and does not involve moving through the entire search space.System level tables have to be generated dynamically because the relationship between the

component’s performance parameters and system performance is dependent on its interactionwith the other components in the system net-list. The component performance is varied byinstantiating a particular topology for it. The component performance is varied by changing itsdesign parameter values, and the effect of this component performance change on the systemperformance is captured in the characterization table. This is based on the fact that changing thetopology of a particular component in the system net-list would not affect the relationshipsbetween the component performances and system performance. The characterization tables forcircuits act as macromodels that describe the circuits. Then the tables are used to built the systemlevel characterization. In the process, the circuit tables for the particular circuit output loading(decided by the system structure) are used. The procedure for generating the system levelcharacterization tables is similar to component level characterization table generation methoddescribed earlier.The component and system level characterization tables presented here are used to define moves

or operators that guide the genetic algorithm based search engine. The description of thishierarchical search engine forms the rest of the section.

3.2. Hierarchical search engine

The search engine is based on genetic algorithms (GA) [13]. GAS are stochastic searchtechniques based on the mechanism of natural selection and genetics [24]. GAs start with an initialset of random solutions called the population. Each individual in the population is called achromosome, representing a candidate solution to the problem being solved. The chromosomesevolve through successive iterations, called generations, through a process of competition andcontrolled variation. Each chromosome in the population is evaluated using some measure offitness, to determine which of them are used to form new ones in the competition process. Thisprocess is called selection. New chromosomes, are created by either (a) merging two chromosomesfrom current generation using a crossover operator or (b) modifying a chromosome using the

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mutation operator. The reason for the success of the GAS is their ability to exploit the informationabout an initially unknown search space in order to bias subsequent searches into usefulsubspaces [25]. This adaptation feature of the GA is the key to its success, particularly in large,complex and poorly understood search spaces, where classical search techniques areinappropriate. Thus, the GA is well suited to perform the task of constraint transformationwhich may be seen as the task of searching the parameter space of the components in the systemfor a solution that falls within the constraint satisfying region of the system’s performance space.The algorithm in Fig. 7 shows the flow of the search engine. The search engine is organized in

two levels. At the highest level is the performance allocation GA (PerfAllocGA), that accepts thesystem net-list (SysNet), system constraints (SysCon), and the system characterization table(SysTable) and computes component performance values ðCPERFÞ that satisfy the systemconstraints. Next, the for loop executes the component synthesis GA (CompSynGA) in parallel foreach of the components in the system net-list. The component synthesis GA computes componentdesign parameter ranges that satisfy the performance constraints generated by the performanceallocation GA.
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RECTED PR

3.2.1. Performance allocation IGA

The first step in the GA is to suitably encode the solution representation. After initialization,the steps of selection, crossover, mutation and replacement are repeated till convergence isreached. The selection step picks the two best solutions from this set. This step makes use of a costfunction to evaluate the solution quality. The crossover and mutation operators perturb theselected solutions to create new ones. Finally, the newly generated solutions are merged into theset of solutions, by replacing the two worst solutions with these new ones. This is done by thereplacement method. Once the convergence condition has been reached the solution with the bestcost function value represents a solution to constraint transformation problem. Typicalconvergence conditions would include number of iterations, or the cost function value for thebest solution remaining the same over a number of iterations. The solution in the performanceallocation GA is represented as a set of interval values. Each interval represents the componentperformance parameter values. The GA assigns values to these component performance valuesthat satisfy the user imposed system level constraints.

UNCOR

Fig. 7. Search engine.

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UNCORRECTED PROOF

Cost function evaluation: The cost function evaluation technique is used to evaluate the solutionquality. The result of this is used by the GA in the selection process. Each solution represents a setof points, forming a region in the system performance space. If all the points in the solution areconstraint satisfying, then the entire solution is a constraint satisfying one having a cost functionvalue of zero. The evaluation of the solution quality is done using a two-level cost function.

The cost function: The IGA uses a two-level cost function which consists of a local part and aglobal one, which are shown below.

Local cost function

1

N�XN

i¼1

W i:Fi,

where N represents the number of specifications, W i is the weight associated with that systemperformance specification and Fi is defined as

Fi ¼

0 if Pi_est satisfies Pi_constraint

Pi_est�Pi_constraint

Pi_constraint

�� otherwise

8<:

Pi_est is the value for the system performance parameter in the current solution, and Pi_constraint isthe user specified constraint. Such a cost function is typical of GAS that handle multipleconstraints. This cost function gives the average factor by which each performance parametersdeviates from the constraints. The GA works towards minimizing the cost function.

Global cost function which is defined as follows:

1

N�XN

i¼1

local_obj_fnðiÞ,

where N denotes the number of points in the region. This global cost function returns a value ofzero only if all points in the region represented by the solution are constraint satisfying.

Directed interval based operators: During the early part of a search, we would like to have manyindividuals explore different parts of the search space. But once a promising region has beendiscovered, we would like to focus the remaining search in that area. The directed interval basedoperators defined here to some extent act as local optimization methods and help in focusing thesearch process. Therefore, in our GA we start out with the traditional operators of non-uniformmutation and uniform crossover [24] and after some evolution we switch to the directed intervalbased operators.

Mutation: Fig. 8 shows the directed interval based mutation operator. Initially, the solution tobe mutated is evaluated using the driver program for the current system net-list. The resultingperformance parameters are compared with the user defined constraints to identify thoseperformance constraints that are being violated in the current solution. These are shown in thefigure as the shaded parts in the performance parameter array. Here, the constraints P3 and P4 arebeing violated. Now the characterization table information is used to select which componentperformance parameters are to be changed and in what direction. The system-level characteriza-tion tables for all the components are seen globally to find all the component performanceparameters that need to be changed to improve the system performance parameter that is being

CORRECTED PROOF

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Fig. 8. Dir interval based mutation.


UNviolated in the current solution. We see that parameters D1 and D2 are the ones to be changed inthe new solution. The mutated solution has the values D1 and D2 replaced by nD1 and nD2. Thussuch a mutation operator attempts to intelligently guide the evolution of the GA towardsconstraint satisfying areas in the search space through the use of characterization information.

Crossover: Fig. 9 shows the directed interval based crossover operator. Similar to the mutationoperator, the two parents are individually evaluated using the driver program, and the constraintsthat are violated are identified on comparison with the user defined constraints. In the figure, inparent 1 the only constraints that are being satisfied are P1 and P5. Similarly in parent 2,

ED PROOF

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Fig. 9. Dir interval based crossover.


UNCORRECTconstraints P3 and P4 are the only constraints being satisfied. The characterization table is lookedup and the component performance parameters that correspond to the satisfied performanceconstraints are combined together to form one child. The remaining parameters are combinedtogether to form the second child. Therefore, child 1 is formed by combining the designparameters d1, d2 from parent 2 and D3 and D4 from parent 1. Child 2 is formed by combiningthe remaining design parameters.Directed interval based operators identify promising space regions guided only by the small-

signal performance attributes embedded in the system and component level characterizationtables. However, once the GA switches to the regular operators, a more general cost functionexpressing also large-signal performance attributes (obtained through SPICE simulation) is usedfor guiding the search. Hence, directed interval based GA performs a coarse search followed by afine search using GA.

Component synthesis IGA: Fig. 10 shows the solution representation for the interval geneticalgorithm (IGA). This has two parts, the first representing the component design parametervalues, and the second topology information. Each value in the topology part of therepresentation indicates the type of topology to be selected from library. Each component mayhave more than one entry in the topology part of the array if that component has sub-componentshaving different topologies. The representation is a two dimensional array of real numbers. Thefirst row represents the center of the interval, and the second row is a delta value, which lies

OF

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Solution Representation:

∆A.2 ∆A.3 ∆B.1 ∆B.2 ∆C.1 ∆C.2 ∆D.1 ∆D.2∆A.1Delta

(0 - 1)

Center

Upper Bound of the Interval - [Center + Delta * Center]

Lower Bound of the Interval - [Center - Delta * Center]

Topology InformationDesign Parameters

A.1 A.2 A.3 B.1 B.2 C.1 C.2 D.1 D.2 A.t1 A.t2 B.t1 B.t2 C.t1 D.t1

− − − − − −

Fig. 10. Solution representation for IGA.


RRECTED PRObetween 0 and 1. The upper and lower bound of the interval are calculated as shown in Fig. 10.

These are calculated for every design parameter in the solution. A set of point values for thedesign parameters constitute a point in the region defined by the design parameter intervals. Thus,moving from one point to an other in this region of points requires us to define a step size, withwhich the design parameters would be incremented from their lower bound to the upper bound.These step sizes are calculated for each design parameter in the solution based on the width of theinterval. The smaller the step size, more would be the number of points in the region representedby the design parameter intervals. The step size in the IGA is set to about 5% of the width of theinterval.

Cost function: The cost function is similar to the one used in the performance allocation IGA,but for component performance parameters being used instead of system performanceparameters.

Genetic operators: A mix of the traditional non-uniform mutation and uniform crossoveroperators were used in conjunction with directed interval based operators. The directed intervalbased operators for the component synthesis GA are similar to the ones defined for theperformance allocation GA. The only difference being the usage of the component characteriza-tion tables instead of the system characterization tables.
O
UNC4. Experimentation

We present two kinds of experimentation. In the first we use the covering based modelgeneration [12] in conjunction with an interval genetic algorithm that was described in theprevious section forming the core of the hierarchical search engine. In this we compare theperformance of the hierarchical approach to a flat one and establish its effectiveness. In the samecontext we also demonstrate the impact of using profile based characterization in the constrainttransformation process. In the second we use the SPICE based system level model generation andshow the results of constraint transformation emphasizing on the quality of the constrainttransformation process.

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ECTED PROOF

The constraint transformation algorithm was implemented using a publicly available GApackage, GAlib [27]. All the experiments used mutation and crossover rates of 0.1 and 0.9 with apopulation size of 1000. UltraSparc 2s and 30s running Solaris were used to run the examples, andthe time was measured using the system time command.Following examples were used in the first experiment. The first example (cascaded amplifiers) is

a system of four cascaded amplifiers. The second example (Acquisition System) is an acquisitionsystem front-end that consists of a series of seven amplifiers connected to an analog-digitalconverter. The next example (Neural Control-1) comprises of two banks of amplifiers connectedin a join configuration with a comparator. The fourth example (Neural Control-2) is a system ofsix blocks, which consists of an amplifier driving two banks of cascaded amplifier pairs which areconnected in a join configuration with a comparator. These examples are typical of controlcircuits used for the activation of neurons in artificial neural networks [26]. The system in the finalexample (Neural Trainer) consists of ten blocks. Inputs from two sensors are amplified bycascaded amplifiers and are compared. The output of the comparator drives two cascaded pairs ofamplifiers whose outputs are summed using a summing amplifier. This kind of a system is used toimplement weighing functions that are used in the training of artificial neural networks.We compare the flat approach to constraint transformation with the hierarchical one presented

here. Table 1 shows two of the constraint sets that were used. Table 2 compares the hierarchicalapproach with the flat one for four constraint sets. Each entry for the flat approach has theobjective score and the time taken. Each entry for the hierarchical approach has the objectivescore, time taken when the component synthesis IGAS are run in parallel (total time ¼ perf allocGA time + max(comp syn IGA times)), and the last row shows the time taken when the IGAS arerun serially. The objective score value shown for the hierarchical approach is the sum of theobjective scores of the component synthesis IGAs, and the performance allocation GA. The finalcolumns show the average savings in time and the average improvement in the objective functionvalue obtained using the hierarchical approach. The results in the table clearly show that thehierarchical approach performs better than the flat one in terms of both the search quality and thetime taken. For the cascaded amplifier example and the constraint set 1 (row 1 in Table 2), the

UNCORRTable 1

Example circuits and constraint sets

ckt name Constraint set 1 Constraint set 2

Cascaded Area ¼ 1200 sqm, power ¼ 40mW, gain ¼ 2e4 Area ¼ 800 sqm, power ¼ 40mW, gain ¼ 1e4

amplifiers bw ¼ 30 kHz, sr ¼ 100 000 bw ¼ 100 kHz, sr ¼ 70 000

Acquisition Area ¼ 1800 sqm, power ¼ 80mW, gain ¼ 10e3 Area ¼ 1800 sqm, power ¼ 90mW, gain ¼ 1e3

System bw ¼ 100 kHz, sr ¼ 70 000 bw ¼ 800 kHz, sr ¼ 80 000

Neural Area ¼ 900 sqm, power ¼ 90mW, gain ¼ 1e3 Area ¼ 1200 sqm, power ¼ 90mW, gain ¼ 2e3

Control-1 bw ¼ 100 kHz, sr ¼ 80 000 bw ¼ 90 kHz, sr ¼ 80 000

Neural Area ¼ 1500 sqm, power ¼ 80mW, gain ¼ 2e3 Area ¼ 1200 sqm, power ¼ 80mW, gain ¼ 2e3

Control-2 bw ¼ 300 kHz, sr ¼ 70 000 bw ¼ 90 kHz, sr ¼ 80 000

Neural Area ¼ 9000 sqm, power ¼ 90mW, gain ¼ 1000 Area ¼ 1800 sqm, power ¼ 12mW, gain ¼ 500

Trainer bw ¼ 20 kHz, sr ¼ 70 000 bw ¼ 200 kHz, sr ¼ 70 000

UNCORRECTED PROOF

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Table 2

Flat vs. hierarchical approaches

Circuit Flat Hierarchical Flat Hierarchical Savings

time (ser) (%)

Savings

time (par) (%)

Avg imp

obj func

set 1 set 2 set 1 set 2 set 3 set 4 set 3 set 4

Cascaded 0 0 0.1 0 0.2 0.1 0 0

amplifiers 5083 s 6219 s 2180 s 2386 s 5567 s 6434 s 2273 s 2178 s 5.5 61.5 0.2

[6013 s] [6114 s] [5464 s] [5633 s]

Acquisition 0.34 0.24 0 0 0.2 0.41 0 0.4

System 21 414 s 19 033 s 2344 s 2831 s 20 414 s 16 370 s 2740 s 2463 s 31.9 86.5 0.26

[14 620 s] [13 990 s] [11 332 s] [12 311 s]

Neural 0 0.08 0 0 0.3 0.2 0.2 0.17

Control-1 26 283 s 24 443 2678 s 2525 s 23 528 s 19 847 s 2684 s 2933 s 40.4 88.3 0.06

[13 844 s] [13 963 s] [13 587 s] [14 088 s]

Neural 1.6 1.3 0 0 0.52 0.51 0 0.2

Control-2 16 869 s 14 738 s 2854 s 3427 s 18 180 s 14 849 s 2781 ss 2665 s 36.5 81.7 1.24

[10 632 s] [10 344 s] [10 063 s] [9690 s]

Neural 0.65 0.59 0 0 0.4 0.37 0 0.09

Trainer 20 860 s 19 400 s 2980 s 3112 s 24 695 s 16 025 s 2750 2960 28.7 85.08 0.41

[14 160 s] [13 980 s] [14 268 s] [14 033 s]

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ORRECTED PROOF

hierarchical GA serially running the component IGAS showed only minor time savings over theflat GA. From experiments we observed that for systems having six or more blocks thehierarchical GA offers important execution time savings compared to the flat GA. The time takenfor system level table generation is very small (less than 1.5–2min) and is included in thehierarchical method’s time.The hierarchical approach uses both the system level and the component level characterization

tables. The ratio between the number of generations the traditional operators was used and thenumber of generations for which the directed interval based operators were used was 40–60. Theimprovement obtained using the hierarchical approach is clear from the table. Next, we observedthe impact of using the characterization tables in the constraint transformation process. For thiswe compared the hierarchical approach using only the traditional non-uniform mutation anduniform crossover operators [25], to one that uses the traditional operators in conjunction withthe directed interval based operators. The results shown in Table 3 clearly indicate the importanceof the characterization tables in the constraint transformation process. Table 4 shows the designparameter ranges generated by the constraint transformation process for two of the componentsin the cascaded amplifier example. The first row shows the constraints generated by theperformance allocation GA, the second row shows the design parameter ranges generated by thecomponent synthesis GAS, and the final row is the performance after component synthesis. Thesizing solutions corresponding to the found design parameter ranges can be used to prune thesearch space of an underlying circuit synthesis tool [28].The second experiment considered two examples (Electro Cardio Graph and Neural Control

systems) that were synthesized using the constraint transformation technique presented in thispaper. In this the component performances that form the first level in the two-level hierarchy areoperational amplifier performances of the components in the net-list. In this case the externalresistor and capacitor values are fixed (either by the user or the top-level architecture generator inthe synthesis environment). The aim of the constraint transformation step is to transform thesystem level constraints on area, power, gain and bandwidth onto opamp level design parameters.Table 5 shows the results of constraint transformation using modes 1 and 2 for the two systems.Spice3f5 was the simulator used to measure the performance of the circuits. A wrapper waswritten in Perl to facilitate the interaction between the GA based optimizer and the SPICEsimulator. All experiments were run on an UltraSPARC 2 running at 296MHz, and the time wasmeasured using the system time command. The GA was run with the following parameters:number of generations—1500, population size—250, probability of mutation—0.25, probabilityof cross over—0.85.
C
UN5. Conclusion

A technique for transformation of high-level performance constraints onto component designparameters was presented. Such a constraint transformation method is crucial in taking the designautomation of analog systems to higher levels of abstraction. A hierarchical two-leveldecomposition based approach to constraint transformation was presented. The mainconstituents of this include a hierarchically organized search engine and a componentcharacterization method. Experimental results comparing the hierarchical approach with a flat

UNCORRECTED PROOF

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Table 3

GA without characterization vs. with characterization info

Circuit GA without charac GA with charac GA without charac GA with charac Savings in time Savings in time

set 1 set 2 set 1 set 2 set 3 set 4 set 3 set 4 (ser) (%) (par) (%)

Cascaded 0.3 0.2 0.1 0 0.2 0.8 0 0

amplifiers 4268 s 4441 s 2180 s 2218 s 3218 s 3597 s 2273 s 2178 s 40.6 41.9

[10 806 s] [9154 s] [6013 s] [5991 s] [9430 s] [9654 s] [5464 s] [5633 s]

Acquisition 0.1 0 0 0 0.7 0.8 0 0.4

System 4594 s 5188 s 2344 s 2831 s 6554 s 5277 s 2740 s 2463 s 35.7 51.5

[20 978 s] [21 635 s] [14 620 s] [13 990 s] [19 637 s] [18 841 s] [11 332 s] [12 311 s]

Neural 0 0 0 0 0.27 0.1 0.2 0.17

Control-1 3561 s 3463 s 2548 s 2525 s 4107 s 4111 s 2684 s 2933 s 37.4 29.68

[19 483 s] [19 981 s] [10 844 s] [10 963 s] [19 793 s] [18 113 s] [13 587 s] [14 088 s]

Neural 0 0.1 0 0 0.1 0.2 0 0.2

Control-2 4300 s 2883 s 2854 s 3427 s 3731 s 3648 s 2781 s 2665 s 32.3 24.4

[14 081 s] [14 552 s] [10 632 s] [10 344 s] [16 311 s] [15 449 s] [10 063 s] [9690 s]

Neural 0 0 0 0 0.15 0.2 0 0.09

Trainer 3641 s 3244 s 2980 s 3112 s 3189 s 3263 s 2750 s 2690 s 36 13.4

[20 741 s] [23 695 s] [14 160 s] [13 980 s] [24 729 s] [19 808 s] [14 268 s] [14 033 s]

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ED PROOF

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Table 4

Constraints and design parameter ranges for cascaded amplifier example

Cascaded Amps Component 1 Component 2

Perf alloc GA Area ¼ 200 sqm, power ¼ 8mW, gain ¼ 88 Area ¼ 300 sqm, power ¼ 12mW, gain ¼ 122

constraints bw ¼ 190 kHz, sr ¼ 100 000 bw ¼ 100 kHz, sr ¼ 70 000

Design Ibias ¼ [2.6,2.9]e-07, Adm ¼ [2157,3457] Ibias ¼ [1.3,1.7]e-06, Adm ¼ [10 157,10 415]

Parameter gainw_l ¼ [45,149] gainw_l ¼ [120,166]

Ranges zout ¼ [101,107], DCgain ¼ [80,93] zout ¼ [3,67], DCgain ¼ [119,126]

Perf after Area ¼ [166,190] sqm, power ¼ [3,7]mW,

gain ¼ [90,133]

Area ¼ [158,186] sqm, power ¼ [5,8]mW,

gain ¼ [78,156]

comp syn bw ¼ [640,1180] kHz, sr ¼ [86 033,107 993] bw ¼ [90,312] kHz, sr ¼ [22 245,287 000]

Table 5

Constraint transformation results

Circuit name Time (s) Constraints Resulting performance

Area Power Gain BW Area Power Gain BW

Electro Cardio Graph 773 1e-07 0.006 60 60Hz 1.3e-07 0.005 57 62Hz

Neural Control 813 1e-07 0.009 5 2.5MHz 1.58e-07 0.0058 2.56 4MHz


CTone clearly establish the superiority of the former approach with respect to search time andquality. Also, the impact of using the characterization information within the constrainttransformation process was observed.
E
RR6. Uncited references

[19–21].
O
UNCReferences

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