heterogeneous integration roadmap update- integrated power … · 2018. 10. 15. · embedded...

North Carolina State [email protected]

Heterogeneous Integration RoadmapTechnical Working Group – Integrated Power Electronics

Heterogeneous Integration Roadmap Update-INTEGRATED POWER ELECTRONICS (IPE)

Technical Working Group

The IEEE Societies, and companies are sponsoring a new Roadmap focused on the critical packaging technologies that can maintain the pace of “More’s Law.”

cpmt.ieee.org/technology/heterogeneous-integration-roadmap.html www.semi.org/en/heterogeneous-integration-roadmap

MOVING HETEROGENEOUS POWER INTEGRATION FORWARD

Excerpts from presentation at IEEE Heterogeneous Integration Roadmap Symposium ECTC 2018



2

Co-Chair: Prof Douglas C Hopkins, Ph.D. North Carolina State University

Dr Hopkins is engaged in research involving very high frequency, high density power electronics, organic-based circuits for power and energy systems, and true 3D electronic packaging.

Co-Chair: Prof Patrick McClusky, Ph.D. University of Maryland

Dr McClusky in engaged in research in high temperature and high power electronics packaging, materials, and reliability, and is General Chair of the 2018 3D-Power Electronics Integration and Manufacturing Symposium.

Integrated Power Electronics (IPE)



PERSPECTIVE

Micro-Electronics

Power Electronics

Heterogeneous Power Integration



Profound Philosophical Distinction Processing Information Processing Energy

Tremendous collaboration on the physical requirements to support competition in the

“Ethereal” world

“ETHEREAL” PROCESSING “PHYSICAL” PROCESSINGCompanies compete on the physical “Energies”, i.e. electrical, mechanical,

thermal, chemical; in the forms of reliability, energy efficiency, size, weight, etc.

HOW DO WE INTEGRATE POWER INTO THE NEW WORLD OF “SYSTEM IN PACKAGE” AND “HETEROGENEOUS INTEGRATION”?



Evolution in Microelectronics Packaging

Courtesy of John Hunt ASE Group 19Sep’16



Cell Phones Evolved…….

Consumers wanted smaller devices




Size Cost

Advanced Packaging for Mobility

DriversSmall, Thin for mobile applicationsLow cost for Consumer ProductsGood Electrical performanceLow powerIntegration of Functionality

SolutionsWafer Level Chip Scale PackageFan Out Wafer Level PackageFan Out System in Package (SiP)

Performance




Driver for Wafer Level Packages & Fanout

Source: TechSearch International, Inc., adapted from TPSS.

iPhone 3GS20094 WLPs

iPhone 120072 WLPs

iPhone 4S20117 WLPs

iPhone 5201311+ WLPs

iPhone 5S201322 WLPs

iPhone 6201426+ WLPs

iPhone 6 Plus201426+ WLPs

Shown to scale

6

7

8

9

10

11

12

13

1 /2007 3GS /2009 4S /2011 5 /2012 5S /2013 6 /2014 6+ /2014iPhone Model/year

iPhone Evolution

Thickness

Thick

ness

(mm

)

6

7

8

9

10

11

12

13

0

5

10

15

20

25

30

1 /2007 3GS /2009 4S /2011 5 /2012 5S /2013 6 /2014 6+ /2014

Thic

knes

s (m

m)

WLC

SPs

iPhone Model/year

iPhone Evolution

WLPs Thickness




Revolution in Packaging

£ Mechanical Processesl Grindingl Sawingl Die Bondingl Wire Bondingl Moldingl Singulation

£ + Chemical Processesl Wafer Processingl Sputteringl Platingl Etchingl Photo Processing

uPhotoresistsuPolymers

l Plasma

2000 0

~

Packaging Technologies




State of Art in PowerPlanar 2D power packaging technology

Flex circuit structurePOL package, SKiN package, etc.

Embedded structure AT&S GaNPX, PCB embedded, etc.

Sandwiched structure Planar Bond All package, etc.

SKiN module [5]Power Overlay package [4]

GaNPX package[7] PCB embedded module[6]

Planar Bond All[8] ABB Stacked DBC [1]



State of Art in Power3D power packaging technology

Device level Quilt dies, stacked / vertical dies

Module level 3D CSP, Power chip on chip, 3D power circuit .

Stacked device[13]3D CSP module[12]

3D Power module[10]

Quilt packaging[9]

Inner post

SiC MOSFET& Diodes

Orthogonal DBC Substrate

Excerpt from Dissertation of Dr Haotao Key, 2018



And needs to take more cues from microelectronics

But, Power Needs a Change



Limitation of level-0 packaging

Source: Mark Papermaster, AMD CTO. GSA Europe, April 6, 2017



Limitation… Cost is raising for digital

Source: Mark Papermaster, AMD CTO. GSA Europe, April 6, 2017

“For the past 50 years, the cheapest and easiest way to increase complexity was to shrink the feature size and grow the waferdiameter.(That was he classic Moore’s Law) Now there is a tradeoff. We will do the things that are most economic for the capabilities we want. Some of those will keep us going with smaller and smaller feature sizes almost forever. But the most economical tradeoff is likely to be a combination of better system engineering, multi-chip packaging, and a whole variety of other techniques to keep advancing the capabilities in the most cost-effective way.” Wally Rhines, Chairman Mentor Graphics.Source: Semiconductor Engineering, Ed Sperling, April 20 2017



DEFINITIONHeterogeneous Integration

SiP through Heterogeneous Integration

The integration of separately manufactured components into a higher level assembly (SiP) that in the aggregate provides

enhanced functionality and improved operating characteristics.



SYSTEM in PACKAGE (SiP) through HI



SiP through Heterogeneous Integration

HIP is defined as the integration of separately manufactured power electronic components and subsystems into higher-level assemblies (SiP, PCB/Substrate-embedded systems) that in the aggregate provide enhanced functionality and improved operating characteristics.

Heterogeneous Integration of Power (HIP)

PMU

Power passivesHigh current InductorsLow profile passivesPower distribution planesAdvanced materialsHeat spreaders, heat sinksActive cooling systemsPower semiconductorsEMI shieldingUnique design architectures

DEFINITION



How Do We Integrate Heterogeneous Power ?Power

Conv

Power

Conv

Power

Conv

0

Not the HIR-IPE focus, but will benefit from our

technologies

Discrete Power is being mapped

through the PSMA in their “Embedded

Component Study.”

Power

Conv

1Power Distribution

uses SiP Pkg & Mfgtechnologies

to distribute power from Discrete Power

converters

Pow

er C

onv

Pow

er C

onv

Power Conv

Power Conv

2On-Chip Peripheral Power Distribution

uses “Component” Pkg& Mfg technologies

to create power conversion at the

interface with the SiP

3On-Chip Distributed Power Conversion

uses “Component” Pkg & Mfg technologies

to create distributed power conversion within

the Component



Integrated PowerSiP Substrate

Heat sink

SUBSTRATE

INDUCTOR

RE-DISTRIBUTION LAYER

1mm

HIP SiP

Discrete Power

HIP PSiP

Complimentary Technologies

TechnologyEXCHANGE

Integration challenge will be in “planarization” of power



Heterogeneous Power Integration (HPI) has begun

What has “Power” been looking at?



The PSMA 2015 Tech Report (334 pp)

PSMA 3D Power Packaging Phase IIA Special Project of the

PSMA Packaging Committee

TECHNOLOGY REPORT

Current Developments in 3D PackagingWith Focus on Embedded Substrate Technologies

March 2015

1. Embedding in PCBs & Inorganic Substrates

2. High Temp Die-Attach & High-Lead Solder

3. Thermal Management4. Packaging Technologies5. Interposers6. Embedded Resistors7. Embedded Capacitors8. Embedded Magnetics9. Additive Manufacturing &

Laser Fabricationwww.psma.org



The PSMA 2018 Tech ReportEXCERPT3D Power Packaging with Focus on Embedded Components• 3D Power Packaging Technologies• Drivers and Trends• 3D Power Package Technologies with Focuses

on Embedded Components• Low Power Packaging Technologies and

Roadmap (0.1W-100 W)• Medium Power Packaging Technologies and

Roadmap (100W-1kW)• High Power Packaging Technologies and

Roadmap (1kW- 100 kW)Advanced Substrate Materials and ReliabilityEmerging Lead-Free High Temperature Die Attach Technologies



“Stacked Components”

3D Stacked Die Packaging (Amkor)

Courtesy of: www.psma.com, [email protected]

TI's NexFET™ PowerStack

Innovations in “brick-type” power converters

Stacking Quarter Bricks



Embedding Process, e.g. Shinko Electric




“Embedded (Active) Components

• Other embedding technologies in the industry– Nanium's embedded wafer level package (eWLP)– Integrated Module Board (IMB) from Imbera– Amkor's Embedded Die/Passives in Substrate– SiPLIT from Siemens– DrBlade from Infineon– i2 Board®, p2 Pack® from Schweizer

Example of HERMES face-down technology with two embedded core FR-4 PCBs, Prepreg layers, and external components

Concept view of Crane Aerospace & Electronics embedded components in fusion bonded Multi-Mix® assembly

Heatsink

DBC

MMX


ROHM/TDK module using the "SEmiconductor embedded in SUBstrate” (SESUB) process



X’ X

Processor Die

Packagesubstrate Inductors Core layer

Inductors in the package board

Die Die top side

Capacitors

Package boardSolder bumps

Inductors are formed in the package substrate

i5-4430 package

Processor Bott. View

Courtesy of LTEC Corporation

PowerDensity

PowerSaving

Efficiency

Fsw up to 130MHz!

Great product, but the inductor is a problem!

26

Haswell processor w/ PCB-embedded inductors



Heterogeneous Integrated Stand-alone Power

heat & currentVinVcc

LFET1

UFET1

Lout1Vout

PWMController

Cbyp

LFET2

UFET2

Lout

Cout

Cboot1

Cboot2PWM2

PWM1

ControlSignals

GaAsDie

Cin

DriverDie

HIPS

CoutCin Lout

GaAs FET Die SiPSilicon Driver Die

Cbypother passivecomponents

GaAsDie

1mm

5mm

5.5mm

DriverDie

GaAsDie

Source Sarda Technologies

27

Courtesy of LTECCorporation



MOVING HETEROGENEOUS POWER INTEGRATION FORWARD

SEEKING YOU HELP



How Do We Integrate Heterogeneous Power ?Power

Conv

Power

Conv

Power

Conv

0

Not the HIR-IPE focus, but will benefit from our

technologies

Discrete Power is being mapped

through the PSMA in their “Embedded

Component Study.”

Power

Conv

1Power Distribution

uses SiP Pkg & Mfgtechnologies

to distribute power from Discrete Power

converters

Pow

er C

onv

Pow

er C

onv

Power Conv

Power Conv

2On-Chip Peripheral Power Distribution

uses “Component” Pkg& Mfg technologies

to create power conversion at the

interface with the SiP

3On-Chip Distributed Power Conversion

uses “Component” Pkg & Mfg technologies

to create distributed power conversion within

the Component



Objectives of an IPE Working Group

Part I “SiP POWER”• Identify SiP power distribution

requirements to support COMPONETs

• Identify key enabling packaging technologies and challenges

Power

Conv1

• Analyze the impact of current and future market drivers at 5, 10, and 15 years• Identify major challenges and barriers• Assess the status of manufacturing Infrastructure• Set project goals and time horizons

• Identify key enabling technologies and challenges• Efficiency: Reduced dynamic & conduction losses (WBG), fsw• Power density: Conductive, dynamic switching losses, fsw• Thermal management: Integrated/embedded cooling• Power integrity: Proximity, coupling effects, EMI• Materials: Improved thermomechanical properties• Interconnect: Power delivery, decoupling

Pow

er C

onv

Pow

er C

onv

Power Conv

Power Conv

2PART-II “COMPONENT POWER”• Identify interface metrics for SiP

COMPONENTs• Identify key enabling packaging

technologies and challenges common to all COMPONENTs

* We hope each COMPONENT TWG will have a “Power Section” in their “Chapter”

and we will merge it into our ”Chapter” also.



“Component” TWGs are Impacted by HIP?Integrated PhotonicsMEMS & Sensor integrationRF and Analog MixedMat’ls & Emerging Res Mat’lsInterconnectSecurity InitiativeIntegration Processes

WLP (fan in and fan out)HI for Specialized ApplicationsMobileIoT and WearableMedical and HealthAutomotiveHigh Performance Computing & Data Center

Join the HIR – IPE committee



HIR Technical Working Groups & ChairsHeterogeneous Integration Components• Single Chip and Multi Chip Packaging • (including Substrates) William Chen (ASE),

Annette Teng (promex)• Integrated Photonics Amr Helmy (U Toronto) &

WR Bottoms (3MTS)• Integrated Power Electronics Doug Hopkins

(NCSU) & Louis Burgyan (Ltec)• MEMS & Sensor integration Shafi Saiyed (ADI)• RF and Analog Mixed Signal Herbert Bennett

(NIST Ret)Cross Cutting topics• Materials & Emerging Research Materials WR

Bottoms,(3MTS),MJ Yim (INTEL) • Emerging Research Devices A. Chen (SRC/IBM),

Myya Meyyappan (NASA)• Interconnect Subramanian S. Iyer (UCLA)• Test Dave Armstrong (Advantest)• Supply Chain Tom Salmon (SEMI)

A separate Security Initiative has been approved Scott List (SRC)

Integration Processes• SiP Rolf Archenbrenner (Fraunhofer IZM)• 3D +2.5D Ravi.Mahajan (Intel), Raja

Swaminathan (Intel)• WLP (fan in and fan out) Rozalia Bieca (DOW)

John Hunt (ASE)HI for Specialized Applications• Mobile (recruting chair)• IoT and Wearable R Lo (ITRI Taiwan) • Medical and Health Mark Poliks (BU) & Nanct

Stoffel (GE)• Automotive R Tummala (Georgia Tech)• High Performance Computing & Data Center

Kanad Ghose (BU)• Aerospace & Defense Tim Lee (Boeing) & D

Green (DARPA)Design • Co-Design & Simulation – Tools & Practice

Andrew Kahng (USD) / C Bailey (Greewich) & Xuejun Fan (Lamar)



HIR Collaborates With Many Roadmaps TodayHIR is committed to collaboration with other Roadmaps wherever possible



Volunteers needed to provide

HETEROGENEOUS INTEGRATION ROADMAPIntegrate Power Electronics – Technical Working Group

PERSPECTIVE Integrated

Electronics

Power Electronics

Heterogeneous Power Integration

Contact: Prof. Doug Hopkins [email protected]

+1-919-513-5929



HIR- Integrated Power Electronics Committee

NAME EMAIL AFFILIATION

Douglas C Hopkins (Co-Chair) [email protected] NC State University (NCSU.edu)

Patrick McClusky [email protected] University of Maryland

Markondeya “Raj” Pulugurtha [email protected] Georgia Tech

Mark Johnson [email protected] University ofNottingham

Mark Hoffmeyer (interim) [email protected] IBM

Date:18Nov/17



WHERE DO WE START?



DELIVERABLE: Report Outline & ContentScopeExecutive Summary

Difficult ChallengesTop 10 for 5-year horizonTop 5 for 15-year horizonTop 10 for 25-year horizon for research areas

Discussion of Key Technical IssuesBackground & OverviewChallengesRequirements for key attributes over time (refer to tables with explanation in the text)Potential SolutionsTechnology Gaps and Research needsSupply chain needs (Materials, Processes, Equipment)SummaryAcknowledgements, References, Bibliography, Definition of terms and Glossary



Prof. Douglas C Hopkins, Ph.D.North Carolina State University1791 Varsity Drive, Suite 100

Raleigh, NC 27606-7571Tele: 919-513-5929

[email protected]

If you would like to join the HIR-IPE Committee, contact:

heterogeneous integration roadmap update- integrated power … · 2018. 10. 15. · embedded...

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