Introduction

Heterogeneous Architecture for Image Reconstruction in

UWB SIRE Radar System

Investigators: Jeanine Cook, New Mexico State University

Collaborators: Army Research Laboratory

l  Field-deployable, real-time imaging system for UWB synchronous impulse reconstruction (SIRE) radar

l 

l  Explore emerging compute technologies like FPGA for improved performance

l  Real-time imaging for SIRE and other radars

l  Cost effective system for use on military vehicles

l  Use in other fields such as medical, search and rescue, optical and pipeline infrastructure

3.64x Speedup over CPU

5.45x Speedup over CPU-GPU

168x Speedup over CPU-DSP

FPGA vs CPU image(MS Error): 2.17%

Parallel CPU Implementation shows further performance improvement

Approach

1. Radar data in IEEE754 single precision floating point format is read from system hard drive by FPGA logic

2. FPGA processes data using backprojection image reconstruction

3. FPGA logic writes image back to system hard drive and final image is generated and displayed using MATLAB

Current design in simulation

Backprojection Results

l Proposed Implementation of Other Compute Intensive Algorithms

l N-Body Algorithm – Proposed implementation on FPGA using OpenCL compiler for HDL generation

l Other CPU implementations of N-Body using parallel programming utilizing multicores: MPI & OpenMP

Jeanine Cook, New Mexico State University Song Jun Park, Army Research Laboratory

Col. Mark Hickey, Army Research Laboratory

Presented by Soumik Banerjee, New Mexico State University

Technical

Technical

Technical

Technical

Collaborations