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HEMT Technology Impact on. Computers and Communications II

by Masayuki Abe, Fujitsu Laboratories Ultra low-noise HEMTs are already commercially available as discrete components for such analogue applications as the front-ends in satellite receivers. They are also being effectively applied in radio astronomy observation applications to discover new interstellar materials in the universe. In the final part of this review, the current progress of HEMT technology at Fujitsu Labs in Japan. I'm sure readers will be impressed at the amount of progress that has already been made.

B uilding on its well-established MESI-IIT GaAs ASIC technology, (see TFR V5 I1. January 1992) high electron mobility transistor (HEMT) technol-

ogy developed by Fujitsu has opened the door to new possibilities for high performance computer and commu- nication applications [I-2]. To exploit this technological edge, Fujitsu has founded the Yamanishi 100ram wafer GaAs lab, located near Tokyo. see heading photo: the first lab to be designed from the outset to handle 100 mm GaAs wafers for MESFET ICs.

The evolution of high-speed, low-power HEMT devices is the result of continuous technological progress utilizing the superior electronic properties due to the supermobility of GaAs A1GaAs heterojunction structure 13].

While discrete HEMTs have already found commercial and technical success m satellite communications and radio astronomy[4], the real potential of LSI ICs has yet to be unlocked. Already, at the LSI complexity le\el, a 64- kbit static RAM with an address access time ol 1.2 ns [51 and a 45k-gate array with 35 ps logic delay 16] have becn achieved at room temperature. These are both the fastest circuit operations ever reported. Such complexities are a critical threshold to make H E M T technology practical in future high-speed computer systems.

It is the purpose of this concluding part of this article to review the H E M T LSI progress that has already been made at Fujitsu labs. In particular, we shall bc looking at logic and memory devices with particular application to computers.

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Supercomputer a . Bus Driver Logic LSI Circuit A H E M T bus driver logic circuit using HEMTs ~ith (}.5- I-un gate length has been developed for a high-speed parallel processing systeln. -['his circuit synchronizes data signals for data transfer in a system ,aith a high clock rate. Fig 10 is a block diagram of a bus driver logic circuit [17].

The clock pulse is applied to each latch through the clock chopper, and then 4 x 9-bit latched input data are transferred to the output ports, synchronized with lhc clock signal. The input and output buffers were designed to provide signal levels compatible with the ECL interface.

Figure 11 is a microphotograph of the bus driver logic LS1. The chip contains II37 gates, 99 signal pads, and 36 power supply pads, and measures 6.1 x 6.2 mm ~. and contains 3335 HEMTs.

The standard supply voltages are -2 and -3.6 V. I h e delay time was 490 ps at room temperature, and the power dissipation was 4.1 W. The gate delay through the path from clock input to data output was estimated to be 43 p s gate.

The bus-driver LSI was packaged on a metal plate connected to an air-cooled fin of 13 stages, with a 180 lead- fiat package with 0+4-mm pitch and 22 x 22-mm ~ ceramic base. The low thermal resistance of 2 .5C 'W is achieved at an air velocity o t 8 m s .

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F(gure 11." H E M T bus driver logic LSI.

Figure 12 shows the bus-driver LSIs installed on the printed circuit board of the common mapping unit. Eight bus-driver LSIs are installed on the board together with silicon bipolar LSI ICs. The maximum system perfor- mance of 10.92 gigaflops and the parallel effect from 2.1 to 3.8 were achieved, demonstrating stable operations using HEMT bus-driver logic LSIs.

b. Cryo Random N u m b e r Genera tor Chip Set To demonstrate the feasibility of cryogenic HEMT LSI ICs, a 32-bit pseudorandom number generator system that operates at liquid nitrogen temperature has developed [22].

Figure 13 is a block diagram of the 32-bit pseudorandom number generator system. The system consists of 4 system- controller, 8 data-buffer, and 8 pseudorandom-number generator circuits as a chip set.

The largest key component of this system is the random

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number generator LSI, consisting of 4 blocks of 47-stage feedback shift registers and peripheral circuits. Feedback shift registers are configured to generate a maximum- length-sequence codes each clock cycle.

The generator polynomial is X 47 -~- X 42 ~- 1. The ' (247-1)pen°d

derived from this polynomial is very long: clock cycles. This means it would take more than 2.4 days to repeat a period at 1.5 ns cycle time.

Figure 14 is a microphotograph of a HEMT random number generator LSI. The nominal gate length is 0.6 gm.

The interconnecting lines and space are 1.5 gm wide and 2.0 gm apart. The chip contains 3319 DCFL gates with 10 183 HEMTs, and is 8.2 x 8.2 mm 2. Nominal power dissipation is 4.5 W. This chip includes 56 pads for signal I/ O, and 68 pads for power connection. The input and output buffers provide signal levels compatible with ECL interface.

DX-centre free material is a key technology to achieve a stable operation of the circuit. In the AIGaAs/GaAs structures using silicon as the n-type dopant, drain current degradations due to DX centres are caused at low temperature although there is no problem at room temperature operation. Using selenium instead of silicon completely eliminates this degradation [23] and results in

Figure 12." H E M T bus driver logic LSIs installed on the PCB. Figure 14." H E M T random number generator LSI.

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stable circuit operation. The data buffer LSI is a I-kword x 4-bit self-timed

RAM, and used for synchronizing internal and external circuits. The chip contains 4-kbit static RAM with peripheral 514 logic gates and 72 I/O pins. Total device count "is 32090 and chip size is 5.0 x 5.0 mm ~. Nominal power dissipation is 3W.

The system controller LSI controls system clock and generates an address for the buffer. The chip contains 1306 gates and 124 I/O pins. Total device count is 4275, and chip size is 8.2 x 8.2 m 2. Nominal power dissipation is 3.8 W.

At liquid nitrogen temperature, the typical transconduc- tance is 270 mS/mm. Unloaded delay is 17 ps. Function test was achieved with a cryogenic automatic probe test system that can handle up to 120 l/O pins.

From the eye pattern, (of the clock and random number signal of the random number generator LSI) it is apparent that the circuit can operate at up to 1.6GHz. From critical path delay simulation, the shift register without the feedback circuit is estimated to operate at up to 2GHz.

Flip chip bonding is used (see Figure 15) to attach bare chips to a circuit board of 18 layers with zirconia glass ceramic, whose thermal expansion almost coincides with that of the H E M T chip within + / -10% over a wide temperature range. The twenty H E M T chips are mounted on a ceramic board of 10x10 sq cm ceramic board system, as shown in Figure 16, immersed in liquid nitrogen. Heat flux under the boiled condition is 18 W/cm e The supply voltages are 2.0, 1.0, and -1.6 V. This system operates stably at high clock cycle of 1.49 ns at liquid nitrogen temperature.

Future Prospects For future prospects, the required breakthroughs have to be focused on deep-submicron-gate H E M T VLSI technol- ogy, effectively applying the high-speed / low-power performance of HEMTs. For this target, a multilevel high-speed interconnection technology becomes impor- tant. Elect romigrat ion and stress migrat ion relating interconnections between devices are under evaluation. These will not be very different from the conventional Si technology.For cost-effective manufacturing in volume a

Figure 15." Flip-chip bonding.

simple to thbncate MIUCILIFe J'or high y~eld proces,,, '~a.,, developed.

Heterostructure materml technology has already made breakthroughs to catch up with the learning curve of the semiconductor industry. With the 025- b~m dcv~cc technology, a H E M T 64-kbit static RAM with subnano- second access opera| ions and 100k-gate logic VLSI with subhundred picosecond logic delays can be projected at room temperature. This performance will achieve speeds required for future high-speed computer s,~ stems.

t'?!jit.s'u l, ahotat~,rh',~ I.~d. lO-1 Mormora l~- l , l , akami 3 o, 1/,ug~ 243-u1. Japan,

]U/,LI~1X-" I x l i 402 4x 4!/2 ~o72. This review is based on paper given at thc 71h International

Microelectronics Conference 1pp.553-560, June 3-5th t992, Pacifico Yokohama, Japan) and also IPRM-IV. Newport Rhode Island, MA. USA, tpp.2-5. April 1992).

Acknowledgements The author would like to express his appreciation to Dr. H. Ishikawa and Dr. T. Mimura for their encouragement and support, and to his colleagues whose many contribu- tions have made possible the results described here.

References 17. M. Abe and T. Mimura, "Ultrahigh-speed HEMT LSI technology", IEEE J. Solid-State Circuit, vol. 26, pp. 1337-1344, 1991. 18. M. Noda et al., "High-speed and highly uniform submicron gate BPLDDFET for GaAs LSIs", Inst. Phys. Conf. Ser., vol. 106, Ch. 9, pp. 653-658, 1990. 19. M. Suzuki et al., "43 ps/5.2 GHz bipolar macrocell array LSIs", in ISSCC Dig. Tech. Papers, pp. 70-71, 1988.

20. H. Tokuda et al., "A 100k-gate ECL standard-cell LSI with layout system", in ISSCC Dig. Tech Papers, pp.94-95, 1990. 21. T. Awaya et al., "A 5 ns access time 64Kb ECL RAM", in ISSCC Dig., Tech. Papers, pp. 130-131, 1987. 22. Y. Asada et al., "A gigahertz cryogenic HEMT pseudoran- dom number generator chip set", in ISSCC Dig. Tech., pp. 186- 187, 1990. 23. T. Yokoyama et al., "Se-doped AIGaAs/GaAs HEMTs for stable low-temperature operation", IEEE Electron Device Letters, vol. 11, pp. 197-199, 1990.