hdl mannual
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VHDL AND ITS STRUCTURE
AN APPROACH TO FPGA IMPLEMENTATION WITH QUARTUS II SOFTWARE
LIST OF EXPERIMENTS
VHDL Coding (With sit!"#$ %$h!&io'!# D!t! )#o* !nd St'+t'!#D$s+'i,tions- )o'.
Basic gates
1. Half Adder and Half Subtractor
2. Full Adder and Full Subtractor
3. 8:1 Multiplexer
4. 4:1 !ecoder
". Four bit co#parator using single bit co#parator
. 8:3 $riorit% encoder
&. Four bit adders
8. Signed and 'nsigned #ultiplier
(. Master sla)e flip*flop+! t%pe and ,*- t%pe
1/. Four bit 0ipple counter and 'p*don counter
11. 'ni)ersal sift register
12. State #acine #odelling of Meela% #acine and Moore #acine.
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VHDL AND ITS STRUCTURE
INTRODUCTION
VHDL is an acron%# for Ver% ig speed integrated circuit (VHSIC-
Hardare Description Language ic is a progra##ing language tat
describes a logic circuit b% function data flo bea)ior andor structure. 5is
ardare description is used to configure a progra##able logic de)ice
+PLD suc as a field progra##able gate arra% +FPGA it a custo# logic
design. 5e general for#at of a 6H!7 progra# is built around te concept of
%LOC/S ic are te basic building units of a 6H!7 design. itin tese
design bloc9s a logic circuit of function can be easil% described.
A 6H!7 design begins it an ENTIT0bloc9 tat describes te interface for
te design. 5e interface defines te input and output 1ogic signals of te
circuit being designed. 5e ARCHITECTUREbloc9 describes te internal
operation of te design. itin tese bloc9s are nu#erous oter functionalbloc9s used to build te design ele#ents of te logic circuit being created.
After te design is created it can be si#ulated and s%ntesied to cec9 its
logical operation. SIMULATION is a bare bones t%pe of test to see if te
basic logic or9s according to design and concept. S0NTHESIS allos
ti#ing factors and oter influences of actual field progra##able gate arra%
+FPGA de)ices to effect te si#ulation tereb% doing a #ore toroug t%pe
of cec9 before te design is co##itted to te FPGAor si#ilar de)ice.
Man% softare pac9ages used for 6H!7 design also support sce#atic
capture ic ta9es a logic sce#atic or state diagra# and translates it into
6H!7 code. 5is in turn #a9es te design process a lot easier.
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5e different t%pes of data tat can be used it 6H!7 include bits buses
boolean strings real and integer nu#ber t%pes p%sical and user defined
enu#erated t%pes.
D$)ining Sign!#s
5ere are to data t%pes used for defining interfacing and interconnecting
signals * "itsand "it=&$+to's. 5e bit t%pe defines a single binar% bit t%pe of
signal li9e RESETor ENA%LE. ;t is used to define a single control or data
line. For #ultiple bus signals suc as data or address buses an arra% called
a bit?)ector is used. Bit?)ectors reuire a range of bits to be defined and as
te s%ntax: bit?)ector+range5e range for a bit?)ector is defined fro# te
least significant bit +LS% to te #ost significant bit +MS% and can be set to
go fro# one to te oter in ascending or descending order b% using: 7SB to
MSB or MSB do*nto7SB. Here are so#e exa#ples of bit?)ector for#s:
!dd'$ss"s(9 to >-?
d!t!"s(:@ do*nto 9-?
5e first defines an 8*bit address bus fro# addressbus+/ to addressbus+&.
5e second a data bus fro# databus+1" donto databus+/.
5e IEEE STD=LOGIC=::B standard includes additional definitions for
6H!7 data t%pes. For te bit t%pe te ;=== t%pe is STD=LOGICand for a
bit?)ector it is STD=LOGIC=VECTOR. 5e use of te ;=== standard t%pes
assures tat our 6H!7 code ill be ,o't!"#$.
Th$ %oo#$!n T3,$
5e boolean t%pe as onl% to )alues: TRUE (:- and FALSE (9- and is
usuall% used to old te results of a co#parison or te basis for conditional
state#ent results.
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u#ber t%pes tat are usable in 6H!7 code are INTEGERS and REALS.
;ntegers are signed nu#bers and reals are used for floating point )alues. 5e
range of )alues for bot nu#ber t%pes depends on te softare application
being used.
S"t3,ing
6H!7 pro)ides a #etod to create a )ersion of an existing t%pe it a
specified range of )alues b% using te SU%T0PE declaration. A t%pical
exa#ple of te use and s%ntax of tis operation is:
s"t3,$ SHORTINT is int$g$' '!ng$ 9 to 1@@?ic creates an integert%pe SHORTINTit a specified range of )alues fro# / to 2"".
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)alues for a specific application ten te t%pe operator can be used as
follos.
5%pe data?7'5 is arra%+( donto / of std?logic?)ector+& donto />
Signal nedata : data?7'5:D +E1/1/11////11//111111////
E1/1/1/1/11//11//////11//
E1111//11111//1111/11///111111111>
;n te abo)e exa#ple nedata is te 7'5 ic is of t%pe data?7'5
and it as ten 8bit )alues.
Oth$' D!t! T3,$s
6H!7 specifications include additional data t%pes tat are used in te
bea)ioral description of a circuit design. 5ese t%pes are:
A. Arra%s are single or #ultidi#ensional enu#erated arra% t%pes and te
std?logic?)ector t%pe.
B. An access t%pe acts li9e a pointer t%pe and as li#ited use.
G. A file t%pe is used to access a file.
!. A p%sical t%pe is used to specif% finite uantities suc as ti#e
)oltage etc. 5is t%pe includes units of #easure suc as #illiseconds
+#s and )olts.
=. 5i#e units used it te p%sical t%pe are:
pri#ar% unit is fs................fe#tosecond
ps D 1/// fs.................. ..picosecond
ns D 1/// ps................. ..nanosecond
us D 1/// ns................ ...#icrosecond
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#s D 1/// us............... ...#illisecond
sec D 1/// #s............. ...second
#in D / sec................ ....#inute
our D / #in............... ....our
F. 5e line t%pe is an ASG;; string of caracters.
. A record contains a collection of #ultiple data t%pes.
5ese are te )arious data t%pes used b% 6H!7.
2 ENTIT0 %LOC/
An $ntit3 "#o+8 is te basic building bloc9 of a 6H!7 design. =ac design
as onl% one entit% bloc9 ic describes te interface signals in to and out
of te design unit. 5e s%ntax for an entit% declaration is:
$ntit3 $ntit3=n!
;n general tere are fi)e t%pes of #odes.
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1. In* co#ponent onl% read te signal
2. Ot*Go#ponent rite to te signal
3. Inot*co#ponent read or rite to te signal +Bidirectional signal
4. %))$'*Go#ponent rite and read bac9 te signal
". Lin8!g$*used onl% in te docu#entation purposes.
5e port diagra#s for )arious #odes are son in te fig.
In VHDL ALL STATEMENTS !'$ t$'
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A #it$'!# +onst!nt can be defined itin an entit% it te g$n$'i+
declaration ic is placed before te port declaration itin te entit% bloc9.
eneric literals can be used in port and oter declarations. 5is #a9es it
easier to #odif% or update designs. For instance if %ou declare a nu#ber of
bit?)ector bus signals eac eigt bits in lengt and at so#e future ti#e %ou
ant to cange te# all to 1*bits %ou ould a)e to cange eac of te
bit?)ector range. B% using a generic to define te range )alue e a)e to
do*n
to 9. en te design is updated to a larger bus sie of sixteen +1 bits teonl% cange is to te literal assign#ent in te generic declaration fro# > to
:@2
B2 ARCHITECTURE %LOC/
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5e !'+hit$+t'$ "#o+8 defines o te entit% operates. 5is #a% be
described in #an% a%s to of ic are #ost pre)alent: STRUCTURAL
and DATA FLOW o' %EHAVIORALfor#ats. 5e %EHAVIORAL approac
describes te actual logic bea)ior of te circuit. 5is is generall% in te for#
of a Boolean expression or process. 5e STRUCTURAL approac defines
o te entit% is structured * at logic de)ices #a9e up te circuit or design.
5e general s%ntax for te arcitecture bloc9 is:
!'+hit$+t'$ !'+h=n!
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n : out std?logic>
end latc>
** arcitecture bloc9
arcitecture flipflop of latc is
begin
** assign#ent state#ents
JD r nor n>
n JD s nor >
end flipflop>
5e first to lines i#ports te ;=== standard logic librar% std=#ogi+=::B
ic contains predefined logic functions and data t%pes suc as std?logic
and std?logic?)ector. 5e use state#ent deter#ines ic portions of a
librar% file to use. ;n tis exa#ple e are selecting all of te ite#s in te 114
librar%. 5e next bloc9 is te entit% bloc9 ic declares te latcIs interface
inputs r and s and /outputs and n. 5is is folloed b% te arcitecture
bloc9 ic begins b% identif%ing itself it te na#e flipflop as a description
of entit% latc.
itin te arcitecture bloc9Is bod% +designated b% te "$gin
reser)ed ord are to assign#ent state#ents. Signal assign#ent
state#ents follo te general s%ntax of:
sign!#=id$nti)i$'=n!
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operation of te C0 latcIs bea)ior is described and translated b% a 6H!7
co#piler into te ardare function appearing in figure 1.
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Again te difference beteen te to ti#e dela%s is tat itout te transport
operator te input as to be present for te entire dela% ti#e ile it te
transport operator te input does not need to be applied for a period eual to
te full dela% ti#e period.
Using V$+to' T3,$s in th$ A'+hit$+t'!# %#o+8
A bit?)ector or std?logic?)ector t%pe is an !''!3 o) "its. 5e range
designates te sie of te arra% and te index )alues to be used b% te arra%.
=le#ents of te arra% are accessed b% using te arra% na#e and an index
)alue in te for# of: !''!3=n!
use ieee.std?logic?114.all>
entit% de#ux is
port + e : in std?logic?)ector +3 donto />
s : in std?logic?)ector +1 donto />
d : out std?logic?)ector +3 donto />
end de#ux>
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arcitecture rtl of de#ux is
signal t : std?logic?)ector +3 donto />
begin
t+3 JD s+1 and s+/>
t+2 JD s+1 and not s+/>
t+1 JD not s+1 and s+/>
t+/ JD not s+1 and not s+/>
d JD e and t>
end rtl>
Before e loo9 at tis exa#ple line b% line e need an introduction to a ne
declaration SIGNAL. 5is declaration is used to define an int$'n!# sign!#for
our design. ;n te entit% bloc9 e defined interfacing or external signals tat
ta9e infor#ation in and return data out. ;nternal signals are tose used to
perfor# so#e internal connections or function beteen logic entities. A signal
declaration as te s%ntax:
sign!# sign!#=id$nti)i$' . t3,$?
;t is si#ilar to a port signal declaration except for te lac9 of a #odeindication.
;n te de#ux exa#ple te entit% as tree arra% declarations to are 4*bits
+$and d and one is 2*bits +s. itin te arcitecture bloc9 a local signal is
declared as a 4*bit arra% +t. 5e )alues for t are assigned in descending
order directed b% te four state co#binations of s(:- and s(9-. otice o
eac ele#ent is accessed using te arra% na#e and an index )alue. t(- is
assigned te results of anding s(:- and s(9-. 5is is a single bit #anipulation
and assign#ent of one bit fro# eac arra% bits t(- s(:- and s(9-. 5e last
line sos o arra% )alues can be assigned for te entire arra% at one ti#e.
5e reuire#ent is tat all arra%s in te assign#ent state#ent a)e te
sa#e sie. ;f tat is te case tan eac ele#ent of eac arra% is acted upon
indi)iduall%. ie:
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d(- $(- !nd t(-etc.
Since )ectors can be assigned using to as ell as donto care #ust be
ta9en in te assign#ent. ;f in te pre)ious exa#ple d as declared as d .
ot std=#ogi+=&$+to'( 9 to -? tan te assign#ent d $ !nd t? ould
assign to d(9- te result of $(-andt(- ic #a% not be at %ou intended.
@2 PROCESS
State#ents itin arcitecture bloc9s to tis point are executed
+on+''$nt#3 * tat is at te sa#e ti#e. Also tere is no a% to s%ncronie
teir execution it cloc9ing or an% oter 9ind of signals. 5o incorporateseuential state#ent execution and so#e #anner of s%ncroniation e
need to use a PROCESSbloc9 ose general s%ntax for# is:
,'o+$ss=n!
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&!'i!"#$=id$nti)i$' . $,'$ssion?
5o e)aluate expressions used in a )ariable declaration or process bloc9 %ou
#ust beco#e fa#iliar it te operators used b% 6H!7. ;n order of teir
precedence te% are:
High$st
+ * parentesis
KK * exponential
abs * absolute unsigned #agnitude nu#bers
not * in)ersion
N$t
K * #ultiplication
* di)ision
#od * #odulo or uotient fro# di)ision
re# * re#ainder result of di)ision
N$t
L * identit%
* * negation
N$t
L * addition
* * subtraction
@ * concatenation
N$t
sll * sift left logical
srl * sift rigt logical
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sla * sift left arit#etic
sra * sift rigt arit#etic
rol * rotate left
ror * rotate rigt
N$t
D * eualit%
D * not eual
J * less tan
* greater tan
JD * less tan or eual
D * greater tan or eual
LOWEST
and * logic and
or * logic or
nand * logic nand
nor * logic nor
xor * logic exclusi)e or
xnor * logic exclusi)e nor
o an exa#ple of a )ariable assign#ent:
+nt . +nt :?
As it an% oter language te expression on te rigt is e)aluated first. ;n
tis case one is added to te )ariable cnt. 5e results are tan stored bac9
into te cnt )ariable indicated on te left side of te assign#ent state#ent.
5is one si#pl% incre#ents cnt b% 1. 5o set tis )ariable state#ent into a
process bloc9 te code ould loo9 li9e:
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+ont . ,'o+$ss(-
&!'i!"#$ +nt . int$g$' . 6:?
"$gin
+nt . +nt :?
$nd ,'o+$ss?
5e first line of te process s%ntax is its declaration and contains an optional
para#eter list 9non as te s$nsiti&it3 #ist. A process executes once at te
beginning of a si#ulation and an% ti#e tat an e)ent occurs on an ite# in te
sensiti)it% list. An EVENT is an% cange of state of a signal. A cange of
state on signal ill cause tis process to execute once.
5e next line is a )ariable declaration tat is si#ilar to a port +signal
declaration. Since it is a )ariable and not a port tere is no #ode selection.
Also )ariables can be assigned an initial )alue using an assign#ent operator
as son in te exa#ple. e ant +ntto start at / but since te process
executes once upon starting si#ulation +itout an e)ent occurring on e
need to initialie+ntto *1. 5e initial execution of te process due to te start
of a si#ulation ill set +ntto / b% incre#enting it once. After tat eac ti#e
an e)ent occurs on +nt ill be incre#ented once tus 9eeping trac9 of
o #an% ti#es canges state. 5e state#ents to be executed b% te
process bod% follo te "$gin reser)ed ord. Finall% te process declaration
is co#pleted using an end process state#ent.
D$+#!'!tionsitin te process bloc9 and preceding te process bod% are
executed onl% once * en si#ulation is initiated. 5ereafter en te
process is run due to an e)ent on one of te signals on te sensiti)it% list
onl% te bod% of te process is executed. 5is pre)ents )ariables fro# being
re*initialied eac ti#e te process is run.
All state#ents in a process execute seuentiall%. Here are a couple of
exa#ples of process state#ents it an anal%sis of eac:
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,'o+$ss ( 0 -
&!'i!"#$ X ; . std=#ogi+?
"$gin
X . 0?
; . not X?
$nd ,'o+$ss?
5is is a fairl% eas% appearing exa#ple but letIs ta9e so#e ti#e exploring
at appens to #a9e sure %ou full% grasp te difference beteen
concurrent and seuential operation.0is included in te sensiti)it% list so it
#ust a)e been declared in te design before te process state#ent.
6ariables Xand ;are declared in te process bloc9 forcing tese )ariables to
be local to te process and not accessible outside of it.
5o follo at appens en te process is executed letIs assu#e so#e
initial )alues for our tree )ariables:
N D 1
O D 1
P D /
;nitial )alues for )ariables can be set in te )ariable declaration state#ents
using te :D assign#ent operator in tis #anner:
&!'i!"#$ X . std=#ogi+ . :?
&!'i!"#$ ; . std=#ogi+ . 9?
Cf course signal0ould a)e to be initialied before te process state#ent
to gi)e it a beginning state. ;n tis case %ou ould probabl% use an
assign#ent state#ent:
0 J:J?
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Since 0 as been defined as an interface signal in an entit% te
assign#ent operator is reuired ere. Assigning a literal logic state 1 or / to
a signal reuires a sing#$ ot$around te 1 or /. 5is causes te softare
to con)ert te ASG;; 1 or / to a logic state and assign it to te signal.
Assigning a string of logic bit literals to a )ector reuires double uotes so
tat te ASG;; string can be con)erted to logic states for eac bit of te
)ector. u#erical literals ill not use te uotes around it.
5e sa#ple states ere not selected as rando#l% as %ou #igt tin9. ; cose
te# to illustrate te point of s$$nti!# operation itin te process. en
0 canges to a / troug so#e outside influence an e)ent occurs and te
process is initiated. ;f te state#ents itin te process ere executed
+on+''$nt#3 te% ould use te initial )alues to produce results for all
outputs. 5e cange in0fro# 1 to / causesXto cange to a / because of
te state#ent X . 0? Because Xad a )alue of 1 initiall% tis )alue is used
for te second state#ent in concurrent execution. 5is forces ;to beco#e 1
fro# te state#ent; . not X2
Hoe)er te state#ents in te process are executed s$$nti!##3 rater
tan concurrentl%. at actuall% occurs in te process is Xbeco#es / en
0 canges to / as it did for a concurrent execution. Hoe)er tis ti#e ;
ould beco#e 1 since te second state#ent in a seuential execution ould
use te ne )alue of X instead ofXIs initial )alue. o to a #ore practical
exa#ple use of a process ic ill also include a #etod to pre)ent
state#ents itin te process bod% fro# executing en si#ulation is first
begun and an e)ent as not %et occurred:
librar% ieee>
use ieee.std?logic?114.all>
entit% !FF is
** Signals are initialied to / b% default.
** 5o #a9e Q a 1 it as to be initialied
port + ! G7- : in std?logic>
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Q : out std?logic>
Q : out std?logic :D I1I>
end !FF>
arcitecture data?flip of !FF is
begin
process + G7-
begin
if +G7- D I1I and G7-Ie)ent ten
Q JD ! after 1/ns>
Q JD not ! after 1/ns>
end if>
end process>
end data?flip>
5e entit% bloc9 is co)ered b% te +o
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5e $#s$ "#o+8 is optional and is used en tere are state#ents to be
executed en te conditional test returns a )!#s$ '$s#t2 5e th$n
state#ents are executed en te condition rings t'$.
5e i)22th$n22$#s$state#ent in te exa#ple as to conditions and bot a)e
to be #et to execute te state#ents itin te ten bloc9. 5e first condition
reuires te state of CL/to be high. 5e and operator in te condition field
forces a second condition to also be true. 5is condition is CL/J$&$nt ic
sa%s tat an event #ust a)e occurred on CL/ to be true. ;f te e)ent
occurred CL/J$&$nt returns t'$. ;f no e)ent occurred it returns a )!#s$
)alue. 5e inclusion of tis condition eli#inates te execution of te
state#ents itin te if bloc9 en si#ulation first begins since te lac9 of a
CL/e)ent causes CL/J$&$nt to be )!#s$. 5e onl% ti#e te if condition ill
be satisfied is en an e)ent on CL/occurred. Additionall% CL/as to be
ig so tis co#bination causes te ten state#ents to be executed onl% on
apositive transition (edge) of te CL/signal.
5e . operator is used to assign initial )alues in a )ariable state#ent.
otice tat for signals sing#$ ot$sare reuired around te initial )alue
+I/I ile none are used for an integer +/. 5is is because signal )alues are
logic states and integer )alues are nu#erical. u#erical )alues do not
reuire uotes.
Also notice te difference en integer )ariables are assigned a )alue fro#
an expression co#pared to a signal assign#ent. ;n a pre)ious exa#ple e
used0 A !nd %?to assign to0te results of Aand %. ;n tis #ost recent
exa#ple e did a arit#etic operation on an integer )alue and assigned te
results to it: +nt . +nt :?
. GC!;5;CA7 S5A5=M=5S
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i)22th$n22$#s$
5e pri#ar% conditional test function is te i)22th$n22$#s$ construct tat or9s
te sa#e as it does in an% progra##ing language. 5e s%ntax for tis
function is:
i) +ondition!#=t$st th$n
st!t$
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+nt . +nt :?
$#s$
+nt . +nt 6 :?
$nd i)?
5is code section is processed ene)er an e)ent occurs on . 5e if
state#ent cec9s to see if is no 1 and as pre)iousl% a / +J#!st=&!#$
J9J. ;f tis is true+ntis incre#ented once. ;f tis is false,ic #eans tat
canged fro# a 1 to a / ten +ntis decre#ented once. 5e final result ill
tell te user at te last change as +a +nt)alue of 1 indicates a cange
fro# / to 1 and a / +nt )alue indicates te last cange as fro# 1 to /.
Other Conditional Statements
S3nt!.
(i- WHEN ELSE st!t$
(ii- id$nti)i$' $,'$ssion:
WHEN +ondition :
ELSE $,'$ssion1 WHEN +ondition1
ELSE $,'$ssion WHEN +ondition
ELSE $,'$ssionN WHEN OTHERS?
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Id$nti)i$' is !ssign$d th$ $,'$ssion )o' th$ WHEN +ondition th!t
is t'$2
=xa#ple:
print1 JD user1 H= +en D I1I and sel D I/I =7S=
user2 H= +en D I1I and sel D I1I =7S=
user3 H= C5H=0S>
CASE St!t$
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H= S'B D N :D A * B>
H= M'7 D N :D A K B>
H= !;6 D N :D A K B>
H= C5H=0S D N :D N>
=! GAS=>
=! $0CG=SS>
Syntax
WITH SELECT st!t$
&. 7CC$S
Th$ Fo' Loo,
5e )o' #oo,is used to repeat te execution of a section of code for a gi)en
nu#ber of ti#es. 5e general s%ntax for a for loop is:
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)o' &!'i!"#$ in '!ng$ #oo,
st!t$
2
2
process+x
)ariable p : std?logic>
begin
p :D I/I>
for i in & donto / loop
p :D p xor x+i>
end loop>
end process>
5e first line is a signal assign#ent not enclosed in an entit%. A local )ariable
+, is assigned itin te process and it is initialied to / en te process is
begun in response to an e)ent on . 5e eigt bits of are exclusi)el% C0ed
it eac oter to produce te e)en parit% for te ord in . en entering
te loop i is initialied to te first )alue in te range +&. ;n te first iteration of
te loop (>- is OC0ed it , (9- te result is returned to , and i is
decre#ented. ;n te second iteration (- is OC0ed it , again and te
result once #ore is returned to ,and i is decre#ented again. 5is seuence
repeats until i 925e last iteration OC0s (9-it te accu#ulated result
in , and exits te loop. en te loop is finised ,ill old te e)en parit%
state for ord .
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2 STRUCTURAL DESIGN
5e arcitecture bloc9 defines o te entit% operates and can be described
in #an% a%s to of ic are #ost pre)alent: structural and bea)ioral
+data flo. e a)e alread% loo9ed at te bea)ior t%pe of arcitecture. 5is
section explores te st'+t'!# !,,'o!+hic defines o te entit% is
constructed * at logic de)ices #a9e up te design. 5e general for#at for
te structural arcitecture is:
!'+hit$+t'$ !'+hit$+t'$=n!
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te source entit% bloc9 exactl%. Cnce te co#ponent is declared it #a% be
inst!nti!t$d (+o,i$d- and reused an% nu#ber of ti#es itin te design b%
te use of tis code:
,!'t=n!
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end #%?nor>
** begin latc design
entit% latc is
port +sr : in std?logic>
n : out std?logic>
end latc>
arcitecture flipflop of latc is
** C0 gate co#ponent declaration
co#ponent nor?gate
port +ab : in std?logic> c out std?logic>
end co#ponent>
begin
** instantiation of to C0 gates
n1 : nor?gate
port #ap +r n >
n2 : nor?gate
port #ap +s n>
end flipflop>
A nu#ber of concepts are illustrated b% tis exa#ple. First e a)e te
co#ponent declaration placed in te arcitecture bloc9 preceding te
arcitecture bod%. ;t starts it te reser)e ord +o
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co#ponent and its corresponding entit% declarations are identical except for
te co#ponent and entit% reser)ed ords. 5e i#portance of tis is tat e
ill declare to instances of tis obte sa#e order as te co#ponent ob
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Before e code tis one letIs ta9e a close loo9 at te circuit. 5ere are four
parts: to A! one C0 and one ;6=05=0 gate. Man% of te co#ponent
signals are connected to external signals:
Sel connected to O1 * A and O3 * A
Ain to O1 * B
Bin to O2 * A
!out to O4 * N
5ere are also internal signal connections beteen co#ponents ic a)e
te folloing labels:
otS * connects output of in)erter to O2 * B
S1 * connects O1 * N to O4 * A
S/ * connects O2 * N to O4 * B
;n a structural design te internal signals are declared using te SIGNAL
declaration ic as te s%ntax:
SIGNAL . T0PE?
otice te lac9 of a #ode designation in te signal declaration. 5is is
because tese are interconnecting signals beteen co#ponents. 5is
#eans tat te% are connecting an output fro# one co#ponent to te input of
anoter. 5at alone ould #a9e it difficult to declare a #ode for te#.
Secondl% te% are internal interconnecting signals. !irection is deter#ined
b% existing port interface declarations of te entities of te co#ponents being
connected.
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For a structural design %ou are onl% stating o parts are connected
togeter. 5e design depends on pre)iousl% defined bea)ior of te indi)idual
parts ic deter#ine o te design ill or9. it all of tis letIs code te
design in structural description.
librar% ;===>
use ;===.std?logic?114.all>
** !efine tree logic co#ponents
** A! ate
entit% #%?and is
port + A B : in std?logic>
N : out std?logic >
end #%?and>
arcitecture and?gate of #%?and is
begin
N JD A and B>
end and?gate>
** C0 gate
entit% #%?or is
port + A B : in std?logic>
N : out std?logic >
end #%?or>
arcitecture or?gate of #%?or is
begin
N JD A or B>
end or?gate>
** ;n)erter gate
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entit% #%?in) is
port + A : in std?logic>
N : out std?logic >
end #%?in)>
arcitecture in)?gate of #%?in) is
begin
N JD not A>
end in)?gate>
** Start 2*bit #ultiplexor
entit% #%?#ux is
port + Sel Ain Bin : in std?logic>
!out : std?logic >
end #%?#ux>
arcitecture #ux?c9t of #%?#ux is
** signal declarations
signal S/ S1 otS : std?logic>
** co#ponent declarations
co#ponent #%?and is
port + A B : in std?logic>
N : out std?logic >
end co#ponent>
co#ponent #%?or is
port + A B : in std?logic>
N : out std?logic >
end co#ponent>
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co#ponent #%?in) is
port + A : in std?logic>
N : out std?logic >
end co#ponent>
** structural design bod%
begin
O1 : #%?and port #ap + Sel Ain S1 >
O2 : #%?and port #ap + Bin otS S/ >
O3 : #%?in) port #ap + Sel otS >
O4 : #%?or port #ap + S1 S/ !out >
end #ux?c9t>
5e design begins b% defining tree logic gates #%?and #%?or and #%?in)
for A! C0 and ;6=05=0 gates. All tree of tese gates could also a)e
been i#ported fro# a librar% file. 5is design includes te tree entit% designs
for te logic gates. =ac arcitecture of te gate designs is in bea)ior or
data flo for#. 5at is te bea)ior of te gate is described for eac. ;n te
arcitecture bloc9 tere are se)eral declarations #ade before te beginning
of te bod% portion. 5e first declares te internal signals used in te design.
Since 6H!7 is ierarcical in nature tese signal declarations a)e to #ade
before te co#ponent instantiations tat use te#.
5e re#aining declarations define te co#ponents used b% te
arcitecture.After teir declarations starts te bod% of te arcitecture bloc9
designated b% te begin reser)e ord. 7oo9 at te si#plicit% of tis part of tedesign. ;ts onl% a list of co#ponents and o signals are connected to te#.
X:andX1 are copies of #%?andXof #%?in) and XBof #%?or. otice tat
te port #ap signals are in te sa#e order as te co#ponent and entit% port
declarations. Suppose %ou do not 9no te order. 5ere is a a% around tat
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9non as DIRECT ASSOCIATIONic does reuire #ini#all% tat %ou
9no te port signal na#es and teir intended use. Here is an alternate a%
of instantiating X: as #%?and:
X: .
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!out : out std?logic?)ector + & donto / >
Sel : in std?logic >
end eigt?#ux>
arcitecture #ultiplex of eigt?#ux is
** declare #%?#ux co#ponent
co#ponent #%?#ux is port #ap + Ain Bin Sel : in std?logic>
!out : out std?logic >
end co#ponent>
** instantiate #%?#ux co#ponent eigt ti#es
begin
M& : #%?#ux port #ap + Ain+& Bin+& Sel !out+& >
M : #%?#ux port #ap + Ain+ Bin+ Sel !out+ >
M" : #%?#ux port #ap + Ain+" Bin+" Sel !out+" >
M4 : #%?#ux port #ap + Ain+4 Bin+4 Sel !out+4 >
M3 : #%?#ux port #ap + Ain+3 Bin+3 Sel !out+3 >
M2 : #%?#ux port #ap + Ain+2 Bin+2 Sel !out+2 >
M1 : #%?#ux port #ap + Ain+1 Bin+1 Sel !out+1 >
M/ : #%?#ux port #ap + Ain+/ Bin+/ Sel !out+/ >
end eigt?#ux>
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AN APPROACH TO FPGA IMPLEMENTATION WITH QUARTUS II
SOFTWARE
5e folloing steps ill elp to use Quartus ;; softare for )arious issues
related to F$A ;#ple#entation.
Step 1: As soon as te Quartus ;; softare is opened after necessar% license file
;nstallations a e $ro
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Step : After correcting errors if an% te ;C pins a)e to be specified fro# $in
$lanner ic is a)ailable in Assign#ents toolbar. As soon as te
s%ntesis process is o)er te pin planner ill contain te list of all pins
present in te entit% of te design.
Step &: 5e design as to be Go#piled. 5is can be perfor#ed b% coosing te
option Start Go#pilation fro# $rocessing toolbar +ie P'o+$ssing 6K
St!'t Co
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LIST OF EXPERIMENTS
VHDL Coding (With suitable Behavioral Data !lo" and Stru#turalDes#riptions$ !or%
Basic gates
1. Half Adder and Half Subtractor
2. Full Adder and Full Subtractor
3. 8:1 Multiplexer
4. 4:1 !ecoder
". Four bit co#parator using single bit co#parator
. 8:3 $riorit% encoder
&. Four bit adders
8. Signed and 'nsigned #ultiplier
(. Master sla)e flip*flop+! t%pe and ,*- t%pe
1/. Four bit 0ipple counter and 'p*don counter
11. 'ni)ersal sift register
12. State #acine #odelling of Meela% #acine and Moore #acine.
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PRELIMINAR0 EXPERIMENT
%ASIC LOGIC GATES
D!t$.
AIM.
5o rite 6H!7 progra#s to i#ple#ent te folloing logic gates.
+a C5 +b 2 input C0 +c 2 input C0 +d 2 input A! +e 2 input A!
+f 2 input OC0 +g 2 input OC0.
ALGORITHM.
1. Start te progra#.
2. ;nclude te ;=== librar% and te std?logic?114.all pac9age.
3. !eclare te entit% of te gate.
4. !efine te input and te output ports
". =nd te entit%.
. !eclare te arcitecture of te gate.
&. !efine te functionalit% of te gate at bea)ioral le)el .
8. =nd te arcitecture.(. 7oad te design si#ulate te a)efor# and )erif% te trut*table.
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LOGIC DIAGRAMS AND TRUTH TA%LES OF %ASIC GATES
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PORT DIAGRAM
a. ;n)erter b.2 ;nput logic gates
PROGRAMS.
!2 In&$'t$'
librar% ieee>
use ieee.std?logic?114.all>
entit% in) is
port+x: in std?logic>
F: out std?logic>
end in)>
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arcitecture in)?be of in) is
begin
F JD not x>
end in)?be>
"2 1 In,t OR g!t$
librar% ieee>
use ieee.std?logic?114.all>
entit% C0?ent is
port+x: in std?logic>
%: in std?logic>
F: out std?logic>
end C0?ent>
arcitecture C0?be of C0?ent is
begin
F JD x or %>
end C0?be>
+2 1 In,t NOR g!t$
librar% ieee>
use ieee.std?logic?114.all>
entit% C0?ent is
port+x: in std?logic>
%: in std?logic>
F: out std?logic>
end C0?ent>
arcitecture be)2 of C0?ent is
begin
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F JD x nor %>
end be)2>
d21 In,t AND g!t$
librar% ieee>
use ieee.std?logic?114.all>
entit% A!?ent is
port+x: in std?logic>
%: in std?logic>
F: out std?logic>
end A!?ent>
arcitecture bea)2 of A!?ent is
begin
F JD x and %>
end bea)2>
$21 In,t NAND g!t$
librar% ieee>
use ieee.std?logic?114.all>
entit% A!?ent is
port+x: in std?logic>
%: in std?logic>
F: out std?logic>
end A!?ent>
arcitecture be)2 of A!?ent is
begin
F JD x nand %>
end be)2>
)21 In,t XOR g!t$
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librar% ieee>
use ieee.std?logic?114.all>
entit% OC0?ent is
port+x: in std?logic>
%: in std?logic>
F: out std?logic>
end OC0?ent>
arcitecture be)2 of OC0?ent is
begin
F JD x xor %>
end be)2>
g21 In,t XNOR g!t$
librar% ieee>
use ieee.std?logic?114.all>
entit% OC0?ent is
port+x: in std?logic>
%: in std?logic>
F: out std?logic>
end OC0?ent>
arcitecture be)2 of OC0?ent is
begin
F JD x xnor %>
end be)2>
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1 In,t OR g!t$
1 In,t NOR g!t$
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1 In,t AND g!t$
1 In,t NAND g!t$
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1 In,t XOR
1 In,t XNOR g!t$
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RESULT.
5e basic logic gates ere si#ulated in MODELSIMand te corresponding trut
tables )erified.
NOTE.
0ecord boo9 sould be #aintained in te folloing for#at.
a. =xperi#ent u#ber
b. !ate
c. Ai# of te experi#ent
d. Algorit#
e. 7ogic diagra#
f. 5rut table
g. $ort diagra#
. 7isting of te progra#
i. a)efor#s
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- 5e students are expected to co#plete te acti)ities #entioned.
HALF ADDER AND HALF SU%TRACTOR
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". =nd te entit% .
. !eclare te arcitecture of alf adderalf subtractor.
&. !efine te functionalit% of alf adder and alf subtractor at
bea)ioral le)el using if*else it*select and case*en en*else
state#ents respecti)el%.
8. =nd te arcitecture.
(. 7oad te design si#ulate te a)efor# and )erif% te trut*table.
PROGRAMS.
!- H!#) !dd$' sing i)6th$n.
entit% alfadder is
port+ a:in std?logic?)ector+1 donto />su#carr%: out std?logic>
end alfadder>
arcitecture alfadder?arc of alfadder is
signal s:std?logic?)ector+1 donto />
begin
process+a
begin
if aD// ten sJD//>
elsif aD/1 ten sJD1/>
elsif aD1/ ten sJD1/>
else sJD/1>
end if>
end process>
carr%JDs+/>
su#JDs+1>
end>
"- H!#) !dd$' sing *ith s$#$+t st!t$
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entit% alfadder1 is
port+ a:in std?logic?)ector+1 donto />su#carr%: out std?logic>
end alfadder1>
arcitecture alfadder?arc of alfadder1 is
signal s:std?logic?)ector+1 donto />
begin
it a select
sJD E// en E//
E1/ en E/1
E1/ en E1/
E/1 en E11>
carr%JDs+/>
su#JDs+1>
end>
!- H!#) S"t'!+to' sing +!s$ *h$n st!t$db: out std?logic>
end alfsub>
arcitecture alfsub?arc of alfsub is
signal s:std?logic?)ector+1 donto />
begin
process+a
begin
case a is
en E//DsJD//>
en E/1DsJD11>
en E1/DsJD1/>
en E11DsJD//>
en otersDnull>
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end case>
end process>
bJDs+/>
dJDs+1>
end>
"- H!#) S"t'!+to' sing *h$n $#s$ st!t$db: out std?logic>
end alfsub1>
arcitecture alfsub?arc of alfsub1 is
signal s:std?logic?)ector+1 donto />
begin
sJD// en aD// else
E11 en aD/1 else
E1/ en aD1/ else
E//>
bJDs+/>
dJDs+1>
end>
RESULT.
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ACTIVIT0 .
1. rite te 6H!7 coding for realiing te function of alf adder using 2 input
A! gates and )erif% te result.
2. rite te 6H!7 coding for realiing te function of alf adder using 2 input
C0 gates and )erif% te result.
3. rite a 6H!7 coding for coding for alf subtractor using 2 input A! gates and
)erif% te result. 'se #ini#u# nu#ber of A! gates.
4. rite a 6H!7 coding for coding for alf subtractor using 2 input A! gates and
)erif% te result. 'se #ini#u# nu#ber of C0 gates.
FULL ADDER !nd FULL SU%TRACTOR
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". =nd te entit%.
. !eclare te arcitecture of full adder.
&. !efine te functionalit% of full adder at bea)ioral le)el using if*else
it*select state#ents.
8. =nd te arcitecture.
(. !eclare te entit% for te full subtractor.
1/. !efine te input and te output ports for te full subtractor.
11 =nd te entit%.
12. !eclare te arcitecture of full subtractor.
13. !efine te functionalit% of full subtractor at bea)ioral le)el using if*
else it*select state#ents.
14. =nd te arcitecture.
1". 7oad te designs si#ulate te a)efor#s and )erif% te trut*tables.
PROGRAMS .
!-F## !dd$' sing i) th$n $#s$.
entit% fulladder is
port+ a:in std?logic?)ector+2 donto />su#carr%: out std?logic>
end fulladder>
arcitecture fulladder?arc of fulladder is
signal s:std?logic?)ector+1 donto />
begin
process+a
begin
if aD/// ten sJD//>
elsif aD//1 ten sJD1/>
elsif aD/1/ ten sJD1/>
elsif aD/11 ten sJD/1>
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elsif aD1// ten sJD1/>
elsif aD1/1 ten sJD/1>
elsif aD11/ ten sJD/1>
else sJD11>
end if>
end process>
carr%JDs+/>
su#JDs+1>
end>
"- F## Add$' sing *ith s$#$+t st!t$su# carr%: out std?logic>
end fulladder1>
arcitecture fulladder?arc of fulladder1 is
signal s:std?logic?)ector+1 donto />
begin
it a select
sJD E// en E///
E1/ en E//1
E1/ en E/1/
E/1 en E/11
E1/ en E1//
E/1 en E1/1
E/1 en E11/
E11 en E111>
carr%JDs+/>
su#JDs+1>
end>
+- F## S"t'!+to' sing i) th$n $#s$.
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entit% fullsub is
port+ a:in std?logic?)ector+2 donto />db: out std?logic>
end fullsub>
arcitecture fullsub?arc of fullsub is
signal s:std?logic?)ector+1 donto />
begin
process+a
begin
if aD/// ten sJD//>
elsif aD//1 ten sJD11>
elsif aD/1/ ten sJD11>
elsif aD/11 ten sJD/1>
elsif aD1// ten sJD1/>
elsif aD1/1 ten sJD//>
elsif aD11/ ten sJD//>
else sJD11>
end if>
end process>
bJDs+/>
dJDs+1>
end>
d- F## S"t'!+to' sing *ith s$#$+t.
entit% fullsub1 is
port+ a:in std?logic?)ector+2 donto />db: out std?logic>
end fullsub1>
arcitecture fullsub?arc of fullsub1 is
signal s:std?logic?)ector+1 donto />
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begin
it a select
sJD E// en E///
E11 en E//1
E11 en E/1/
E/1 en E/11
E1/ en E1//
E// en E1/1
E// en E11/
E11 en E111>
bJDs+/>
dJDs+1>
end>
RESULT.
ACTIVIT0.
1. rite te 6H!7 coding for realiing te function of full adder using 2 input
A! gates and )erif% te result.
2. rite te 6H!7 coding for realiing te function of full adder using 2 input
C0 gates and )erif% te result.
3. rite a 6H!7 coding for a single bit full adder using 2 alf adders and )erif% te
result. 'se structural le)el of #odeling.
4. rite te 6H!7 coding for realiing te function of full subtractor using 2 input
A! gates and )erif% te result.
". rite te 6H!7 coding for realiing te function of full subtractor using 2 input
C0 gates and )erif% te result.
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. rite te 6H!7 coding in structural #odel to design te folloing co#binational
circuits. Also tabulate te trut table for all co#binations of inputs.
Gircuit 1:
Gircuit 2:
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Gircuit 3:
.: MULTIPLEXER
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RESULT.
ACTIVIT0.
1. rite a 6H!7 coding for 8:1 Multiplexer using +iit select +ii en else
state#ents. ;#ple#ent 1:1 Multiplexer using 8:1 Multiplexer
2. rite a 6H!7 coding for realiing F+x%D + using 4:1 M'O and )erif%
te result.
3. rite a 6H!7 coding for realiing te function of alf adder using 2:1
#ultiplexer and )erif% te result.
4. rite a 6H!7 coding for realiing te function of alf subtractor using 2:1
#ultiplexer.
". rite a 6H!7 coding to realie full adder using 4:1 Multiplexer.
. rite a 6H!7 coding for realiing F+ABG!D V+ 134111213141"
using 4:1 M'O and )erif% te result .
B.: DECODER
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". =nd te entit%.
. !eclare te arcitecture of decoder.
&. !efine te functionalit% of decoder at bea)ioral le)el.
8. =nd te arcitecture.
(. 7oad te design si#ulate te a)efor# and )erif% te trut*table.
PROGRAMS.
!- Using +!s$*h$n st!t$
entit% decoder is
port+;:in std?logic?)ector+3 donto />
C:out std?logic?)ector+1" donto />
end decoder>
arcitecture be) of decoder is
begin
process +;
begin
case ; is
en R////R D C JD R///////////////1R>
en R///1R D C JD R//////////////1/R>
en R//1/R D C JD R/////////////1//R>
en R//11R D C JD R////////////1///R>
en R/1//R D C JD R///////////1////R>
en R/1/1R D C JD R//////////1/////R>
en R/11/R D C JD R/////////1//////R>
en R/111R D C JD R////////1///////R>
en R1///R D C JD R///////1////////R>
en R1//1R D C JD R//////1/////////R>
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en R1/1/R D C JD R/////1//////////R>
en R1/11R D C JD R////1///////////R>
en R11//R D C JD R///1////////////R>
en R11/1R D C JD R//1/////////////R>
en R111/R D C JD R/1//////////////R>
en R1111R D C JD R1///////////////R>
en oters Dnull>
end case>
end process>
end be)>
"- Loo8, t!"#$ A,,'o!+h.
librar% ieee>
use ieee.std?logic?114.all>
use ieee.std?logic?arit.all>
entit% decoder4x1 is
port+din : in std?logic?)ector+3 donto />
dout : out std?logic?)ector+1" donto />
end decoder4x1>
arcitecture bea)ioral of decoder4x1 is
t%pe arra%?t%pe is arra%+1" donto / of std?logic?)ector+1" donto />
signal decodeout : arra%?t%pe :D +R1///////////////R R/1//////////////R
R//1/////////////R R///1////////////R R////1///////////R
R/////1//////////RR//////1/////////R R///////1////////R
R////////1///////RR/////////1//////RR/////////1//////R
R///////////1////RR////////////1///RR/////////////1//R
R//////////////1/RR///////////////1R >
**5e order of arrange#ent of output )alues in 7'5 is )er% i#portant.
begin
process+din
begin
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case din is
en R////R D dout JD decodeout+/>
en R///1R D dout JD decodeout+1>
en R//1/R D dout JD decodeout+2>
en R//11R D dout JD decodeout+3>
en R/1//R D dout JD decodeout+4>
en R/1/1R D dout JD decodeout+">
en R/11/R D dout JD decodeout+>
en R/111R D dout JD decodeout+&>
en R1///R D dout JD decodeout+8>
en R1//1R D dout JD decodeout+(>
en R1/1/R D dout JD decodeout+1/>
en R1/11R D dout JD decodeout+11>
en R11//R D dout JD decodeout+12>
en R11/1R D dout JD decodeout+13>
en R111/R D dout JD decodeout+14>
en R1111R D dout JD decodeout+1">
en oters D dout JD +oters DI/I>
end case>
end process>
end bea)ioral>
RESULT.
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ACTIVIT0.
1. rite a 6H!7 coding for 3:8 decoder using +i;f else +ii en else state#ents.
Also i#ple#ent 4:1 decoder using 3:8 decoder.
2. rite a 6H!7 coding for 2:4 decoder using case en state#ent. Also
i#ple#ent 4:1 decoder using 2:4 decoder.
3. rite 6H!7 codings for 2:4 decoder and 3:8 decoder using loo9up table
#etod.
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&. !efine te functionalit% of co#parator at bea)ioral le)el using if*else
state#ents.
8. =nd te arcitecture.
(. 7oad te design si#ulate te a)efor# and )erif% te trut*table.
PROGRAM.
librar% ieee>
use ieee.std?logic?114.all>
entit% co#parator is
generic+n: natural :D4>
port+A:in std?logic?)ector+n*1 donto />
B:in std?logic?)ector+n*1 donto />
less:out std?logic>
eual:out std?logic>
greater:out std?logic>
end co#parator>
arcitecture be) of Go#parator is
begin
process+AB
begin
if +AJB ten
less JD I1I>
eual JD I/I>
greater JD I/I>
elsif +ADB ten
less JD I/I>
eual JD I1I>
greater JD I/I>
else
less JD I/I>
eual JD I/I>
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greater JD I1I>
end if>
end process>
end be)>
RESULT.
ACTIVIT0.
1.rite a 6H!7 coding for realiing 1 bit co#parator using A! gates and
)erif% te result. Also i#ple#ent 4 bit co#parator fro# te lo le)el design. 'se
For generate s%ntax for realiing te top le)el progra#.
2.rite a 6H!7 coding for realiing 1 bit co#parator using C0 gates and )erif%
te result. Also i#ple#ent 4 bit co#parator fro# te lo le)el design. 'se ;F
generate s%ntax for realiing te top le)el progra#.
. PRIORIT0 ENCODER
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". =nd te entit%.
. !eclare te arcitecture of priorit% encoder.
&. !efine te functionalit% of priorit% encoder at bea)ioral le)el.
8. =nd te arcitecture.
(. 7oad te design si#ulate te a)efor# and )erif% te trut*table.
PROGRAM:
librar% ieee>
use ieee.std?logic?114.all>
entit% priorit% is
port + : ;n std?logic?)ector+& donto />
% : Cut std?logic?)ector+2 donto />
end priorit%>
arcitecture bea)ior of priorit% is
begin
% JDR111R en +& D I1I else
R11/R en + D I1I else
R1/1R en +" D I1I else
R1//R en +4 D I1I else
R/11R en +3 D I1I else
R/1/R en +2 D I1I else
R//1R en +1 D I1I else
R///R>
end bea)ior>
RESULT.
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ACTIVIT0.
1. rite a 6H!7 coding for 8:3 priorit% encoder. i)e priorit% to ????? bit.
2. rite a 6H!7 code for i#ple#enting 4:2 encoder using icase..en and
ii if..ten..else state#ents
3. rite a 6H!7 code for i#ple#enting 8:3 encoder using structural #odel.
FOUR %IT ADDER
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D!t$.
AIM.
5o rite a 6H!7 progra# to i#ple#ent a )o' "it 'i,,#$ +!''3 !dd$'using single bit
full adder.
ALGORITHM.
1. Start te progra#.
2. ;nclude te ;=== librar% and te std?logic?114.all pac9age.
3. !eclare te entit% for te loer le)el +single bit full adder .
4. !efine te input and te output ports.
". =nd te entit% for te loer le)el.
. !eclare te arcitecture of. loer le)el.
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&. !efine te functionalit% of loer le)el at bea)ioral le)el .
8. =nd te arcitecture for te loer le)el.
(. !eclare te entit% for te four bit ripple carr% adder .
1/. !efine te input and te output ports for te four bit ripple carr%
adder.
11. =nd te entit%.
12. !eclare te arcitecture of te four bit ripple carr% adder
13. !efine te functionalit% of te four bit ripple carr% adder at a structural
le)el using te loer le)el single bit full adder.
14. =nd te arcitecture.
1". 7oad te design si#ulate te a)efor# and )erif% te trut*table.
PROGRAMS.
!-Sing#$ "it )## !dd$'.
entit% fulladd is
port+ a:in std?logic?)ector+2 donto />su#carr%: out std?logic>
end fulladd>
arcitecture fulladder?arc of fulladd is
signal s:std?logic?)ector+1 donto />
begin
process+a
begin
if aD/// ten sJD//>
elsif aD//1 ten sJD1/>
elsif aD/1/ ten sJD1/>
elsif aD/11 ten sJD/1>
elsif aD1// ten sJD1/>
elsif aD1/1 ten sJD/1>
elsif aD11/ ten sJD/1>
else sJD11>
end if>
end process>
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carr%JDs+/>
su#JDs+1>
end>
"- Fo' "it 'i,,#$ +!''3 !dd$' sing i)6g$n$'!t$.
librar% ieee >
use ieee.std?logic?114.all >
entit% adder4 is
port + x % : in std?logic?)ector+3 donto / > cin : in std?logic >
s : out std?logic?)ector+3 donto / >cout : out std?logic >
end adder4 >
arcitecture structure of adder4 is
signal c : std?logic?)ector+/ to 4 >
begin
c+/ JD cin >
g1:for i in / to 3 generate
stages: fulladder port #ap +x+i %+i c+i s+i c+iL1 >
end generate>
cout JD c+4 >
end structure >
+- Fo' "it !dd$' sing st'+t'!#
use ieee.std?logic?114.all >
entit% adder4 is
port + x % : in std?logic?)ector+3 donto / >
cin : in std?logic >
s : out std?logic?)ector+3 donto / >
cout : out std?logic >
end adder4 >
arcitecture structure of adder4 is
signal c : std?logic?)ector+1 to 3 >
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begin
stage/: fulladd port #ap + x+/ %+/ cin s+/ c+1 >
stage1: fulladd port #ap + x+1 %+1 c+1s+1 c+2 >
stage2: fulladd port #ap + x+2 %+2 c+2s+2 c+3 >
stage3: fulladd port #ap + x+3 %+3 c+3s+3 cout >
end structure >
RESULT.
ACTIVIT0.
1. rite a 6H!7 coding for BG! adder circuit and )erif% te result .
2. rite a 6H!7 coding for carr% propagate adder circuit and )erif% te result .
3.rite a 6H!7 coding for 8 bit adder using 8 single bit full adder. 'se For generate
s%ntax for te top le)el design. ;#ple#ent full adder using ????????state#ent.
SIGNED AND UNSIGNED MULTIPLIERS
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3. !eclare te entit% for te to bit binar% #ultiplier .
4. !efine te input and te output ports.
". =nd te entit%.
. !eclare te arcitecture for te to bit binar% #ultiplier.
&. !efine te functionalit% for te to bit binar% #ultiplier.
8. =nd te arcitecture.
(. 7oad te design si#ulate te a)efor# and )erif% te trut*table.
PROGRAM.
librar% ieee>
use ieee.std?logic?114.all>
use ieee.std?logic?arit.all>
use ieee.std?logic?unsigned.all>
entit% #ultiplier is
port+nu#1 nu#2:in std?logic?)ector+1 donto />
product: out std?logic?)ector+3 donto />
end #ultiplier>
arcitecture be) of #ultiplier is
begin
process+nu#1 nu#2
)ariable nu#1?reg: std?logic?)ector+2 donto />
)ariable product?reg: std?logic?)ector+" donto />
begin
nu#1?reg :D I/I @ nu#1>
product?reg :D R////R @ nu#2>
** algorit# is to repeat siftingadding
for i in 1 to 3 loop
if product?reg+/DI1I ten
product?reg+" donto 3 :D product?reg+" donto 3
L nu#1?reg+2 donto />
end if>
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product?reg+" donto / :D I/I @ product?reg+" donto 1>
end loop>
** assign te result of co#putation bac9 to output signal
product JD product?reg+3 donto />
end process>
end be)>
RESULT.
ACTIVIT0.
1. rite a 6H!7 coding for a 4 bit binar% arra% #ultiplier and )erif% te result.
2. rite a 6H!7 coding for 4bit O 3 bit binar% #ultiplier and )erif% te result.
3. rite a 6H!7 coding for 4 bit Baug oole% #ultiplier and )erif% te result.
4. rite a 6H!7 coding for 4bit Braun #ultiplier and )erif% te result.
MASTER SLAVE FLIP FLOPS (D T0PE AND 6/ T0PE-
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. !eclare te arcitecture of ! flip flop .
&. !efine te functionalit% of ! flip flop at bea)ioral le)el .
8. =nd te arcitecture.
(. 7oad te design si#ulate te a)efor# and )erif% te trut*table.
PROGRAMS.
F#i, )#o, *ith !s3n+h'onos '$s$t.
librar% ieee>
use ieee.std?logic?114.all>
entit% dff is
port+data?in:in std?logic>
cloc9:in std?logic>
reset: in std?logic>
data?out:out std?logic>
end dff>
arcitecture be) of dff is
begin
process+cloc9reset
begin
if resetD/ ten data?out JD U/>
elsif +cloc9Ie)ent and cloc9DI1I ten
data?out JD data?in>
end if>
end process>
end be)>
F#i, )#o, *ith s3n+h'onos '$s$t.
librar% ieee>
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use ieee.std?logic?114.all>
port+data?in:in std?logic>
cloc9:in std?logic>
reset: in std?logic>
data?out:out std?logic>
end dff>
arcitecture be) of dff is
begin
process+cloc9
begin
if +cloc9Ie)ent and cloc9DI1I ten
if resetD/ ten
data?out JD U/>
else
data?out JD data?in>
end if>
end if>
end process>
end be)>
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RESULT.
ACTIVIT0.
:2rite a 6H!7 coding for realiing cloc9ed ,- flip flop using A! gates along
it preset and clear action.
12 rite a 6H!7 coding for realiing #aster sla)e ! flip flop and )erif% te result.
2 rite a 6H!7 coding for realiing #aster sla)e ,*- flip flop and )erif% te result.
FOUR %IT RIPPLE COUNTER AND UP DOWN COUNTER
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4. !efine te input and te output ports.
". =nd te entit%.
. !eclare te arcitecture of te 3 bit '$!C counter.
&. !efine te functionalit% of 3 bit '$!C counter at bea)ioral
le)el.
8. =nd te arcitecture.
(. 7oad te design si#ulate te a)efor# and )erif% te trut*table.
PROGRAM.
librar% ieee>
use ieee.std?logic?114.all>
use ieee.std?logic?unsigned.all>
entit% updon is
port+cl9reset: in std?logic>
countenup:in std?logic>
su#:out std?logic?)ector+2 donto />
cout:out std?logic>
end>
arcitecture rtl of updon is
signal count: std?logic?)ector+2 donto />
begin
process+cl9reset
begin
if resetD/ ten countJD+otersD/>
elsif cl9e)ent and cl9D1 ten
if countenD1 ten
case up is
en U1 DGountDcountL1>
en oters DGountDcount*1>
end case>
end if>
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end if>
end process>
su#JDcount>
coutJD1 en countenD1 and ++upD1 and countD& or +upD/ and
countD/ else/>
end>
RESULT.
ACTIVIT0.
1. rite a 6H!7 coding for 4 bit 0ipple counter using ! flip*flop and )erif% te
result.
2. rite a 6H!7 coding for 4 bit '$!C counter using 5 flip flop and )erif%
te result.
UNIVERSAL SHIFT REGISTER
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. !eclare te arcitecture of sift register.
&. !efine te functionalit% of sift register at bea)ioral le)el .
8. =nd te arcitecture.
(. 7oad te design si#ulate te a)efor# and )erif% te trut*table.
PROGRAM.
librar% ieee >
use ieee.std?logic?114.all>
entit% sift?reg is
port+;:in std?logic>
cloc9:in std?logic>
sift:in std?logic>
Q:out std?logic>
end sift?reg>
arcitecture be) of sift?reg is
signal S: std?logic?)ector+2 donto /:DR111R>
begin
process+; cloc9 sift S
begin
** e)er%ting appens upon te cloc9 canging
if cloc9Ie)ent and cloc9DI1I ten
if sift D I1I ten
S JD ; @ S+2 donto 1>
end if>
end if>
end process>
** concurrent assign#ent
Q JD S+/>
end be)>
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1. Start te progra#.
2. ;nclude te ;=== librar% and te std?logic?114.all pac9age.
3. !eclare te entit% for te gi)en #oore state #acine .
4. !efine te input and te output ports.
". =nd te entit%.
. !eclare te arcitecture of #oore state #acine.
&. ;nitialise all te states of te finite state #acine.
8. !efine te functionalit% of #oore state #acine at bea)ioral le)el .
(. =nd te arcitecture.
1/. 7oad te design si#ulate te a)efor# and )erif% te trut*table.
MOORE STATE MACHINE.
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PROGRAM.
librar% ieee>
use ieee.std?logic?114.all>
entit% #oorefs# is
port+le)elcl9 :in std?logic>
tic9 :out std?logic>end #oorefs#>
arcitecture ar of #oorefs# is
t%pe state?t%pe is +eroedgone>
signal state:state?t%pe>
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begin
process+cl9le)elstate
begin
if cl9Ie)ent and cl9 D I1I ten
case state is
en ero D
tic9 JD I/I>
if le)el D I1I ten
state JD edg>
else
state JD ero>
end if>
en edg D
tic9 JD I1I>
if le)el D I1I ten
state JD one>
else
state JD ero>
end if>
en one D
tic9 JD I/I>
if le)el D I1I ten
state JD one>
else
state JD ero>
end if>
end case>
end if>
end process>
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end>
RESULT.
ACTIVIT0.
1. rite a 6H!7 code to design a Moore state #acine ic as te states
s/s1s2 @ s3.
2. rite a 6H!7 code to design a Meal% state #acine it tree states na#el%
onetotree.
FREQUENC0 DIVIDER
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librar% ieee>
use ieee.std?logic?114.all>
use ieee.std?logic?arit.all>
entit% cloc9di)ider1 is
port+cl9inreset : in std?logic> ** cl9in force )alue D 2/ns+for an ip cloc9 freuenc% of
** "/MH
cl9out : out std?logic>
end cloc9di)ider1>
arcitecture bea)ioral of cloc9di)ider1 is
signal count :integer range / to 2///:D/>
begin
process+cl9inreset
begin
if reset D I1I ten ** as%ncronous reset
cl9out JD I/I>
count JD />
elsif cl9inIe)ent and cl9in D I1I ten
count JD count L 1>
if count JD 24 ten
cl9out JD I1I>
elsif count 24 and count J 12"/ ten
cl9out JD I/I>
else
count JD 1>
cl9out JD I1I>
end if>
end if>
end process>
end bea)ioral>
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RESULT.
ACTIVIT0.
1. enerate a cloc9 signal it freuenc% 1/-H and dut% c%cle 2"&". Assu#e te
input cloc9 c%cle period as 2"ns.
2. enerate a cloc9 signal it freuenc% 12"-H and dut% c%cle "/"/. Assu#e te
input cloc9 freuenc% as /MH.
QUESTIONS
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Int'od+tion
1. at t%pe of language is 6H!7X
2. at is te basic building unit of a 6H!7 designX
3. at do all 6H!7 designs begin itX
4. ic bloc9 describes a designIs interfaceX
". ic bloc9 describes a designIs bea)iorX
. at is te difference beteen si#ulation and
s%ntesisX
D!t! T3,$s
&. 6H!7 is a ???????????? t%ped language.
8. ic data t%pe defines a single logic signalX
(. ic data t%pe describes a busX
1/. at to a%s can a )ectorIs range be describedX
11. at are te ;=== S5!?7C;G?114 data t%pes for
single logic signals and busesX
12. % is it desirable to use ;=== S5!?7C;G?114
data t%pingX at is te difference beteen resol)ed
and unresol)ed logicX
13. at are te onl% to )alues for a Boolean t%peX
14. at are te nu#erical data t%pesX
1". at is S'B5N$; used forX
1. at t%pe is use to create a user data t%peX
1&. at reser)ed ord is used to declare a user data
t%peX
18. Greate te use data t%pe DA0Sand assign it te
)alues: MON TUE WED THU FRI SATand SUN.
1(. ic data t%pe is used for a string of ASG;;
caractersX
2/. ic data t%pe includes ti#e units as )aluesX
Entit3
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21. Greate te entit% bloc9 for a tree input OC0 gate.
22. ic s%#bol is used to end all 6H!7 state#entsX
23. at part of a port declaration defines a signals in or
out directionX
24. ic 6H!7 construct is used to define a literal
constant in an entit% bloc9X
2". Greate te integer constant included in an entit% bloc9
called %US=SI;Eand assign it a )alue of 32.
2. ic s%#bols are used as an assign#ent operator to
assign a literal to an identifier na#eX
A'+hit$+t'$ %#o+8
2&. at are te to pri#ar% a%s to describe a logic
circuits function itin an arcitecture bloc9X
28. Greate te arcitecture bloc9 for te 3*input OC0 gate
of uestion 21.
2(. ic s%#bols are used to assign an expressionIs
result to an output interface signalX
3/. at are te rules used to define an identifier na#eX
31. at s%#bols define a co##ent lineX
32. rite te state#ents tat ill allo a design to access
all te contents of te ;=== A0;5H librar%.
33. Add a 2" ns inertial dela% to te OC0 assign#ent
state#ent of uestion 28.
34. Ma9e te dela% in uestion 33 transport rater tan
inertial.
3". Ho does a transport dela% differ fro# an inertial
dela%X
3. at is te purpose of a SIGNALdeclarationX
3&. ere are SIGNALdeclarations placed in te designX
38. rite an assign#ent state#ent tat assigns te
contents of s(@-to t(1-.
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3(. rite an assign#ent state#ent tat copies all te
states of d!t!="sto d!t!=in. 5e% are bot 8*bit
buses.
P'o+$ss
4/. State#ents in an arcitecture bloc9 are executed
???????????????? .
41. State#ents in a process bloc9 are executed
??????????????.
42. at is te purpose of a processI sensiti)it% listX
43. 'nder at conditions is a process runX
44. at is an EVENTX
4". at is te difference beteen e)ent and non*e)ent
dri)en process executionX
4. rite a process bloc9 tat 9eeps a running tall% of eac
ti#e an interrupt +INT signal is asserted ig.
4&. ic s%#bols are used to differentiate beteen a
logic 1 and an integer 1X
48. ic s%#bols are used to differentiate beteen a
logic 1/11 and an integer 1/11X
4(. at are te results of using CL/J$&$ntas a condition
in te i)state#ent of te DEFexa#pleX
Condition!# St!t$
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. at is a #oduleX
&. ere do #odules get teir functions and interface
signalsX