HDH PIF 32000 eVC ArchitecturePIF eVC is a fully eRM verification component composedby master and slave PIF agents, able to generate andtransmit transactions as a master ,or to respond to trans-action requests as a slave, according to PIF protocol.Transactions has all fields needed to model any kind ofphysical transaction on PIF interface : all types of requests,delays, capability for error injection, etc...PIF eVC can be configured to be only passive component(monitor). Monitor logs all traffic information, has abilityto check if there is any violation of PIF protocol and to col-lects items for functional coverage.

HDH PIF 32000 - Solution for theverification of PIF-based systems

HDL Design House, Golsvortijeva 35, Belgrade, Serbia

Phone: +381 11 414 55 55 Fax: +381 11 414 55 59 Email: info@hdl-dh.com On-line: http://www.hdl-dh.com

HDH_PIF 32000-1.0 DS.REV.1.0

30.08.2011.

Key Features:

• Configurable as Master or Slave

•Configurable as passive or active

•Slave can be configures as RAM

•All five request types are supported:- Single data read request- Single data write request- Block-read request- Block-write request

•Multiple requests are supported

•Out of order responses are fully supported

•Built-in set of coverage items

•Protocol checkers fully compliant with PIF protocol

•Database of predefined sequences

•Ability to control response

Benefits:

• PIF eVC is plug and play component – ready-to-use and configurable verification environment

•Easy to integrate and use

•Randomization of sequences and tests to speedup the verification processs

•Set of functional coverage items and protocolcheckers

The Verification IP (VIP) for the Tensilica ProcessorInterface (PIF)® provides a quick and efficient way to verifyPIF based SoC designs by implementing advanced tech-niques for more productive verification. The VIP for PIF supports the e/Specman hardware verifica-tion language and the e Reuse Methodology (eRM). TheeRM defines a coverage driven methodology for using aconstrained random environment. The Master and SlaveVIP can be configured to represent any PIF-based masteror slave component. The protocol monitors providedebug information, protocol violation notification andprotocol coverage metrics. In addition the monitorincludes performance monitoring capabilities enablingdesigners to accurately measure the bandwidth andlatency of the subsystem.PIF eVC is the complete solution for the verification of PIF-based systems. It has a complete built-in set of predefinedcoverage items and protocol checkers that are fully com-pliant with PIF protocol. Most of possible PIF scenarios aredefined trought predefined sequences. PIF eVC can beused verification environments both at module, subsys-tem and system level.

It has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.

HDH PIF 32000 - Solution for theverification of PIF-based systems

HDL Design House, Golsvortijeva 35, Belgrade, Serbia

Phone: +381 11 414 55 55 Fax: +381 11 414 55 59 Email: info@hdl-dh.com On-line: http://www.hdl-dh.com

HDH_PIF 32000-1.0 DS.REV.1.0

30.08.2011.

CONFIGURATION PARAMETERS:

• eVC can be configured to work as a MASTER or as a SLAVE• ACTIVE/PASSIVE• Enable (disable) write responses • Data bus width• Number of outstanding reads• Number of outstanding writes• Slave can be configures as RAM

MASTER TRANSACTIONFields of master transaction:• Type of transaction (single data read/write, block- read/write and read-conditional-write)• Byte enable• Address• Data (for write or block-write)• Error injection: capability to sent address that is not aligned to the byte enables• ID• Priority (Xtensa-the processor always issues transaction requests at medium-hight priority,

level 0x2, and ignores the priority bits of PIF responses)• ReqRdy – is (not) asserted in the same cycle as a single data read/write request• Back-to-back write requests during successive cycles• Drop write request • Block length - number of transfers (2,4,8,16) for block-read/write transactions

Figure1. HDH PIF 32000 eVC Architecture

HDH PIF 32000 - Solution for theverification of PIF-based systems

HDL Design House, Golsvortijeva 35, Belgrade, Serbia

Phone: +381 11 414 55 55 Fax: +381 11 414 55 59 Email: info@hdl-dh.com On-line: http://www.hdl-dh.com

HDH_PIF 32000-1.0 DS.REV.1.0

30.08.2011.

SLAVE RESPONSE

Slave response can be configured with these parameters:• Data (response for read operation)• ReqRdy• Address bus error• Data bus error• RespRdy – is (not) asserted during the same cycle as a single data read/write response• Number of cycles for delayed response• Idle cycles - inserted in the middle of the block-read response

Deliverables. e Core files with database of predefined sequences. Examples of different configurations of eVC and testbench. Documentation: Comprehensive User Guide. Online Support Service: Fast bug fixing,general problem solving and direct interaction with product’s development team

. Training on demand

HDL Design House Representatives

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Contact Information

HDL Design House

Golsvortijeva 35,

Belgrade, Serbia

Phone: +381 11 414 55 55

Fax: +381 11 414 55 59

Email: info@hdl-dh.com

http://www.hdl-dh.com

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