hd4004 pspi manufacturing, integration and cpi qualification
TRANSCRIPT
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HD4004 PSPI Manufacturing, HD4004 PSPI Manufacturing, Integration and CPI Integration and CPI
QualificationQualificationRich VolantRich Volant
Tim Daubenspeck, Yutong Wu,Tim Daubenspeck, Yutong Wu,Ken Davis, Leo Tai, Ken Davis, Leo Tai, Tang Teck Jung,
Leong Chee Kong
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Scope and ObjectiveScope and Objective
Qualification and implementation of a negative Qualification and implementation of a negative tone photosensitive polyimide (PSPI) as a tone photosensitive polyimide (PSPI) as a universal passivation in 300mm wafer fabsuniversal passivation in 300mm wafer fabsThis This ““universaluniversal”” process will generate significant process will generate significant time and cost savings, will improve yield and time and cost savings, will improve yield and reliability, and reliability, and can be extended to future can be extended to future technologies.technologies.Transfer of process/technology to second Transfer of process/technology to second 300mm fab 300mm fab -- Chartered Semiconductor Fab 7Chartered Semiconductor Fab 7
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Representative Ceramic Package Representative Ceramic Package –– Purpose of PolyimidePurpose of Polyimide
97/3 Pb/Sn C-4 Solder
Balls
AluminumHeatsink / Cap
Silicon Chip
Alumina Substrate Module
CTE= 2.6 x 10 -6 /C
Alumina substrateCTE= 6.5 x 10 -6 /C
CTE= 23 x 10 -6 /C
Epoxy UnderfillCTE= 25-30 x 10 -6 /C
CTE= 29 x 10 -6 /C
Epoxy/Glass BoardCTE= 16 - 20 x 10 -6 /C
(Can join substrate toboard by LGA, BGA, CGA)
Polyimide / PSPI
CTE= 35 x 10 -6 /C
Insulates chip
Planarization and package interface
Damage protection
CPI Stress buffer.
5878 G has been our staple since about 1972
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HD4004 Material Properties HD4004 Material Properties –– ““UniversalUniversal””
Why is HD4004 universal?Why is HD4004 universal?Can be used for bumping and wirebond Can be used for bumping and wirebond applicationsapplicationsMultiple substrates Multiple substrates –– organic and ceramicorganic and ceramic
Photosensitive Polyimide (PSPI)Photosensitive Polyimide (PSPI)Good adhesion to wafer and package level filmsGood adhesion to wafer and package level films
Negative toneNegative toneHigh Tg (350 C) High Tg (350 C) -- good for bumping applicationsgood for bumping applicationsSmall feature patterning capability for wirebondSmall feature patterning capability for wirebond
Resistant to copper migrationResistant to copper migrationCTE = 33 ppmCTE = 33 ppm
Tensile = 200 MPaTensile = 200 MPaElongation = 50%Elongation = 50%
Modulus = 3.5 GpaModulus = 3.5 Gpa
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HD4004 Benefits in Manufacturing HD4004 Benefits in Manufacturing –– Fewer Processes, Less CostFewer Processes, Less Cost
5878
HD4004
Polyimide
Apply
Wet
Operation
Resist Apply
& ExposeDevelop
Resist
Strip
Second
Develop
Final
CurePre Cure
PSPI
ApplyExpose Develop
Final
Cure
•Realized process time savings
•Direct cost savings
HD4004 PSPIHD4004 PSPI4 operations4 operations4 chemicals4 chemicals3 tools3 tools10 hours raw 10 hours raw process timeprocess time11--2% rework2% rework
587858788 operations8 operations10 chemicals10 chemicals5 tools5 tools
•• 14 hours raw 14 hours raw process timeprocess time
••55--10% rework10% rework
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Problems with 5878 (GPOLY) Problems with 5878 (GPOLY) not seen with PSPInot seen with PSPI
Adhesion failure Adhesion failure –– PSPI is selfPSPI is self--priming and does not require priming and does not require an adhesion promoter such as A1100an adhesion promoter such as A1100Underdeveloped polyimide/residuals in kerf Underdeveloped polyimide/residuals in kerf –– PSPI is a negative PSPI is a negative tone polyimide with a much larger wet etch process window. tone polyimide with a much larger wet etch process window. Gpoly uses a positiveGpoly uses a positive--tone resist.tone resist.Overdeveloped vias Overdeveloped vias –– with the larger wet etch process with the larger wet etch process window, the kerf will be cleared w/o sacrificing CD design window, the kerf will be cleared w/o sacrificing CD design rulesrulesCD CenterCD Center--toto--edge and lotedge and lot--toto--lot variation lot variation –– once again, the once again, the larger process window provides a more stable process with larger process window provides a more stable process with PSPIPSPIRaw Process Time Raw Process Time –– PSPI has fewer operations, reducing PSPI has fewer operations, reducing
RPT by 30%RPT by 30%
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Package TypesPackage Types
Ceramic FC-PBGAFC-PBGA HP
polyimide
EPBGA WB
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HD4K Photosensitive Polyimide HD4K Photosensitive Polyimide (PSPI) Qualification(PSPI) Qualification
““T0T0”” -- Feasibility Checkpoint Feasibility Checkpoint Material performanceMaterial performancePreliminary packaging evaluationPreliminary packaging evaluation
““T1T1”” -- Technology / Manufacturability CheckpointTechnology / Manufacturability CheckpointReliability qualification for chip and packageReliability qualification for chip and packageCostly, resource intensive, and time consumingCostly, resource intensive, and time consuming
***Must cover all products and technologies******Must cover all products and technologies***
Objective: Implement HD4004 upon completion of all T1 itemsObjective: Implement HD4004 upon completion of all T1 items
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130nm technology
C4Wirebond
FCPBGA Ceramic Hyper BGAEPBGAHPBGA
High Pb Pb reduced Pb free
Thick Laminate Thin Laminate
4 on 8 Pitch 3 on 6 Pitch
High Pb Pb reduced Pb free
130nm technology
FCPBGA Ceramic
C4Wirebond
Thick Laminate Thin Laminate
Hyper BGA
4 on 8 Pitch 3 on 6 Pitch
EPBGAHPBGA
Large ChipSmall Chip
Underfill BUnderfill A
BLM 2BLM 1
High Pb Pb reduced Pb free
90nm technology
FCPBGA Ceramic
C4Wirebond
Thick Laminate Thin Lamina
H
4 on 8 Pitch 3 on 6 Pitch
EPBGAHPBGA
Large ChipSmall Chip
UndUnderfill A
BLM 2BLM A
Expansion of CPI workExpansion of CPI work
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Technical ChallengesTechnical Challenges
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PSPI Lithographic Performance CriteriaPSPI Lithographic Performance CriteriaC4 RequirementsC4 Requirements
Smooth, tapered (<70 deg) PI via slope for BLM or UBM coverageSmooth, tapered (<70 deg) PI via slope for BLM or UBM coverageTypical via size range; ~47Typical via size range; ~47-- 70 um diameter70 um diameter
••smaller openings ~20 um for support structures e.g. fusebayssmaller openings ~20 um for support structures e.g. fusebays••+/+/-- 11--2 um 3sig image size tolerance 2 um 3sig image size tolerance
MidMid--term 3 on 6 C4 pitch objectiveterm 3 on 6 C4 pitch objective••requires improved via size control, reduced tolerancerequires improved via size control, reduced tolerance••smaller C4 w/ larger via size for performancesmaller C4 w/ larger via size for performance••BLM must always cover via openingBLM must always cover via opening
Wirebond RequirementsWirebond RequirementsMinimum Minimum ““webweb”” structure width down to 4 umstructure width down to 4 umconsistent w/consistent w/””roadmaproadmap””
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Dimensional Characterization: TopDimensional Characterization: Top--DownDown (Chartered)(Chartered)
OpticalOpticalTopTop
OpticalOpticalBottomBottom
OpticalOpticalFootFoot
SEMSEMTopTop
SEMSEMBottomBottom
SEMSEMFootFoot
Post DevPost Dev 5252 4747 4545 NANA NANA NANA
Post Post CureCure
5252 4747 4444 5252 4949 4444
Post Post Cure & Cure & CleanClean
5353 4848 NANA 5454 5050 4545
• Variability & detectability of foot creates measurement standardization issues
- Coating, dev. & post-dev. processing affect foot size- Foot size variable across wafer for a given process- SEM more sensitive to foot than optical
• Careful standardization of measurement methodology across products & fabs required.
Top-Down Image
CD Measurements
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Dimensional Characterization: CrossDimensional Characterization: Cross--SectionSection (Chartered)(Chartered)
• Sidewall Angle: +/-15 deg depending on how you measure• PSPI Thickness: Varies with underlying topography• Via Size:
- Via Top vs Bottom (Foot difficult to quantify)
Center Edge
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Integration Difficulties in Integration Difficulties in Manufacturing Manufacturing –– Sidewall SlopeSidewall Slope
Steep Slope Fix
1) Optimized post apply bake (PAB) temperature
2) Decreased PAB time
3) Increased expose focus
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Integration Difficulties in Integration Difficulties in Manufacturing Manufacturing –– Pinched CornerPinched Corner
Pinched Corner Fix
1) Increased post develop bake (PDB) temperature
2) Increased PDB time
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Indirect Process/Integration SensitivitiesIndirect Process/Integration Sensitivities (Chartered)(Chartered)
Develop Stability HillocksSurface Ionics vs Process
Acceptable POR
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Tech TransferTech Transfer
Fab 7 using different developerFab 7 using different developerFab 7 using integrated exposure / track Fab 7 using integrated exposure / track
Enables use of post expose bake to stabilize Enables use of post expose bake to stabilize imageimage
IBM using nonIBM using non--integrated exposure / trackintegrated exposure / trackRequires minimum delay of 45 min. between Requires minimum delay of 45 min. between expose and develop and maximum delay of 4 expose and develop and maximum delay of 4 hours.hours.
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Implementation TasksImplementation Tasks•• Mask order Mask order –– reverse polarity from original Gpoly reverse polarity from original Gpoly
processprocess•• Part number / EC setup in systemPart number / EC setup in system•• Wafers for mask verification and xWafers for mask verification and x--section for slopesection for slope
•• Process engineer, litho team Process engineer, litho team •• Stepper files setup w/laser scribe changeStepper files setup w/laser scribe change
•• Litho teamLitho team•• Route update for relevel to new part number Route update for relevel to new part number ––
material managementmaterial management•• Releveling coordination with production groupReleveling coordination with production group
•• Includes quarterly demands and inhibits to control hardware.Includes quarterly demands and inhibits to control hardware.•• Communication with C4 and outgoing quality teamsCommunication with C4 and outgoing quality teams•• Coordination with customers and bump vendorsCoordination with customers and bump vendors
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Package/CPackage/C PI QualPI Qual
TechTech BEOLBEOL B&A B&A LocationLocation
B&A ConditionB&A Condition I/O PitchI/O Pitch BLMBLM StatusStatus
WirebondWirebondEPBGAEPBGAHPBGAHPBGA
130nm130nm FTEOSFTEOS InternalInternalExternalExternal
PbReduced laminatePbReduced laminate 5050--55 um55 um8 um web8 um web
N/AN/A T1 1Q04T1 1Q04Implementation 1Q04Implementation 1Q04(complete)(complete)
WirebondWirebondEPBGAEPBGAHPBGAHPBGA
90 nm90 nm LowK LowK InternalInternalExternalExternal
PbReduced laminatePbReduced laminate 5050--55 um55 um8 um web8 um web
N/AN/A Implementation 1Q04Implementation 1Q04Technology T1 3Q04Technology T1 3Q04completedcompleted
CeramicCeramicSCM&MCMSCM&MCM
130 nm130 nm FTEOSFTEOS InternalInternal PbReduced laminate;PbReduced laminate;Leaded; PbFree C4Leaded; PbFree C4
4 on 8 mil4 on 8 mil stdstd completecomplete
Ceramic Ceramic SCM&MCMSCM&MCM
90 nm90 nm LowKLowK InternalInternal PbReduced laminate; PbReduced laminate; Leaded; PbFree C4Leaded; PbFree C4
4 on 8 mil4 on 8 mil stdstdcompletecomplete
HyperBGAHyperBGA 130 nm130 nm FTEOSFTEOS InternalInternal PbReduced laminate; PbReduced laminate; Leaded, PbFree C4Leaded, PbFree C4
4 on 8 mil4 on 8 mil stdstd completecomplete
FCPBGAFCPBGAThin/thickThin/thick
130 nm130 nm FTEOSFTEOS InternalInternalExternalExternal
PbReduced laminate;PbReduced laminate;Leaded; PbFree C4Leaded; PbFree C4
4 on 8 mil4 on 8 mil stdstdadvadv completecomplete
FCPBGAFCPBGAThin/thickThin/thick
90 nm 90 nm LowKLowK InternalInternalExternalExternal
PbReduced laminate; PbReduced laminate; Leaded; PbFree C4Leaded; PbFree C4
4 on 8 mil4 on 8 mil stdstdadvadv
completecomplete
All Existing All Existing CustomersCustomers
130 nm130 nm FTEOSFTEOS InternalInternalExternalExternal
PbReduced laminate;PbReduced laminate;Leaded C4Leaded C4
4 on 8 mil4 on 8 mil stdstd completecomplete
Results and conclusionsResults and conclusions Packaging/CPI Qualification Matrix Packaging/CPI Qualification Matrix
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Results and conclusionsResults and conclusions
Wide process window provides for a very Wide process window provides for a very stable product stable product
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Focus WindowFocus Window
F=12.0um
F=-4.0um
F=-8.0um
F=-12.0um
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Dimensional ControlDimensional Control
ExampleExampleAverage size of via in center of wafer = Average size of via in center of wafer = 41.55um41.55umAverage size of via at edge of wafer = Average size of via at edge of wafer = 41.48um41.48um
Lot to lot variation less than 5% Lot to lot variation less than 5% 5878 could be over 15%5878 could be over 15%
3um tabs resolved on wirebond webs3um tabs resolved on wirebond webs
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Results and conclusionsResults and conclusions
Technology transfer demonstrated despite Technology transfer demonstrated despite differences in process flows and toolingdifferences in process flows and toolingChartered Fab 7 fully qualified for Chartered Fab 7 fully qualified for production production
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Tech TransferTech TransferIBM Process SetupIBM Process Setup Fab7 Process SetupFab7 Process Setup
Chemical MaterialsChemical MaterialsPSPI: HD4004, 1588 cSt (cover 8um and PSPI: HD4004, 1588 cSt (cover 8um and
11um)11um)Developer: QZ3501: GBL70%, NBA 30%Developer: QZ3501: GBL70%, NBA 30%Rinse solvent: PGMEARinse solvent: PGMEABSR solvent: NMPBSR solvent: NMPBath rinse: NMPBath rinse: NMP
HD4004, 1588 cSt, (cover 8um and 11um)HD4004, 1588 cSt, (cover 8um and 11um)Developer: A515 (cyclopentanone )Developer: A515 (cyclopentanone )Rinse solvent: C260 (>95% PGMEA)Rinse solvent: C260 (>95% PGMEA)BSR solvent: A515BSR solvent: A515Bath rinse: A515Bath rinse: A515
Coating recipeCoating recipeACT12, one step static dispense.ACT12, one step static dispense.No EBR.No EBR.Thickness uniformity: std =<3%Thickness uniformity: std =<3%
M/C ID: LIPN701M/C ID: LIPN701Flow Recipe ID: LPYDV, LPYFVFlow Recipe ID: LPYDV, LPYFVACT12, one step static dispense.ACT12, one step static dispense.No EBRNo EBRThickness uniformity: std <3%Thickness uniformity: std <3%
ExposureExposureASML 400, scannerASML 400, scannerExposure dose /Focus: Exposure dose /Focus:
220mj/cm220mj/cm22, focus , focus --6um6um
Nikon SF100, stepperNikon SF100, stepperExposure dose /Focus:Exposure dose /Focus:
260mj/cm2, focus 260mj/cm2, focus --8um8um
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Reliability BenefitsReliability BenefitsFewer operations that can cause Fewer operations that can cause corrosioncorrosion
Polyimide adhesion promoter, develop Polyimide adhesion promoter, develop rinserinse
Tighter wiring for new technologiesTighter wiring for new technologies58% reduction in feature openings58% reduction in feature openings
Fewer misprocessed wafers with fewer Fewer misprocessed wafers with fewer operationsoperationsWider wet etch windowWider wet etch window
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SummarySummaryPolyimides are used for insulation, protection, and Polyimides are used for insulation, protection, and stress reliefstress reliefHD4004, a negative tone PSPI, is HD4004, a negative tone PSPI, is ““universaluniversal””
Used with multiple substrates and applicationsUsed with multiple substrates and applicationsThe high Tg, 350C, makes it a good material for bumping The high Tg, 350C, makes it a good material for bumping applicationsapplications
$ millions in savings from a reduction in operations, $ millions in savings from a reduction in operations, chemicals, process time, tools, floor space and reworkchemicals, process time, tools, floor space and reworkIntegrated into manufacturing after overcoming Integrated into manufacturing after overcoming material and sidewall profilesmaterial and sidewall profilesImproved reliability by eliminating corrosive Improved reliability by eliminating corrosive processing materials, reducing the number of processing materials, reducing the number of operations, and widening the process windowoperations, and widening the process windowT1 Qual complete on all productsT1 Qual complete on all productsSuccessful transfer of technology to Chartered FabSuccessful transfer of technology to Chartered Fab
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Acknowledgment
Anne Petrosky, Kim Larson, Spyridon Skordas, Jennifer Kelp, Bradley Jones, Vincent Chai,
Nitin Parbhoo, David Colon, Gerald Advocate