harry d. foster - stac research · 2017. 6. 5. · uvm •protocol expertise •reduces tb...

Harry D. Foster

Demystifying FPGA Design and Verification

Chief Scientist Verification

Design Verification Technology

June 5, 2017

© Mentor Graphics Corporation

THE ERA OF DIGITAL INTELLIGENCE


Everything Connected and in the Cloud

HF, Demystifying FPGA Design and Verification, STAC 20173

• Evans, CTO of Stringify, says 30 billion connected devices by 2020

• Ericsson figures on 28 billion by 2020

• HIS Markit projects 30.7 billion IoT devices by2020

• Cartner expects 20.8 billion by 2020

• IDC anticipates 28.1 billion by 2020


REALLY BIG DATA & FAST DATA


Advantages of FPGA-Based Accelerator PlatformsCompetitive Advantage Through Low Latency and Faster Compute

Source: A low-latency library in FPGA hardware for High-Frequency Trading (HFT),

2012 IEEE 20th Annual Symposium on High-Performance Interconnect



The Need to Shift LeftCharacteristics of Projects Who Meet or Exceed Schedule

Behind ScheduleAhead of schedule

Source: Wilson Research Group and Mentor Graphics, 2014 Functional Verification Study

H Foster, Honeywell, Sept 20166

0%

5%

10%

15%

20%

25%

30%

35%

40%

More than 10%EARLY

10% EARLY ON-SCHEDULE 10% BEHINDSCHEDULE

20% 30% 40% 50% >50% BEHINDSCHEDULE

FP

GA

De

sig

n P

roje

cts

Actual FPGA design project completion compared to project's original schedule

World 2012

World 2014

World 2016

2012: 67% behind schedule2014: 59% behind schedule2016: 65% behind schedule

6 HF, Demystifying FPGA Design and Verification, STAC 2017


The Need to Be GreenCharacteristics of Projects Without Bug Escapes



7

0%

5%

10%

15%

20%

25%

30%

35%

0 1 2 3 4 5 6 or More

De

sig

n P

roje

cts

2016 FPGA Non-Trivial Bug Escapes to Production

78% of FPGA design projectshave non-trivial bugs that



Flaws Contributing to FPGA Rework


* Multiple answers possible

0%

10%

20%

30%

40%

50%

60%

LOGIC ORFUNCTIONAL

CLOCKING TUNINGANALOGCIRCUIT

CROSSTALK POWERCONSUMPTION

MIXED-SIGNALINTERFACE

TIMING – PATH TOO SLOW

FIRMWARE TIMING – PATH TOO FAST

OTHER

De

sig

n P

roje

cts

Trends in Types of Flaws Resulting in Rework

2012

2014

2016




RISING VERIFICATION COMPLEXITY


The Emergence of New Layers of Verification Requirements Brought on by the System Era

La

ye

rs o

f R

eq

uir

em

en

ts

Clock Domains

Power Domains

Software Domains

Performance Domains

Functional Domains

Security / Safety Domains



Demand for Design Engineers Grows Slowly


0

2

4

6

8

10

12

2007 2010 2012 2014 2016

AS

IC/IC

Me

an

Pe

ak

Nu

mb

er

of

En

gin

ee

rs

Design Engineers

CAGR Designers 3.6%




But what about Verification Productivity?


0

2

4

6

8

10

12

2007 2010 2012 2014 2016

AS

IC/IC

Me

an

Pe

ak

Nu

mb

er

of

En

gin

ee

rs

Design Engineers

Verification Engineers

CAGR Designers 3.6% CAGR Verifiers 10.4%




About a 1-to-1 Ratio of FPGA Verification and Design Engineers


4.04.3 4.3

2.6

3.5 3.6

0

2

4

6

2012 2014 2016

FP

GA

Me

an

Pe

ak

Nu

mb

er

of

En

gin

ee

rs

Design Engineers

Verification Engineers

1.8% CAGR between 2012 and 2014 for FPGA design engineers

8.48% CAGR between 2012 and 2014 for FPGA verification engineers




What Makes Functional Verification Difficult?

14

Single, sequential data streams— Floating point unit— Graphics shading unit— DSP convolution unit — MPEG decode— . . .

Channel

Compressed

Audio

Data Link LayerTX

RX

PHY

Sequential data streams1x number of bugs

Concurrent data streams5x number of bugs

Encoder Decoder

Multiple, concurrent data streams— Cross bar— Bus traffic controller— DMA controller— Standard I/F (e.g., PCIe)— . . .

-Ted Scardamalia, internal IBM studyHF, Demystifying FPGA Design and Verification, STAC 2017


Packet-Based Design

Transaction

Layer Packet

Reformater

Data Link

Layer Packet

Reformater

Retry BufferArbiter

Tx

Rx

From

FabricTo

PHY

From Rx

Channel

Verifying Concurrency Requires Appropriate Solutions

H Foster, NC State, Spring 201715



Finding Corner Case Bugs Requires Appropriate Solutions

Constrained-random simulation finds the bugs

you never anticipated!

Directed-test-based simulation finds the bugs

you can think of…




VERIFICATION BEST PRACTICES


Simulation-Based Techniques

— Fundamental verification technique in use today— Generally scales well— Testing all possible states is generally incomplete


Simulation Testbench

DesignModel

GenerateStimulus

CheckResults

Measure Coverage

Assertions can be used to check results and measure coverage


18


FPGA Projects are Maturing their Verification Processes



0% 10% 20% 30% 40% 50% 60% 70%

Constrained-RandomSimulation

Functional coverage

Assertions

Code coverage

FPGA Design Projects

World 2012

World 2014

World 2016



FPGA Verification Technology Adoption and Bug EscapesData suggest organizations that are less mature in their verification processes experience more bugs



0% 10% 20% 30% 40% 50% 60% 70% 80%

Constrained-RandomSimulation

Functional coverage

Assertions

Code coverage

FPGA Design Projects

Bug Escapes

No Bug Escapes



Formal-Based Techniques

— Does not require a testbench or input stimulus!

— Automatically uses algorithms to verify the functionality

— Verification can be complete

— Complements simulation-based techniques


Pass?FormalTool

DesignModel

Assertions

DoneYes

No


21


FPGA Formal Technology Adoption Trends



0%

5%

10%

15%

20%

25%

Formal property checking Automatic formal verification

FP

GA

De

sig

n P

roje

cts

Static Verification Technique

World 2012

World 2014

World 2016



Proven Benefits from Advanced VerificationFPGA customers realize the benefits of evolving their verification methodologies

• Constrained random for better testing

• Functional coverage for better insight

• Assertions to improve debug efficiencySystemVerilog

• Enables benefits of SystemVerilog

• Provides consistent methodology

• Promotes reuse for productivity boostUVM

• Protocol expertise

• Reduces TB development effort

• Risk reductionVerification IP

23

FPGA Customer Success StoriesIncreased business due to shorter design cycles

400% ROI after adopting UVM and VIP

5 straight FPGA’s without a bug

Zero bugs found in lab since moving to UVM

Reduced expensive lab equipment

100x faster to debug vs lab



IMPROVING VERIFICATION SKILLS

www.verificationacadmy.com


The Most Comprehensive Verification Resource AroundFree Resource Available to You!

Online Courses

Verification Cookbooks

Discussion Forums

Patterns Library UVM Cookbook

Coverage Cookbook



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2009 2010 2011 2012 2013 2014 2015 2016 2017 (February)

Verification Academy Membership TrendFree Resource Available to You!



WWW.VERIFICATIONACADEMY.COM


Learn More About Mentor’s FPGA Design & Verification Tools and Solutions

Pete LaFauci, Senior Account Manager— [email protected]

Ted Lin, Technical Account Manager— [email protected]

Harry Foster, Chief Scientist Verification— [email protected]


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harry d. foster - stac research · 2017. 6. 5. · uvm •protocol expertise •reduces tb...

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