harmony-ams analog/mixed-signal simulator · 2015-09-08 · harmony-ams analog/mixed-signal...

7/15/04

Harmony-AMS Analog/Mixed-Signal Simulator

Yokohama, June 2004 Workshop

- 2 -Harmony-AMS Simulator

Challenges for a True Single-Kernel A/MS Simulator

ß Accurate partition of analog and digital circuit blocks

ß Simple communication definition between analog and digitalblocks

ß Correct initialization of analog and digital simulators

ß Synchronization between two simulators during run-time

ß Convergence

ß Single viewer that simultaneously displays any combinationof digital and analog signals

ß Industry-proven and accepted analog and digital simulatorfrom a single vendor

ß Lack of an AMS language standard that is complete,commonly agreed upon and widely accepted


Harmony-AMS Analog/Mixed-Signal Simulator withIntegrated AMS Viewer


Harmony-AMS Overview

ß Harmony-AMS is a mixed-signal design and verification solutionbased on analog simulator SmartSpice and the veteran Verilog(IEEE-1364-2001) simulator Silos.

ß Harmony-AMS provides a comprehensive environment thatenables design and verification of full-chip mixed-signal designswith built-in support for Verilog-AMS language defined by theAccellera 2.1 standard.

ß It provides a combination of accuracy, performance and capacitywith the flexibility of simulating design abstractions in anycombination of Verilog, SPICE, Verilog-A and Verilog-AMS

ß Harmony-AMS provides a platform for the transfer of analogdesigns from Gateway Schematic Editor, a complete graphicalanalog design environment supporting design creation andexploration including optimization.

ß Post layout analysis and verification, using back-annotation ofparasitic data, for DRC/LVS correct layout is accomplished usingSPRINT Transistor Level Simulator


Harmony-AMS Single Waveform Viewer

Data Tips in the Source Window display value, scope, and time of thehighlighted expression at the T1 marker in the Data Analyzer.


Harmony-AMS and SmartView for Complex Plots

Harmony-AMS can save vectors within any hierarchical subcircuit forSmartView graphical analysis including annotated eye diagram,

constellation, FFT analysis, and vector calculator


Interactive Debugging Environment

ß Interactive, interpreted Verilog-AMS environment provides a set ofmulti-tasking utilities to edit HDL source, set incremental breakpoints,stepping or timed simulation, real-time viewing, and error detection

ß Multi-window customizable Data Analyzer controls pan and zoom,timing markers, using interactive “drag & drop” capture, and displayfor signals and expressions for analog and digital waveforms

ß Trace Mode graphically traces all fan-in connections to any signalthrough all levels of circuit hierarchy instantly

ß Watch window displays or forces state values of specified signalsand variables while single-stepping—all set up through “drag & drop”for designer convenience

ß Interactive Source Code Editor displays line numbers for stop, start,and breakpoints, Data Tips to view the values of analog and digitalvariables and expressions, and Verilog code coverage information


Communication System using DPLL for SystemClock Recovery


Digital (Verilog-D)

Analog (SPICE + Verilog-A)

Digital Phase Lock Loop for System Clock Recovery


DPLL

ß First pass of the DPLL is all in Verilog-AMS

ß All modules are represented in behavioral form


XOR - PD

D_clock

LPF_in

VDD/2

VDD

p/2 p


LPF_in

LPF_out

Low Pass Filter (LPF)


VCO


Divide By N Circuit


PLL


TestBench


Harmony-AMS Single Window Environment


DPLL

ß Second pass of the DPLL is all in Verilog-AMS except VCOis now a SPICE netlist


VCO


VCO -Subcircuit


VCO Netlist


Harmony-AMS Single Kernel Simulator

ß Third pass of the DPLL is an architectural change with aVerilog-D Phase Frequency Detector and a analog netlistfor a charge pump.



DEMONSTRATION


Summary

ß Single-kernel engine provides optimal co-simulation initialization,synchronization, convergence, and accuracy

ß Single parser reads Verilog, SPICE, Verilog-A and Verilog-AMS inputdecks and testbench descriptions to automatically partition design atcorrect level

ß Single window viewing and plotting for both analog and digitalwaveforms

ß Compliant with Accellera 2.1 standard for Verilog-AMS and Verilog-A, IEEE 1364-2001 standard for Verilog-D and ProgrammingLanguage Interface (PLI), and HSPICE™ netlist/command

ß Provides the most accurate circuit simulation results and robustconvergence for critical mixed-signal designs

ß Productive debugging environment with graphic data analyzer, tracemode, hierarchy explorer, and interactive source code editor

ß Efficient use of CPU resources optimizes run-time performance

harmony-ams analog/mixed-signal simulator · 2015-09-08 · harmony-ams analog/mixed-signal...

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