hardware simulator

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Slide 1/49HW Simulator Tutorial Tutorial Indexwww.idc.ac.il/tecs

This program is part of the software suitethat accompanies the book

The Elements of Computing Systems

by Noam Nisan and Shimon Schocken

MIT Press

www.idc.ac.il/tecs

This software was developed by students at the

Efi Arazi School of Computer Science at IDC

Chief Software Architect: Yaron Ukrainitz

Hardware Simulator Tutorial
http://www.idc.ac.il/tecshttp://www.idc.ac.il/tecs


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Background

The Elements of Computing Systemsevolves aroundthe construction of a complete computer system,done in the framework of a 1- or 2-semester course.

In the first part of the book/course, we build the

hardware platform of a simple yet powerfulcomputer, called Hack. In the second part, we buildthe computers software hierarchy, consisting of anassembler, a virtual machine, a simple Java-likelanguage called Jack, a compiler for it, and a mini

operating system, written in Jack.The book/course is completely self-contained,requiring only programming as a pre-requisite.

The books web site includes some 200 test

programs, test scripts, and all the softwaretools necessary for doing all the projects.


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The books software suite

This tutorial isabout thehardware

simulator. Translators (Assembl er ,J ackCompi l er ):

Used to translate from high-level to low-level;

Developed by the students, using the booksspecs; Executable solutions supplied by us.

Other

Bi n: simulators and translators software;

bui l t I n: executable versions of all the logic

gates and chips mentioned in the book;

OS: executable version of the J ack OS;

Text Compar er : a text comparison utility.

(All the supplied tools are dual-platform: Xxx. bat startsXxx in Windows, and Xxx. sh starts it in Unix)

Simulators(HardwareSi mul at or , CPUEmul at or , VMEmul at or ):

Used to build hardware platforms andexecute programs;

Supplied by us.


4/43Slide 4/49HW Simulator Tutorial Tutorial Indexwww.idc.ac.il/tecs

The Hack computer

The hardware simulator described in this

tutorial can be used to build and test manydifferent hardware platforms. In this book, wefocus on one particular computer, called Hack.

Hack -- a 16-bit computer equipped with ascreen and a keyboard -- resembles hand-held

computers like game machines, PDAs, andcellular telephones.

The first 5 chapters of the book specify theelementary gates, combinational chips,sequential chips, and hardware architecture of

the Hack computer.All these modules can be built and tested usingthe hardware simulator described in thistutorial.

That is how hardware engineers build chips

for real: first, the hardware s designed,tested, and optimized on a softwaresimulator. Only then, the resultinggate logic is committed to silicon.



Hardware Simulation Tutorial

I. Getting started

II. Test scripts

III. Built-in chips

IV. Clocked chips

V. GUI-empowered chips

VI. Debugging tools

VII.The Hack Platform

Relevant reading (from The Elements of Computing Systems):

Chapter 1: Boolean Logic

Appendix A: Hardware Description Language

Appendix B: Test Scripting Language




Part I:

Getting Started



/ ** Excl usi ve- or gat e. out = a xor b */CHI P Xor {

I N a, b;

OUT out ;

/ / I mpl ement at i on mi ssi ng.}


I N a, b;

OUT out ;

/ / I mpl ement at i on mi ssi ng.}

Chip interface:

Chip Definition (. hdl file)

Name of the chip

Names of its input and output pins

Documentation of the intended chip operation

Typically supplied by the chip architect; similar to an API, or a contract.

chipinterface




I N a, b;

OUT out ;

PARTS:Not ( i n=a, out =not a) ;

Not ( i n=b, out =not b) ;

And( a=a, b=not b, out =w1) ;

And( a=not a, b=b, out =w2) ;Or ( a=w1, b=w2, out =out ) ;

}


I N a, b;

OUT out ;

PARTS:Not ( i n=a, out =not a) ;

Not ( i n=b, out =not b) ;

And( a=a, b=not b, out =w1) ;

And( a=not a, b=b, out =w2) ;

Or ( a=w1, b=w2, out =out ) ;

}

Any given chip can be implemented in several different ways. This particular

implementation is based on: Xor(a,b) = Or(And(a,Not(b)), And(b,Not(a)))

Not , And, Or : Internal parts (previously built chips), invoked by the HDL

programmer

not a, not b, w1, w2: internal pins, created and named by the HDL programmer;used to connect internal parts.

chipimplementation

chipinterface

Chip Definition (. hdl file)


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Loading a Chip

Navigate to adirectory and selectan . hdl file.


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Loading a Chip

Names and current valuesof the chips input pins;

To change their values,

enter the new valueshere.

Read-only view of the loaded . hdl file;

Defines the chip logic;

To edit it, use an external text editor.

Names and currentvalues of the chips

output pins; Calculated by the

simulator; read-only.

Names and current values ofthe chips internal pins(used to connect the chipsparts, forming the chips logic);

Calculated by the simulator;read-only.


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Exploring the Chip Logic

1. Click thePARTS

keyword

2. A table pops up, showing the chips internalparts (lower-level chips) and whether they are:

Primitive (given) or composite (user-defined)

Clocked (sequential) or unclocked (combinational)


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1. Click any one ofthe chip PARTS

2. A table pops up, showing theinput/output pins of the selectedpart (actually, its API), and theircurrent values;

A convenient debugging tool.

Exploring the Chip Logic


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Interactive Chip Testing

1. User: changes the values of someinput pins

2. Simulator: responds by:

Darkening the output and internal

pins, to indicate that the displayedvalues are no longer valid

Enabling the eval(calculator-shaped) button.

Re-

calc

3. User: Clicked the eval button

4. Simulator: re-calculates the valuesof the chips internal and output

pins (i.e. applies the chip logic tothe new input values)

5. To continue interactive testing,enter new values into the inputpins and click the eval button.


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Part II:

Test Scripts


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Test Scripts

l oad Xor . hdl ,

out put - f i l e Xor . out ,compar e- t o Xor . cmp,out put - l i st a%B3. 1. 3

b%B3. 1. 3out %B3. 1. 3;

set a 0,set b 0,eval ,out put ;

set a 0,set b 1,eval ,out put ;Et c.

l oad Xor . hdl ,out put - f i l e Xor . out ,compare- t o Xor . cmp,out put - l i st a%B3. 1. 3

b%B3. 1. 3out %B3. 1. 3;

set a 0,set b 0,eval ,out put ;

set a 0,set b 1,eval ,out put ;Et c.

If the script specifies a compare file, thesimulator will compare the . out file tothe . cmp file, line by line.

| a | b | out || 0 | 0 | 0 || 0 | 1 | 1 || 1 | 0 | 1 || 1 | 1 | 0 |

| a | b | out || 0 | 0 | 0 || 0 | 1 | 1 || 1 | 0 | 1 |

| 1 | 1 | 0 |

Generatedoutput file(Xor . out )

Init

Simulation step

Simulation step

Test scripts:

Are used for specifying, automating andreplicating chip testing

Are supplied for every chip mentioned in

the book (so you dont have to write them) Can effect, batch-style, any operation that

can be done interactively

Are written in a simple language describedin Appendix B of the book

Can create an output file that records theresults of the chip test


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Loading a Script

To load a new script (. t s t

file), click this button;

Interactive loading of the chipitself (. hdl file) may not be

necessary, since the test

script typically contains aload chipcommand.

S i C l


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Script Controls

Executes the nextsimulation step

Multi-step execution,until a pause

Pauses thescript execution

Resetsthe script

Controlsthe script

executionspeed Script =

series ofsimulationsteps, each

ending witha semicolon.

R i S i t


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Running a Script

Typical initcode:

1. Loads a chip definition (. hdl ) file

2. Initializes an output (. out ) file

3. Specifies a compare (. cmp) file

4. Declares an output line format.

Scriptexec-

utionflow

R i S i t


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Scriptexec-ution

ends

Running a Script

Comparison of the output lines tothe lines of the . cmp file are

reported.

Vie ing Output and Compare Files


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Conclusion: the chip logic(Xor . hdl ) is apparently

correct (but not necessarilyefficient).

Observation:This output file

looks like a Xortruth table

Viewing Output and Compare Files



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Part III:

Built-in Chips

Built In Chips


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Built-In Chips

General

A built-in chip has an HDL interface and a J avaimplementation (e.g. here: Mux16. cl ass )

The name of the J ava class is specified followingthe BUI LTI Nkeyword

Built-In implementations of all the chips thatappear in he book are supplied in thet ool s/ bui t I n directory.

/ / Mux16 gat e ( exampl e)CHI P Mux16 {

I N a[ 16] , b[ 16] , sel ;

OUT out [ 16] ;

BUI LTI N Mux16;

}

/ / Mux16 gat e ( exampl e)CHI P Mux16 {

I N a[ 16] , b[ 16] , sel ;

OUT out [ 16] ;

BUI LTI N Mux16;

}

Built-in chips are used to: Implement primitive gates (in the computer built in this book: Nand and DFF)

Implement chips that have peripheral side effects (like I/O devices)

Implement chips that feature a GUI (for debugging)

Provide the functionality of chips that the user did not implement for some reason

Improve simulation speed and save memory (when used as parts in complex chips)

Facilitate behavioral simulation of a chip before actually building it in HDL

Built-in chips can be used either explicitly, or implicitly.

Explicit Use of Built in Chips


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Explicit Use of Built-in Chips

The chip is loaded from thet ool s/ bui t I n directory (includes

executable versions of all the chipsmentioned in the book).

Built-in implementation.

Standard interface.

Implicit Use of Built in Chips


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Implicit Use of Built-in Chips

When any HDL file is loaded, the simulator parses its definition. For each internalchip Xxx( . . . ) mentioned in the PARTS section, the simulator looks for an Xxx. hdlfile in the same directory (e.g. Not . hdl , And. hdl , and Or . hdl in this example).

IfXxx. hdl is found in the current directory (e.g. if it was also written by the user), the

simulator uses its HDL logic in the evaluation of the overall chip. IfXxx. hdl is not found in the current directory, the simulator attempts to invoke the

file t ool s/ bui l t I n/ Xxx. hdl instead.

And since t ool s/ bui l t I n includes executable versions of all the chips mentioned in

the book, it is possible to build and test any of these chips before first building theirlower-level parts.

/ ** Excl usi ve- or gat e. out = a xor b */

CHI P Xor {I N a, b;

OUT out ;

PARTS:

Not ( i n=a, out =Not a) ;

Not ( i n=b, out =Not b) ;And( a=a, b=Not b, out =aNot b) ;

And( a=Not a, b=b, out =bNot a) ;

Or ( a=aNot b, b=bNot a, out =out ) ;

}

/ ** Excl usi ve- or gat e. out = a xor b */

CHI P Xor {I N a, b;

OUT out ;

PARTS:

Not ( i n=a, out =Not a) ;

Not ( i n=b, out =Not b) ;And( a=a, b=Not b, out =aNot b) ;

And( a=Not a, b=b, out =bNot a) ;

Or ( a=aNot b, b=bNot a, out =out ) ;

}



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Part IV:

Clocked Chips

(Sequential Logic)

Clocked (Sequential) Chips


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Clocked (Sequential) Chips

The implementation of clocked chips is based on sequential logic

The operation of clocked chips is regulated by a master clock signal:

In our jargon, a clock cycle =tick-phase (low), followed by a tock-phase (high)

During a tick-tock, the internal states of all the clocked chips are allowed to change,but their outputs are latched

At the beginning of the next tick, the outputs of all the clocked chips in thearchitecture commit to the new values

In a real computer, the clock is implemented by an oscillator; in simulators, clockcycles can be simulated either manually by the user, or repeatedly by a test script.

The D-Flip-Flop (DFF) Gate


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The D Flip Flop (DFF) Gate

Clocked chips

Clocked chips include registers,RAM devices, counters, andthe CPU

The simulator knows that the

loaded chip is clocked whenone or more of its pins isdeclared clocked, or one ormore of its parts (or sub-parts,

recursively) is a clocked chip In the hardware platform built in

the book, all the clocked chipsare based, directly or indirectly,

on (many instances of) built-inDFF gates.

/ ** Dat a Fl i p- f l op:

* out ( t ) =i n( t - 1)* wher e t i s t he t i me uni t .*/

CHI P DFF {I N i n;OUT out ;

BUI LTI N DFF;CLOCKED i n, out ;

}

/ ** Dat a Fl i p- f l op:

* out ( t ) =i n( t - 1)* wher e t i s t he t i me uni t .*/

CHI P DFF {I N i n;

OUT out ;

BUI LTI N DFF;CLOCKED i n, out ;

}

DFF:

A primitive memory gate that canremembera state over clock cycles

Can serve as the basic building block ofall the clocked chips in a computer.

Simulating Clocked Chips


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Since this built-in chip alsohappens to be GUI- empowered,the simulator displays its GUI

(More about GUI-empoweredchips, soon)


A built-in,clockedchip(RAM8) is

loaded

Clocked (sequential) chips are clock-regulated.

Therefore, the standard way to test a clocked chipis to set its input pins to some values (as withcombinational chips), simulate the progression ofthe clock, and watch how the chip logic respondsto the ticks and the tocks.

For example, consider the simulation of an 8-wordrandom-access memory chip (RAM8).



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4. Simulator:commits thechips output pinto the value of

the chipsinternal state.

3. User: clicks

the clock iconagain (tock)

A built-in,clockedchip(RAM8) is

loaded

1. User: enterssome input

values andclicks the clockicon once (tick)


2. Simulator:changes theinternal state ofthe chip, but note

that the chipsoutput pin is notyet effected.

Simulating Clocked Chips Using a Test Script


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Single-actiontick-tock

Tick-tocksrepeatedly andinfinitely

Controls the script

speed, and thus thesimulated clock speed,and thus the overallchip execution speed

Default script: always loaded whenthe simulator starts running;

The logic of the default script simply

runs the clock repeatedly;

Hence, executing the default scripthas the effect of causing the clockto go through an infinite train of ticsand tocks.

This, in turn, causes all the clockedchip parts of the loaded chip to reactto clock cycles, repeatedly.

g p g p



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Part V:GUI-Empowered

chips

Built-in Chips with GUI Effects


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2. If the loaded chip orsome of its parts have

GUI side-effects, thesimulator displays theGUIs here.

p

1. A chip whose

parts includebuilt-in chips

was loaded intothe simulator

(ignore the chiplogic for now)

GUI of the built-inScreen.hdl chip

GUI of the built-in

RAM16K.hdl chip

GUI of the built-inKeyboard.hdl chip

For each GUI-empowered built-in chip that appearsin the definition of the loaded chip, the simulator

does its best to put the chip GUI in this area.

The actual GUIs behaviors are then effected by theJ ava classes that implement the built-in chips.

The Logic of the GUIDemo Chip


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g p

/ / Demo of bui l t - i n chi ps wi t h GUI ef f ect sCHI P GUI Demo {

I N i n[ 16] , l oad, addr ess[ 15] ;

OUT out [ 16] ;

PARTS:RAM16K( i n=i n, l oad=l oad, addr ess=addr ess[ 0. . 13] , out =nul l ) ;

Scr een( i n=i n, l oad=l oad, addr ess=addr ess[ 0. . 12] , out =nul l ) ;

Keyboar d( out =nul l ) ;

}

/ / Demo of bui l t - i n chi ps wi t h GUI ef f ect sCHI P GUI Demo {

I N i n[ 16] , l oad, addr ess[ 15] ;

OUT out [ 16] ;

PARTS:

RAM16K( i n=i n, l oad=l oad, addr ess=addr ess[ 0. . 13] , out =nul l ) ;

Scr een( i n=i n, l oad=l oad, addr ess=addr ess[ 0. . 12] , out =nul l ) ;

Keyboar d( out =nul l ) ;

}

Effect: When the simulator evaluates this chip, it displays the GUI side-effects of its built-in chip parts

Chip logic:The only purpose of this demo chip is to force the simulator toshow the GUI of some built-in chips. Other than that, the chip logic ismeaningless: it simultaneously feeds the 16-bit data input (i n) into theRAM16Kand the Scr een chips, and it does nothing with the keyboard.

RAM16K,Scr een, &

Keyboardare built-inchips with GUIside-effects

GUIDemo Chip in Action


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1. User enters:

in = 1(=16 1s in binary)

address = 5012

load = 1

2. User:

runs theclock

3. 16 black

pixels are

drawnbeginning inrow = 156col = 320

3.The chip logic

routes the i n value

simultaneously intothe Scr een chip andthe RAM16Kchip

Explanation: According to the specification ofthe computer architecture described in thebook, the pixels of the physical screen are

continuously refreshed from an 8K RAM-resident memory map implemented by theScr een. hdl chip. The exact mapping

between this memory chip and the actualpixels is specified in Chapter 5. The refreshprocess is carried out by the simulator.



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Part VI:

Debugging tools

System Variables


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The simulator recognizes and maintains the following variables:

Time: the number of time-units (clock-cycles) that elapsed since the scriptstarted running is stored in the variable t i me

Pins: the values of all the input, output, and internal pins of the simulated chipare accessible as variables, using the names of the pins in the HDL code

GUI elements: the values stored in the states of GUI-empowered built-in chips

can be accessed via variables. For example, the value of register 3 of theRAM8 chip can be accessed via RAM8[ 3] .

All these variables can be used in scripts and breakpoints, for debugging.

Breakpoints


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The breakpoints logic:

Breakpoint = (variable, value)

When the specified variable in some

breakpoint reaches its specified value,the script pauses and a message isdisplayed

A powerful debugging tool.

1. Open thebreakpointspanel

2. Previously-declared

breakpoints

3. Add, delete,or updatebreakpoints

3. To update an existingbreakpoint, double-click it

Scripts for Testing the Topmost Comput er chip


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l oad Comput er . hdlROM32K l oad Max. hack,

out put - f i l e Comput er Max. out ,compare- t o Comput er Max. cmp,out put - l i st t i me%S1. 4. 1

r eset %B2. 1. 2ARegi st er [ ] %D1. 7. 1

DRegi st er [ ] %D1. 7. 1PC[ ] %D0. 4. 0RAM16K[ 0] %D1. 7. 1RAM16K[ 1] %D1. 7. 1RAM16K[ 2] %D1. 7. 1;

br eakpoi nt PC 10;

/ / Fi r st r un: comput e max( 3, 5)set RAM16K[ 0] 3,set RAM16K[ 1] 5,out put ;r epeat 14 {

t i ck, t ock, out put ;}/ / Reset t he PC ( pr epar i ng f or/ / second r un)set r eset 1,t i ck, t ock, out put ;

/ / E tc .cl ear - br eakpoi nt s;

l oad Comput er . hdlROM32K l oad Max. hack,

out put - f i l e Comput er Max. out ,compar e- t o Comput er Max. cmp,out put - l i st t i me%S1. 4. 1

r eset %B2. 1. 2ARegi st er [ ] %D1. 7. 1DRegi st er [ ] %D1. 7. 1PC[ ] %D0. 4. 0RAM16K[ 0] %D1. 7. 1RAM16K[ 1] %D1. 7. 1RAM16K[ 2] %D1. 7. 1;

br eakpoi nt PC 10;

/ / Fi r st r un: comput e max( 3, 5)set RAM16K[ 0] 3,set RAM16K[ 1] 5,out put ;r epeat 14 {

t i ck, t ock, out put ;

}/ / Reset t he PC ( pr epar i ng f or/ / second r un)set r eset 1,t i ck, t ock, out put ;/ / E tc .cl ear - br eakpoi nt s;

Scripts that test the CPUchip or theComput er chip described in the book usually

start by loading a machine-language program(. asmor . hack file) into the ROM32Kchip

The rest of the script typically uses variousfeatures like:

Output files

Loops

Breakpoints

Variables manipulation tick, tock

Etc.

All these features are described in Appendix

B of the book (Test Scripting Language).

Visual Options


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Script: displays thecurrent test script

Output: displays thegenerated output file

Compare: displaysthe suppliedcomparison file

Screen: displays theGUI effects of built-in

chips, if any.

Program flow: animates theflow of the currently loadedprogram

Program & data flow: animatesthe flow of the current program

and the data flow throughout theGUI elements displayed on thescreen

No animation (default):

program and data flow are not

animated. Tip: When running programs on

the CPUor Comput er chip, any

animation effects slow down thesimulation considerably.

Format of displayedpin values:

Decimal (default)

Hexadecimal

Binary



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Part VII:

The Hack

Hardware Platform

Hack: a General-Purpose 16-bit Computer


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Hang

ManMaze

PongGradesStats

Sample applications running on the Hack computer:

These programs (and many more) were written in the J ack programming language,

running in the J ack OS environment over the Hack hardware platform. The hardwareplatform is built in chapters 1-5, and the software hierarchy in chapters 6-12.

The Hack Chip-Set and Hardware Platform


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Elementary logic gates

(Project 1):

Nand (primitive)

Not

And

Or

Xor Mux

Dmux

Not 16

And16

Or 16

Mux16

Or 8Way

Mux4Way16

Mux8Way16

DMux4Way

DMux8Way

Combinational chips

(Project 2):

Hal f Adder

Ful l Adder

Add16

I nc16

ALU

Sequential chips

(Project 3):

DFF (primitive)

Bi t

Regi st er

RAM8

RAM64

RAM512

RAM4K

RAM16K

PC

Computer Architecture

(Project 5):

Memor y

CPU

Comput er

Most of these chips are generic, meaning that they can be

used in the construction of many different computers.

The Hack chip-set and hardware platform can be built usingthe hardware simulator, starting with primitive Nand. hdl and

DFF. hdl gates and culminating in the Comput er . hdl chip.

This construction is described in chapters 1,2,3,5 of the book,

and carried out in the respective projects.

Aside: H.D. Thoreau about chips, bugs, and close observation:


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I was surprised to find that the chips were covered

with such combatants, that it was not a duellum, but abellum, a war between two races of ants, the red alwayspitted against the black, and frequently two red ones toone black. The legions of these Myrmidons covered all

the hills and vales in my wood-yard, and the ground wasalready strewn with the dead and dying, both red andblack.

It was the only battle which I have ever witnessed, the only battlefield I

ever trod while the battle was raging; internecine war; the redrepublicans on the one hand, and the black imperialists on the other. Onevery side they were engaged in deadly combat, yet without any noisethat I could hear, and human soldiers never fought so resolutely.... Themore you think of it, the less the difference. And certainly there is notthe fight recorded in Concord history, at least, if in the history ofAmerica, that will bear a moments comparison with this, whether for thenumbers engaged in it, or for the patriotism and heroism displayed.

FromBrute Neighbors,

Walden (1854).

hardware simulator

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