hardware description language aula 4 -vhdl prof. afonso ferreira miguel, msc
TRANSCRIPT
![Page 1: Hardware Description Language Aula 4 -VHDL Prof. Afonso Ferreira Miguel, MSc](https://reader035.vdocuments.site/reader035/viewer/2022081502/552fc163497959413d8e9ed9/html5/thumbnails/1.jpg)
Hardware Description Language
Aula 4 -VHDL
Prof. Afonso Ferreira Miguel, MSc
![Page 2: Hardware Description Language Aula 4 -VHDL Prof. Afonso Ferreira Miguel, MSc](https://reader035.vdocuments.site/reader035/viewer/2022081502/552fc163497959413d8e9ed9/html5/thumbnails/2.jpg)
Data Objects
Inteiros e Vetores
![Page 3: Hardware Description Language Aula 4 -VHDL Prof. Afonso Ferreira Miguel, MSc](https://reader035.vdocuments.site/reader035/viewer/2022081502/552fc163497959413d8e9ed9/html5/thumbnails/3.jpg)
• Exercício 1Implementar uma memória ROM com um pino que
controle a saída (OE) para TRISTATE. Utilize os mesmos dados armazenados do slide anterior.
![Page 4: Hardware Description Language Aula 4 -VHDL Prof. Afonso Ferreira Miguel, MSc](https://reader035.vdocuments.site/reader035/viewer/2022081502/552fc163497959413d8e9ed9/html5/thumbnails/4.jpg)
• Exercício 2Implementar uma memória RAM com 3 bits de endereço e
4 bits de dados. Esta memória fica sempre habilitada (não tem CE) e escreverá um dado quando wr for para 1.
Completar
![Page 5: Hardware Description Language Aula 4 -VHDL Prof. Afonso Ferreira Miguel, MSc](https://reader035.vdocuments.site/reader035/viewer/2022081502/552fc163497959413d8e9ed9/html5/thumbnails/5.jpg)
Paralelismo de processos
Arquitetura
Processo 1
Processo 2
Processo 3
Processo 4
Processo 5
![Page 6: Hardware Description Language Aula 4 -VHDL Prof. Afonso Ferreira Miguel, MSc](https://reader035.vdocuments.site/reader035/viewer/2022081502/552fc163497959413d8e9ed9/html5/thumbnails/6.jpg)
Paralelismo de processos
Alterando A, os processos P1 e P2 são executados em paralelo
![Page 7: Hardware Description Language Aula 4 -VHDL Prof. Afonso Ferreira Miguel, MSc](https://reader035.vdocuments.site/reader035/viewer/2022081502/552fc163497959413d8e9ed9/html5/thumbnails/7.jpg)
Paralelismo de processos
Alterando B, os processos P1 e P3 são executados em paralelo
![Page 8: Hardware Description Language Aula 4 -VHDL Prof. Afonso Ferreira Miguel, MSc](https://reader035.vdocuments.site/reader035/viewer/2022081502/552fc163497959413d8e9ed9/html5/thumbnails/8.jpg)
Paralelismo de processos
Alterando C, apenas o processo P2 é executado
![Page 9: Hardware Description Language Aula 4 -VHDL Prof. Afonso Ferreira Miguel, MSc](https://reader035.vdocuments.site/reader035/viewer/2022081502/552fc163497959413d8e9ed9/html5/thumbnails/9.jpg)
Comunicação entre processos
Processo P1
Processo P2
Processo P3
![Page 10: Hardware Description Language Aula 4 -VHDL Prof. Afonso Ferreira Miguel, MSc](https://reader035.vdocuments.site/reader035/viewer/2022081502/552fc163497959413d8e9ed9/html5/thumbnails/10.jpg)
Comunicação entre processos
Processo P1
Processo P2
Processo P3
![Page 11: Hardware Description Language Aula 4 -VHDL Prof. Afonso Ferreira Miguel, MSc](https://reader035.vdocuments.site/reader035/viewer/2022081502/552fc163497959413d8e9ed9/html5/thumbnails/11.jpg)
Comunicação entre processos
Evento em A
Evento em D
Evento em E
![Page 12: Hardware Description Language Aula 4 -VHDL Prof. Afonso Ferreira Miguel, MSc](https://reader035.vdocuments.site/reader035/viewer/2022081502/552fc163497959413d8e9ed9/html5/thumbnails/12.jpg)
Comunicação entre processos
![Page 13: Hardware Description Language Aula 4 -VHDL Prof. Afonso Ferreira Miguel, MSc](https://reader035.vdocuments.site/reader035/viewer/2022081502/552fc163497959413d8e9ed9/html5/thumbnails/13.jpg)
Comunicação entre processos
Evento em D
![Page 14: Hardware Description Language Aula 4 -VHDL Prof. Afonso Ferreira Miguel, MSc](https://reader035.vdocuments.site/reader035/viewer/2022081502/552fc163497959413d8e9ed9/html5/thumbnails/14.jpg)
Comunicação entre processos
![Page 15: Hardware Description Language Aula 4 -VHDL Prof. Afonso Ferreira Miguel, MSc](https://reader035.vdocuments.site/reader035/viewer/2022081502/552fc163497959413d8e9ed9/html5/thumbnails/15.jpg)
• Exercício 3Modifique o exercício do Latch da aula anterior
para que utilize dois processos (proc1 e proc2) para controlar as funções do latch e da saída respectivamente. Utilize um signal (s) para comunicar dados entre os processos.
![Page 16: Hardware Description Language Aula 4 -VHDL Prof. Afonso Ferreira Miguel, MSc](https://reader035.vdocuments.site/reader035/viewer/2022081502/552fc163497959413d8e9ed9/html5/thumbnails/16.jpg)
Evitar processos desnecessários
![Page 17: Hardware Description Language Aula 4 -VHDL Prof. Afonso Ferreira Miguel, MSc](https://reader035.vdocuments.site/reader035/viewer/2022081502/552fc163497959413d8e9ed9/html5/thumbnails/17.jpg)
Outros atributosarray type or objects of the array type
![Page 18: Hardware Description Language Aula 4 -VHDL Prof. Afonso Ferreira Miguel, MSc](https://reader035.vdocuments.site/reader035/viewer/2022081502/552fc163497959413d8e9ed9/html5/thumbnails/18.jpg)
Outros atributosSignals attributes
![Page 19: Hardware Description Language Aula 4 -VHDL Prof. Afonso Ferreira Miguel, MSc](https://reader035.vdocuments.site/reader035/viewer/2022081502/552fc163497959413d8e9ed9/html5/thumbnails/19.jpg)
ContadoresContador Simples (UP – 3 bits - MOD 8)
Tipo inteiro, unsigned ou signed
![Page 20: Hardware Description Language Aula 4 -VHDL Prof. Afonso Ferreira Miguel, MSc](https://reader035.vdocuments.site/reader035/viewer/2022081502/552fc163497959413d8e9ed9/html5/thumbnails/20.jpg)
ContadoresContador Simples (UP – 3 bits - MOD 8)
O valor contado é incrementado e armazenado em uma variável do processo.
![Page 21: Hardware Description Language Aula 4 -VHDL Prof. Afonso Ferreira Miguel, MSc](https://reader035.vdocuments.site/reader035/viewer/2022081502/552fc163497959413d8e9ed9/html5/thumbnails/21.jpg)
ContadoresContador Simples (UP – 3 bits - MOD 8)
Neste exemplo, a ação de incremento é sensível a rampa ascendente.
![Page 22: Hardware Description Language Aula 4 -VHDL Prof. Afonso Ferreira Miguel, MSc](https://reader035.vdocuments.site/reader035/viewer/2022081502/552fc163497959413d8e9ed9/html5/thumbnails/22.jpg)
ContadoresContador com Reset (UP – 3 bits - MOD 8)
A variável de contagem é zerada ao receber um sinal de reset.
![Page 23: Hardware Description Language Aula 4 -VHDL Prof. Afonso Ferreira Miguel, MSc](https://reader035.vdocuments.site/reader035/viewer/2022081502/552fc163497959413d8e9ed9/html5/thumbnails/23.jpg)
ContadoresContador com Reset + Load (UP – 3 bits - MOD 8)
A entrada é carregada quando load vai para 1.
![Page 24: Hardware Description Language Aula 4 -VHDL Prof. Afonso Ferreira Miguel, MSc](https://reader035.vdocuments.site/reader035/viewer/2022081502/552fc163497959413d8e9ed9/html5/thumbnails/24.jpg)
ContadoresContador UP/DOWN – 3 bits - MOD 8
A variável de contagem é incrementada ou decrementada em função da entrada up_down.