harald deppe ee- asic holger flemming gsi event-driven tdc with 4 channels get4 harald deppe,...
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![Page 1: Harald Deppe EE- ASIC Holger Flemming GSI Event-driven TDC with 4 Channels GET4 Harald Deppe, EE-ASIC Holger Flemming, EE-ASIC](https://reader036.vdocuments.site/reader036/viewer/2022081516/551628b1550346c6758b4a40/html5/thumbnails/1.jpg)
Harald Deppe EE- ASIC
Holger Flemming
GSI Event-driven TDC with 4 Channels
GET4
Harald Deppe, EE-ASICHolger Flemming, EE-ASIC
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Harald Deppe EE- ASIC
Holger Flemming
Outline
• CBM Time of Flight Requirements
• The GET4 TDC Prototype
• First Measurement Results• Serial readout
• Differential Nonlinearity
• Time Resolution
• Summary and Outlook
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Harald Deppe EE- ASIC
Holger Flemming
Requirements for the CBM ToF
• Very high time resolution < 25ps
• Double hit resolution < 5ns
• Event rate up to 50 kHz per channel
• Capability to measure time over threshold
• Low power consumption with less than 30 mW per channel
• Number of Channels: ~ 65.000
• Triggerless operation: • Each event combined with a timestamp
• Epoche event on timestamp counter overflow
• Timestamp counters of all chips have to run synchronously
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Harald Deppe EE- ASIC
Holger Flemming
Schematic Overview of GET4 Prototype
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Harald Deppe EE- ASIC
Holger Flemming
GET4 Layout
Clock Distribution
Amplifier Vctrl
DLL
Bin Distribution
Channel 0&1
Channel 2&3
FiFo Channel 0&1
FiFo Channel 2&3
Serializer
Token Ring Controlller & Timestamp counter
Sync & Error FiFo
Full size prototype with 4 channels
• UMC 180nm process
• 1P6M layer
• 3240µm x 3240µm, 64 Bondpads
• Submitted in Oct. 2008
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Harald Deppe EE- ASIC
Holger Flemming
GET4 Prototype PCB
Bottom side view Top side view
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Harald Deppe EE- ASIC
Holger Flemming
Serial Data Transmission
• External Data Clock• For 50 kHz/Ch event rate
• => Min. Data Rate 10.5 MBit/s
• Asynchronous Data format• 1 Start Bit (Low)
• 24 Data Bits
• 1 Stop Bit (High)
• no Parity
• LVDS Clock input
• LVDS Serial Data Output
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Harald Deppe EE- ASIC
Holger Flemming
Serial Data Transmission
Serial Clock
Serial Data
Tested Data Rate: 312.5 MBit/s ~ 1.5 MHz/Ch Eventrate
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Harald Deppe EE- ASIC
Holger Flemming
Test Setup
GET4 TDC
DTG 5078
SMY2Signal Generator
Hit Signal Stimulus
156.25 MHz Clock
Spartan 3EEvaluation Board
Serial Data
Serial Clock
TLA 7012Logic Analyser
Parallel Data
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Harald Deppe EE- ASIC
Holger Flemming
Measurements and Results GET4
• Clock 156.25MHz
• Lock Range 110MHz – 165MHz
• Power consumption:• 27mW/Chan @ 150kHz event
rate
Vctrl vs. FrequenceGET4 V1.0 @ 1.8V core
0
200
400
600
800
1000
1200
1400
1600
1800
Frequence / MHz
Vc
trl
/mV
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Harald Deppe EE- ASIC
Holger Flemming
Measurements and Results GET4
• Linearity:• DNL < +/- 60 ps = +/- 1.2
LSB
• INL < +/- 80 ps = +/- 1.5 LSB
• In comparison to DANTE:• DNL: +/- 0.4 LSB
• INL: +/- 0.5 LSB
• Reasons for Nonlinearity are still under investigation
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Harald Deppe EE- ASIC
Holger Flemming
Test Setup: Hit Signal Stimulus
• Puls Width: 1.25 ns
• Synchronous Pulses on two channels
• Double Pulses, 3.75 ns puls spacing
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Harald Deppe EE- ASIC
Holger Flemming
Measurements and Results GET4
• Puls Width Measurements
• µ : 1.283 ns
• σ : 36.7 ps
• Uncorrelated Resolution: 25.9 ps
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Harald Deppe EE- ASIC
Holger Flemming
Measurements and Results GET4
• Time Difference
• σ : 29.1 ps
• Uncorrelated Resolution: 20.6 ps
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Harald Deppe EE- ASIC
Holger Flemming
Measurements and Results GET4
• Puls spacing Measurements
• µ : 3.766 ns
• σ : 33.5 ps
• Uncorrelated Resolution: 23.7 ps
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Harald Deppe EE- ASIC
Holger Flemming
Summary and Outlook
• First full scale TDC Prototype GET4 was submitted In Oct. 2008• Token ring readout and serialiser are fully operational
• DNL of TDC core worse than on DANTE test chip
• Time resolution: 20 ps … 25 ps
• Double hit resolution > 3.2 ns
• With GET4 a first TDC Prototype for ToF detector test is available
• Next Steps:• Investigation on reasons for nonlinearity
• Upgrading of Linearity => Improve the Resolution
• Slow control, etc.
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Harald Deppe EE- ASIC
Holger Flemming
Thanks......
• ...................... for your attention
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Harald Deppe EE- ASIC
Holger Flemming
Event Format
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Harald Deppe EE- ASIC
Holger Flemming
Timestamp Synchronization
• External Sync signal
• Synchronization on next leading edge of clock after leading edge of Sync signal
• Flagging of Epoche and Sync events