Half Adder

Sum = X’Y+XY’ = XY

Carry = XY

YXYXYX

YYYX XX

XOR

XNOR

Full Adder

SUM=

Carry Out=

Sequential Logic Circuits

CLCInput

Output

Comparison Between CLC & SLC

Unlike Combinational logic circuits that change state depending upon the

actual signals being applied to their inputs at that time, Sequential Logic

circuits have some form of inherent "Memory" built in to them and they are

able to take into account their previous input state as well as those actually

present a sort of "before" and "after" is involved.

They are generally termed as Two State or Bistable devices which can have their

output set in either of two basic states, a logic level "1" or a logic level "0" and will

remain "Latched" indefinitely in this current state or condition until some other

input signal or data is applied which will changes its state once again.

The word "Sequential" means that things happen in a "sequence", one after

another and in Sequential Logic circuits, the actual clock signal determines when

things will happen next.

Sequential Logic circuits can be divided into 3 main categories:

1. Clock Driven - Synchronous Circuits that are Synchronized to a specific clock signal.

2. Event Driven - Asynchronous Circuits that react or change state when an external

event occurs.

3. Pulse Driven - Which is a Combination of Synchronous and Asynchronous.

Simple sequential logic circuits can be constructed from standard Bistable circuits

such as Flip-flops. The term "Flip-flop" relates to the actual operation of the

device, as it can be "Flipped" into one logic state or "Flopped" back into another.

Flip Flops(Bistable Multivibrator)

RS Latch

Reset-Set (RS) Flip Flop

J-K Flip Flop

Toggle (T) Flip Flop

Data Storage (D) Flip Flop

The SR Latch

An SR Flip-Flop can be considered as a basic one-bit memory device that has

two inputs, one which will "SET" the device and another which will "RESET" the device

back to its original state and an output Q that will be either at a logic level "1" or logic

"0" depending upon this Set/Reset condition.

S R Q Q’ State

0 0 1 1 Invalid

0 1 1 0 Set

1 0 0 1 Reset

1 10 1 No Change (or)

Previous state1 0

S

R

Q

Q’

S

R

Q

Q’

Clocked SR Flip-Flop

S

CLK

R

Q

Q’

S

CLK

R

Q

Q’

N1

N2

N3

N4

CLK S R Q Q’ State

1 0 00 1 No Change (or)

Previous state1 01 0 1 0 1 Reset

1 1 0 1 0 Set

1 1 1 1 1 Invalid

The JK Flip-flop

J

CLK

K

Q

Q’

J

CLK

K

Q

Q’

N1

N2

N3

N4

CLK J K Q Q’ State

1 0 00 1 No Change (or)

Previous state1 0

1 0 1 0 1 Reset

1 1 0 1 0 Set

1 1 1 0 1 Toggle1 0

Q

Q’

J

CLK

K

D

The D & T Flip-flops

Q

Q’

J

CLK

K

T

CLK J K Q Q’ State

1 0 00 1 No Change (or)

Previous state1 0

D1 0 1 0 1 Reset

1 1 0 1 0 Set

T 1 1 1 0 1 Toggle1 0

Counters

Synchronous Pertaining to two or more processes that depend upon the

occurrence of specific events such as common timing signals.

counter A functional unit with a finite number of states each of which

represents a number that can be, upon receipt of an appropriate signal, increased by

unity or by a given constant.

So a "synchronous counter" is actually a functional unit with a certain number

of states, each representing a number which can be increased or decreased upon

receiving an appropriate signal (e.g. a rising edge pulse), and is usually used to count to,

or count down to zero from, a specified number N.

Synchronous counters Asynchronous counters

Synchronous counter

CLK Q4 Q3 Q2 Q1

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

….. ….. ….. ….. …..

14 1 1 1 0

15 1 1 1 1

Shift RegisterShift Registers are mainly used to store data and to convert data from

either a serial to parallel or parallel to serial format with all the latches being driven

by a common clock (Clk).

Shift Registers consists of a number of single bit "D-Type Data Latches"

connected together in a chain arrangement so that the output from one data latch

becomes the input of the next latch and so on, thereby moving the stored data

serially from either the left or the right direction.

Generally, Shift Registers operate in one of four different modes:

Serial-in to Parallel-out (SIPO)

Serial-in to Serial-out (SISO)

Parallel-in to Parallel-out (PIPO)

Parallel-in to Serial-out (PISO)

Serial-in to Parallel-out.

Clock Pulse No QA QB QC QD0 0 0 0 01 1 0 0 02 0 1 0 03 0 0 1 04 0 0 0 15 0 0 0 0

Serial-in to Serial-out

Parallel-in to Serial-out

Parallel-in to Parallel-out