gtl11 - jitter analysis

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© Eric Bogatin 2000

Slide -1

www.bogatinenterpr ises.com

MYTHS

Signal Integri ty:

Problems and Solut ions

Dr. Eric Bogatin

President

Bogatin Enterprises

www.BogatinEnterprises.com

(copies of the presentation are available for down load on th e web site)

Presented at Lock heed,

Sunn yvale, CA, March 1, 2000


Slide -2


MYTHS

Overview

• What is Signal Integrity?

• Why is it growing in importance?

• What can you do about it?




Slide -3


MYTHS

Signal Integri ty and

Interconnect Design

How the electrical properties of theinterconnects screw up the beautiful,

pristine signals from the chips


Slide -4


MYTHS

The Confus ing Mix o f Signal

Integr i ty Problems

LOSSY LINES

CROSSTALK

PARASITICS

EMI/EMC

GROUND BOUNCE

INDUCTANCE

EMISSIONS

TRANSMISSION LINESDELTA I NOISE

IR DROP

ATTENUATION

RC DELAY

POWER AND

GROUND DISTRIBUTION

CRITICAL NET

SIGNAL INTEGRITY

SKIN DEPTH

RETURN CURRENT PATH

STUB LENGTHS

TERMINATIONSCAPACITANCE

GAPS IN PLANES

REFLECTIONS

RINGING

LINE DELAY

UNDERSHOOT, OVERSHOOT DISPERSION

LOADED LINES

SUSCEPTABILITY

IMPEDANCE DISCONTINUITIES

NON-MONOTONIC EDGES




Slide -5


MYTHS The Four High Speed Problems

1. Signal quality of one net: reflections anddistortions from impedance discontinuitiesin the signal or return path

2. Cross talk between multiple nets: with idealreturn paths, and without (SSO)

3. Rail collapse in the power and grounddistribution network

4. EMI from a component or the system


Slide -6


MYTHS

Signal Qual ity o n One Net:

Distorted by the Interconnect

Initial output signal

Signal distorted

by interconnect

Simulated with Hyperlynx




Slide -7


MYTHS

Cross Talk Between Two A djacent

Condu ctors- Ideal Return Path

Near end

Far end

50ΩΩ

(HP 83480 High speed scope and TDR)

Active line

far end

Near end

The far end

noise is ~ 10x

larger than thenear end noise

rise time ~ 100 psec,TD ~ 1 nsec


Slide -8


MYTHS

On Chip

V SS

VCC

GND

15836

© 1991 Integrated Circuit Engineering Corporation

L Bonding

L BondingPower

commonlead

inductance

Conceptual Or ig in of SSO Noise

Icharge

Idischarge

Switching lines

Quiet data line




Slide -9


MYTHS

Simp le Example of Rai l

Col lapse

100 nF

Rail collapse:∆∆V ~ - dI/dt

Source: National Semiconductor

CdecouplingTo

regulator

Current On Current Off

Vdd nominal

Vdd rail collapse


Slide -10


MYTHS

Radiated Em ission s and

Power and Groun d Rout ing




Slide -11


MYTHS

Two Classes of

High Speed Problems

• Timing: setup, hold, propagation delay, skewü Scales with decreasing clock period

• Electrical Noise: signal integrity and EMIü Scales with decreasing rise time

dI

dt

dV

dt f, f 2


Slide -12


MYTHS

On Chip

V SS

VCC

GND

15836

© 1991 Integrated Circuit Engineering Corporation

L Bonding

L BondingPower

commonlead

inductance

“…it ’s the rise tim e, …”

Icharge

IdischargeSwitching data lines

Quiet data line

N = number of switching leads per ground leadsL = lead inductance or lead length

ττ = rise timeSSO noise ~

N x L

ττ




Slide -13


MYTHS

Shorter Delays Mean Sho rter Clock

Per iods, Higher Clock Frequencies

Digital Clock Frequencies are Increasing: doubling every 2 years!

1

10

100

1000

10000

1970 1975 1980 1985 1990 1995 2000

Introduction Year

C l o c k F r e q u e n c y ( M H z )

Clock fr equency of I ntel Processors

High speed usually refers to increasing cloc k frequency


Slide -14


MYTHS

Incr ease in Cloc k Frequenc ies

0

500

1000

1500

2000

2500

3000

3500

1996 1998 2000 2002 2004 2006 2008 2010 2012 2014

Year

C l o c k F r e q u e n c y ( M H z ) on-chip

on-board

Source: SIA Roadmap




Slide -15


MYTHS

Rise Times Are Loo sely

Related to Clock Frequency

0.01

0.1

1

10

100

1 10 100 1,000 10,000

Clock Frequency (MHz)

A p p r o x i m a t e R i s e T i m e ( n s e c )

clock F

1

10

1~τ

What is the consequence of high er speed?

10 nsec period

1 nsec rise time


Slide -16


MYTHS

The Driv ing Force Fuel ing th e

Electronics Revolut ion : Gate Leng th Feature Size Redu ctio n

50% reduction every 4 years




Slide -17


MYTHS

Transistors Swi tch Faster A s

Channel Length Shrinks

Shorter channel length means:

->> shorter delay

->> shorter rise time

in out

What can happen to the clock period and clock frequency?


Slide -18


MYTHS

Si tuat ion Analysis

• Clock frequency will get faster

• Rise times for every every chip will get shorter

• SI problems will be more significant

• Design cycle times will be decreasing

Conclusion:Gett ing new p rodu cts to market on t ime wi l l be harder .

Solution:A n ew des ign methodology is n eeded.




Slide -19


MYTHS The Old Design Strategy

Guess a design

Hope it works

Build it

Test it

Try to Fix it

Ship it


Slide -20


MYTHS

Detai ls of th e Three Design

Approaches

Source: G. Doyle, Mentor Graphics

Design by correct ing

Design by virtu al iteration

Correct by design The earlier in the design cy cle problem s

can be identif ied and solv ed, the lower the

developm ent cost and the faster time to

market.




Slide -21


MYTHS

Two Cri t ical Processes for

Virtual Design and Test

Model ing : Translating the physical world into anequivalent electrical circuit model (Schematic)

Simulat ion : Predicting voltage/current waveforms based onthe circuit behavior

Zo,

τ

DZo,

τ

D

Lpower

Lgnd

Clk1

Lpin

Cpin

LpinLconnLconn

Cconn Cconn

Cpin

Lpower

Lgnd

Clk1

Gate1

Gate2

PCB#1 Backplane PCB#2

Zo,

τ

D

V1

PULSE

R150 L11U

C1

30P

Q2

QN3904

Q10

QN3906

R4

680

R2

5K

V310

V210

X1WIRER310

C2

7P

V(10)

VLOADV(7)VEMITTER

V(3)

VOUT

2 1 3

4

7

8

9

6 10


Slide -22


MYTHS

1 6

1 1

1 6

2 1

2 6

M01:i011

M09:i091

M16:i161

M24a:i24a1

0.0

0.5

1.0

1.5

2.0

I n d u c t a n c e ( n H )

• Calculations: (03, 06)ü Rules of thumb

ü Analytic approximation

ü Parasitic extraction numerical tools: field solvers

• Measurements: (06)ü Impedance analyzer (LCZ)

ü Network Analyzer (NA)

ü Time Domain Reflectometer (TDR)

Where do Models Come From?

Courtesy of TDA Systems




Slide -23


MYTHS

Two Tools for Simulating

Circui ts

• SPICE : Simulation Program withIntegrated Circuit Emphasisü PSPICE from OrCAD/Cadence

ü IsSPICE from Intusoft

ü Advanced Design System (ADS) from HP Eesof

ü Maxwell SPICE from Ansoft

ü Micro-CAP from Spectrum

ü HSPICE from Avant!

• IBIS based simulators: Input/outputBuffer Interface Specificationü

Hyperlynx (Pads)ü Veribest/Mentor Graphics

ü Zukan Redac

ü Viewlogic

ü Interconnectix (Mentor Graphics)


Slide -24


MYTHS

Design Pr inc ip les for Good SI

Noise Categories Design Principles

Signal Quality Signals should see the sameimpedance through all interconnects

Cross talk Keep spacing of traces greater thana minimum value, minimize mutualinductance of non ideal returns

Rail Collapse Minimize the impedance of the

power and ground pathEMI Minimize bandwidth, minimize

ground impedance and shield

When are you done? How m uch reduct ion is enough?




Slide -25


MYTHS

time

money

risk

Cost factors:

…just follow

these RULES

Performance Per formance (meet specs) (meet specs)


Slide -26


MYTHS

Design Tradeoffs A re Nego t iated

With a Budget

• Total voltage swing is 3.3v

• Within 500 mV, all the noise sources must be accounted for:

**dynamic ef fects impor tant

An example:

•• In hi speed systems, keeping with in the noise budget is HARD! In hi speed systems, keeping with in the noise budget is HARD!

•• The more accurately you can predict perform ance, the less margin The more accurately you can predict perform ance, the less margin needed and the higher theneeded and the higher the

performanceperformance

Noise Source Allocated BudgetRinging/reflections 100mV

Discontinuities 40mV

Cross talk 90mVSSO noise 120mV

Rail collapse 100mV

Total* 450mV

Margin ~50mV

Discontinuities

9%

Rail collapse

22%

SSO noise

27%Cross talk

20%

Ringing

22%




Slide -27


MYTHS

The Most Important General

Design Principles

1. Slow down edges

2. Minimize the length of all interconnects

3. Use low dielectric constant materials for signal layers

4. Use controlled impedance lines and terminate

5. Minimize loop mutual inductances between signal lines

6. Use continuous, closely spaced, adjacent power andground planes


Slide -28


MYTHS

#1 so lut ion :

s low down th e edges

50 psec

150 mils spacing

50 Ohm line

2 short stubs (capacitive discontinuity)Top view

Longer therise time,

smaller the

impact, or,

the shorter thediscontinuity,the smaller the

impact




Slide -29


MYTHS Minimize Bandw idth

AVX Z chip: integrated RC, with low stray C

Spread Spectrum Clock Generator (SSCG)

At 2 GHz At 2.3 GHz

Figure 28. Data from Ansoft HFSS showing the field distribution on and off resonance for a 208 lead QFP, excited at one lead.

Avoid resonance and clock harmonics


Slide -30


MYTHS

#2 solut ion:

shorter is better

• Reflections:

• Cross talk

• Rail collapse

• EMI Near end

Mutual C, mutual L, scale with lengthSeries L scales with length

Radiated emission scales with length of current path




Slide -31


MYTHS

Term inations w i l l Minim ize

Reflected Noise from th e Ends

Series R terminate

RC terminate at far end, changing C

Source: Analog Devices


Slide -32


MYTHS

Avo id Stubs and B ranches

(for 0.5 nsec edges, stub length < 0.5 inches)

branches

daisy chain




Slide -33


MYTHS

Thin Power and Ground Layers

Reduc e Switching Noise

Conventional, 10mil thick spacing, 2

plane pairs

Thin layer, 2 milthick, 4 plane pairs

“A Low-Cost Technique for Reducing the

Simultaneous Switching Noise in Sub-Board

Packaging Configurations”, Koike and Kaizu, IEEE

Trans CPMT part B vol 21(4) Nov 1998 p. 428

Small daughtercard


Slide -34


MYTHS

Reduced Swi tching Noise

Improves effectiveness of the

decoupling caps

Reduces SSO noise




Slide -35


MYTHS

Reducing Emiss ions:

Low Impedance Power and Groun d Layers by

Thinner Dielectric


Slide -36


MYTHS

Avoid Spl i ts in Return Path

Archambeault, Bruce; “Proper design of intentional splits

in the ground reference plane of PC Boards to minimize

emissions from I/O wires and cables”, Proc. 1998 IEEE

conf on EMC, p. 768

with split

no split

Avoid al l spl i ts in the return path! Avoid al l spl i ts in the return path!




Slide -37


MYTHS Unintention al Spl i ts

Figure 9. How a via field for a connector can create a gap. By decreasing the clearance hole diameter in the ground plane, a continuous return path can be provided.

Figure 10. Data from [10]. Left is the emission from a board with gapsunder via fields- failing the Class A test. Right: the exact same board, but with smaller clearance holes and no gaps under traces- passing Class Atest.

Decreasingsize of

clearance

holesreduced

radiatedemissions


Slide -38


MYTHS

The Design Strategy

1. Use design guidelines as design guidelines to shoot for

2. Estimate the magnitude of each effect and the benefit from adesign or technology solution

3. Verify the models and simulations based on measurements of testvehicles and previous designs

4. Evaluate cost/performance trade offs

5. Keep optimizing until the noise budget is met

6. The earlier in the design cycle correct design decisions can bemade, the shorter time to market and lower the development cost




Slide -39


MYTHS

SI Problems App ly Across

ALL Interconnects

Courtesy of ICE

BOLData Corp


Slide -40


MYTHS

“There are two kind s of design

engineers, tho se that have sign al

integri ty problems , and thos e that wi l l”

Good Luck!

gtl11 - jitter analysis

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