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GS1532 HD-LINX® IIMulti-Rate Serializer with ClockCleaner™
GS1532 Data Sheet
21498 - 8 February 2007 1 of 51
Key Features• SMPTE 292M and SMPTE 259M-C compliant
scrambling and NRZ → NRZI encoding (with bypass)
• DVB-ASI sync word insertion and 8b/10b encoding• User selectable additional processing features
including: • CRC, ANC data checksum, and line number
calculation and insertion• TRS and EDH packet generation and insertion• illegal code remapping
• Internal flywheel for noise immune TRS generation• 20-bit / 10-bit CMOS parallel input data bus• 148.5MHz / 74.25MHz / 27MHz / 13.5MHz parallel
digital input• Automatic standards detection and indication• Pb-free and RoHS Compliant• 1.8V core power supply and 3.3V charge pump
power supply• 3.3V digital I/O supply• JTAG test interface• Small footprint compatible with GS1560A, GS1561,
GS9060, and GS9062
Applications• SMPTE 292M Serial Digital Interfaces• SMPTE 259M-C Serial Digital Interfaces• DVB-ASI Serial Digital Interfaces
DescriptionThe GS1532 is a multi-standard serializer with an integrated cable driver. When used in conjunction with the GO1555/GO1525* Voltage Controlled Oscillator, a transmit solution can be realized for HD-SDI, SD-SDI and DVB-ASI applications.
The device features an internal PLL, which can be configured for loop bandwidth as narrow as 100kHz. Thus the GS1532 can tolerate in excess of 300ps jitter on the input PCLK and still provide output jitter well within SMPTE specification. Connect the output clocks from Gennum’s GS4911 clock generator directly to the GS1532’s PCLK input and configure the GS1532’s loop bandwidth accordingly.
In addition to serializing the input, the GS1532 performs NRZ-to-NRZI encoding and scrambling as per SMPTE 292M/259M-C when operating in SMPTE mode. When operating in DVB-ASI mode, the device will insert K28.5 sync characters and 8b/10b encode the data prior to serialization.
Parallel data inputs are provided for 10-bit multiplexed or 20-bit demultiplexed formats at both HD and SD signal rates. An appropriate parallel clock input signal is also required.
The integrated cable driver features an output mute on loss of parallel clock, high impedance mode, adjustable signal swing, and automatic dual slew rate selection depending on HD/SD operational requirements.
The GS1532 also includes a range of data processing functions including automatic standards detection and EDH support. The device can also insert TRS signals, calculate and insert line numbers and CRC’s, re-map illegal code words and insert SMPTE 352M payload identifier packets. All processing features are optional and may be enabled/disabled via external control pin(s) and/or host interface programming.
The GS1532 is Pb-free, and the encapsulation compound does not contain halogenated flame retardant.
This component and all homogeneous subcomponents are RoHS compliant.
*For new designs use GO1555
GS1532 Data Sheet
Functional Block Diagram
GS1532 Functional Block Diagram
SDO
SDO
SDO_EN/DIS
RSET
CP
_CA
PH V F
DIN[19:0]
IOP
RO
C_E
N/D
IS
DV
B_A
SI
I/O Buffer & demux
SMPTE352M
generation
TRS insertion, Line number insertion, CRC insertion, data blank, code- re-map and flywheel
dvb
-asi
byp
ass
RE
SE
T_TRS
T
ResetHOST Interface / JTAG test
CS
_TMS
SC
LK_TC
K
SD
IN_TD
I
SD
OU
T_TDO
JTAG
/HO
ST
LOC
KE
D
VC
O
VC
O LF
LB_C
ON
T
VC
O_V
CC
VC
O_G
ND
SD
/HD
20bit/10b
it
DVB-ASI syncword insert &
8b/10b encode
EDHgeneration& SMPTEscramble
PC
LK
BLA
NK
DE
TEC
T_TRS
SM
PTE
_BY
PA
SS
Phase detector, charge pump, VCO control & power supply
P -> S
sd/h
d
ClockCleaner™
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GS1532 Data Sheet
Contents
Key Features.................................................................................................................1Applications...................................................................................................................1Description ....................................................................................................................1Functional Block Diagram .............................................................................................21. Pin Out .....................................................................................................................5
1.1 Pin Assignment ...............................................................................................51.2 Pin Descriptions ..............................................................................................6
2. Electrical Characteristics........................................................................................142.1 Absolute Maximum Ratings ..........................................................................142.2 DC Electrical Characteristics ........................................................................142.3 AC Electrical Characteristics.........................................................................162.4 Solder Reflow Profiles...................................................................................182.5 Input/Output Circuits .....................................................................................192.6 Host Interface Maps......................................................................................21
2.6.1 Host Interface Map (Read Only Registers) .........................................222.6.2 Host Interface Map (R/W Configurable Registers) .............................23
3. Detailed Description ...............................................................................................243.1 Functional Overview .....................................................................................243.2 Parallel Data Inputs.......................................................................................24
3.2.1 Parallel Input in SMPTE Mode............................................................253.2.2 Parallel Input in DVB-ASI Mode..........................................................253.2.3 Parallel Input in Data-Through Mode..................................................253.2.4 Parallel Input Clock (PCLK) ................................................................26
3.3 SMPTE Mode................................................................................................273.3.1 Internal Flywheel.................................................................................273.3.2 HVF Timing Signal Extraction.............................................................27
3.4 DVB-ASI mode..............................................................................................293.4.1 Control Signal Inputs ..........................................................................29
3.5 Data-Through Mode......................................................................................293.6 Additional Processing Functions...................................................................30
3.6.1 Input Data Blank .................................................................................303.6.2 Automatic Video Standard Detection..................................................303.6.3 Packet Generation and Insertion ........................................................32
3.7 Parallel-To-Serial Conversion .......................................................................393.8 Serial Digital Data PLL..................................................................................40
3.8.1 External VCO......................................................................................403.8.2 Lock Detect Output .............................................................................403.8.3 Loop Bandwidth Adjustment ...............................................................41
3.9 Serial Digital Output ......................................................................................413.9.1 Output Swing ......................................................................................42
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GS1532 Data Sheet
3.9.2 Serial Digital Output Mute...................................................................423.10 GSPI Host Interface ....................................................................................42
3.10.1 Command Word Description.............................................................433.10.2 Data Read and Write Timing ............................................................443.10.3 Configuration and Status Registers ..................................................45
3.11 JTAG...........................................................................................................453.12 Device Power Up ........................................................................................473.13 Device Reset...............................................................................................47
4. Application Reference Design................................................................................484.1 Typical Application Circuit .............................................................................48
5. References & Relevant Standards.........................................................................496. Package & Ordering Information............................................................................50
6.1 Package Dimensions ....................................................................................506.2 Packaging Data.............................................................................................516.3 Ordering Information .....................................................................................51
7. Revision History .....................................................................................................52
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GS1532 Data Sheet
1. Pin Out
1.1 Pin Assignment
DV
B_A
SI
IOP
RO
C_E
N/D
IS
SDOUT_TDO
SDIN_TDI
SCLK_TCK
F
V
H
DIN0
DIN1
IO_GND
BLANK
CORE_GND
CORE_VDD
JTAG/HOST
CS_TMS
RESET_TRSTVCO_VCC
CP_GND
VCO_GND
LF
VCO
LOCKED
CP_CAP
CORE_GND
CORE_VDD
DIN19
DIN18
IO_VDD
PCLK
LB_CONT
VCO
DETECT_TRS
CP
_VD
D
PD
_VD
D
PD
_GN
D
20b
it/10
bit
SM
PTE
_BY
PAS
S
RS
ET
DIN
17
IO_V
DD
DIN
2
DIN
3
DIN
4
DIN
5
DIN
6
DIN
7
DIN
8
DIN
9
IO_G
ND
IO_V
DD
DIN
10
DIN
11
DIN
12
DIN
13
DIN
14
DIN
15
DIN
16
IO_G
ND
1
80
SD
/HD
2 3 4 5 6 7
79
78
77
76
75
74
73
8 9 10 11 12 13 14
72
71
70
69
68
67
66
65
64
63
62
61
15 16 17 18 19 20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
4060 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
NC
NC
CD
_VD
D
SDO
SDO
CD_GND
SDO_EN/DIS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
RS
V
NC
NC
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GS1532 Data Sheet
1.2 Pin Descriptions
Table 1-1: Pin Descriptions
Pin Number
Name Timing Type Description
1 CP_VDD – Power Power supply connection for the charge pump. Connect to +3.3V DC analog.
2 PD_GND – Power Ground connection for the phase detector. Connect to analog GND.
3 PD_VDD – Power Power supply connection for the phase detector. Connect to +1.8V DC analog.
4, 6-8, 10, 14-17, 31, 65, 66, 70,
71
NC – – No connect.
5 RSV – – Reserved. Connect to Analog GND.
9 DVB_ASI Non Synchronous
Input CONTROL SIGNAL INPUTSignal levels are LVCMOS/LVTTL compatible.When set HIGH in conjunction with SD/HD = HIGH and SMPTE_BYPASS = LOW, the device will be configured to operate in DVB-ASI mode.When set LOW, the device will not support the encoding of received DVB-ASI data.
11 SD/HD Non Synchronous
Input CONTROL SIGNAL INPUTSignal levels are LVCMOS/LVTTL compatible.When set LOW, the device will be configured to transmit signal rates of 1.485Gb/s or 1.485/1.001Gb/s only.When set HIGH, the device will be configured to transmit signal rates of 270Mb/s only.
12 20bit/10bit Non Synchronous
Input CONTROL SIGNAL INPUTSignal levels are LVCMOS/LVTTL compatible.Used to select the input data bus width in SMPTE or Data-Through modes. This signal is ignored in DVB-ASI mode.When set HIGH, the parallel input will be 20-bit demultiplexed data.When set LOW, the parallel input will be 10-bit multiplexed data.
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GS1532 Data Sheet
13 IOPROC_EN/DIS Non Synchronous
Input CONTROL SIGNAL INPUTSignal levels are LVCMOS/LVTTL compatible.Used to enable or disable I/O processing features.When set HIGH, the following I/O processing features of the device are enabled:
• EDH Packet Generation and Insertion (SD-only)• SMPTE 352M Packet Generation and Insertion• ANC Data Checksum Calculation and Insertion• Line-based CRC Generation and Insertion (HD-only)• Line Number Generation and Insertion (HD-only)• TRS Generation and Insertion• Illegal Code Remapping
To enable a subset of these features, keep IOPROC_EN/DIS HIGH and disable the individual feature(s) in the IOPROC_DISABLE register accessible via the host interface.When set LOW, the I/O processing features of the device are disabled, regardless of whether the features are enabled in the IOPROC_DISABLE register.
18 SMPTE_BYPASS Non Synchronous
Input CONTROL SIGNAL INPUTSignal levels are LVCMOS/LVTTL compatible.When set HIGH in conjunction with DVB_ASI = LOW, the device will be configured to operate in SMPTE mode. All I/O processing features may be enabled in this mode. When set LOW, the device will not support the scrambling or encoding of received SMPTE data. No I/O processing features will be available.
19 RSET Analog Input Used to set the serial digital output signal amplitude. Connect to CD_VDD through 281Ω +/- 1% for 800mVp-p single-ended output swing.
20 CD_VDD – Power Power supply connection for the serial digital cable driver. Connect to +1.8V DC analog.
21 SDO_EN/DIS Non Synchronous
Input CONTROL SIGNAL INPUTSignal levels are LVCMOS/LVTTL compatible.Used to enable or disable the serial digital output stage.When set LOW, the serial digital output signals SDO and SDO are disabled and become high impedance.When set HIGH, the serial digital output signals SDO and SDO are enabled.
22 CD_GND – Power Ground connection for the serial digital cable driver. Connect to analog GND.
23, 24 SDO, SDO Analog Output Serial digital output signal operating at 1.485Gb/s, 1.485/1.001Gb/s, or 270Mb/s.The slew rate of these outputs is automatically controlled to meet SMPTE 292M and 259M specifications according to the setting of the SD/HD pin.
Table 1-1: Pin Descriptions (Continued)
Pin Number
Name Timing Type Description
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GS1532 Data Sheet
25 RESET_TRST Non Synchronous
Input CONTROL SIGNAL INPUTSignal levels are LVCMOS/LVTTL compatible.Used to reset the internal operating conditions to default settings and to reset the JTAG test sequence.Host Mode (JTAG/HOST = LOW)When asserted LOW, all functional blocks will be set to default conditions and all input and output signals become high impedance, including the serial digital outputs SDO and SDO.Must be set HIGH for normal device operation.JTAG Test Mode (JTAG/HOST = HIGH)When asserted LOW, all functional blocks will be set to default and the JTAG test sequence will be held in reset.When set HIGH, normal operation of the JTAG test sequence resumes.
26 JTAG/HOST Non Synchronous
Input CONTROL SIGNAL INPUTSignal levels are LVCMOS/LVTTL compatible.Used to select JTAG Test Mode or Host Interface Mode.When set HIGH, CS_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are configured for JTAG boundary scan testing.When set LOW, CS_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are configured as GSPI pins for normal host interface operation.
27 CS_TMS Synchronous with
SCLK_TCK
Input CONTROL SIGNAL INPUTSignal levels are LVCMOS/LVTTL compatible.Chip Select / Test Mode SelectHost Mode (JTAG/HOST = LOW)CS_TMS operates as the host interface chip select, CS, and is active LOW.JTAG Test Mode (JTAG/HOST = HIGH)CS_TMS operates as the JTAG test mode select, TMS, and is active HIGH.NOTE: If the host interface is not being used, tie this pin HIGH.
28 SDOUT_TDO Synchronous with
SCLK_TCK
Output CONTROL SIGNAL OUTPUTSignal levels are LVCMOS/LVTTL compatible.Serial Data Output / Test Data OutputHost Mode (JTAG/HOST = LOW)SDOUT_TDO operates as the host interface serial output, SDOUT, used to read status and configuration information from the internal registers of the device.JTAG Test Mode (JTAG/HOST = HIGH)SDOUT_TDO operates as the JTAG test data output, TDO.
Table 1-1: Pin Descriptions (Continued)
Pin Number
Name Timing Type Description
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GS1532 Data Sheet
29 SDIN_TDI Synchronous with
SCLK_TCK
Input
CONTROL SIGNAL INPUTSignal levels are LVCMOS/LVTTL compatible.Serial Data In / Test Data InputHost Mode (JTAG/HOST = LOW)SDIN_TDI operates as the host interface serial input, SDIN, used to write address and configuration information to the internal registers of the device.JTAG Test Mode (JTAG/HOST = HIGH)SDIN_TDI operates as the JTAG test data input, TDI.NOTE: If the host interface is not being used, tie this pin HIGH.
30 SCLK_TCK Non Synchronous
Input CONTROL SIGNAL INPUTSignal levels are LVCMOS/LVTTL compatible.Serial Data Clock / Test Clock.Host Mode (JTAG/HOST = LOW)SCLK_TCK operates as the host interface burst clock, SCLK. Command and data read/write words are clocked into the device synchronously with this clock.JTAG Test Mode (JTAG/HOST = HIGH)SCLK_TCK operates as the JTAG test clock, TCK.NOTE: If the host interface is not being used, tie this pin HIGH.
32 BLANK Synchronous with PCLK
Input CONTROL SIGNAL INPUTSignal levels are LVCMOS/LVTTL compatible.Used to enable or disable input data blanking.When set LOW, the luma and chroma input data is set to the appropriate blanking levels. Horizontal and vertical ancillary spaces will also be set to blanking levels.When set HIGH, the luma and chroma input data pass through the device unaltered.
33, 68 CORE_GND – Power Ground connection for the digital core logic. Connect to digital GND.
34 F Synchronous with PCLK
Input CONTROL SIGNAL INPUTSignal levels are LVCMOS/LVTTL compatible.Used to indicate the ODD / EVEN field of the video signal when DETECT_TRS is set LOW. The device will set the F bit in all outgoing TRS signals for the entire period that the F input signal is HIGH (IOPROC_EN/DIS must also be HIGH).The F signal should be set HIGH for the entire period of field 2 and should be set LOW for all lines in field 1 and for all lines in progressive scan systems.The F signal is ignored when DETECT_TRS = HIGH.
Table 1-1: Pin Descriptions (Continued)
Pin Number
Name Timing Type Description
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GS1532 Data Sheet
35 V Synchronous with PCLK
Input CONTROL SIGNAL INPUTSignal levels are LVCMOS/LVTTL compatible.Used to indicate the portion of the video field / frame that is used for vertical blanking when DETECT_TRS is set LOW. The device will set the V bit in all outgoing TRS signals for the entire period that the V input signal is HIGH (IOPROC_EN/DIS must also be HIGH).The V signal should be set HIGH for the entire vertical blanking period and should be set LOW for all lines outside of the vertical blanking interval.The V signal is ignored when DETECT_TRS = HIGH.
36 H Synchronous with PCLK
Input CONTROL SIGNAL INPUTSignal levels are LVCMOS/LVTTL compatible.Used to indicate the portion of the video line containing active video data when DETECT_TRS is set LOW. The device will set the H bit in all outgoing TRS signals for the entire period that the H input signal is HIGH (IOPROC_EN/DIS must also be HIGH).H signal timing is configurable via the H_CONFIG bit of the IOPROC_DISABLE register, accessible via the host interface.Active Line Blanking (H_CONFIG = 0h)The H signal should be set HIGH for the entire horizontal blanking period, including the EAV and SAV TRS words, and LOW otherwise. This is the default setting.TRS Based Blanking (H_CONFIG = 1h)The H signal should be set HIGH for the entire horizontal blanking period as indicated by the H bit in the received TRS ID words, and LOW otherwise.
37, 64 CORE_VDD – Power Power supply connection for the digital core logic. Connect to +1.8V DC digital.
Table 1-1: Pin Descriptions (Continued)
Pin Number
Name Timing Type Description
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GS1532 Data Sheet
38, 39, 42-48, 50
DIN[0:9] Synchronous with PCLK
Input PARALLEL DATA BUSSignal levels are LVCMOS/LVTTL compatible.DIN9 is the MSB and DIN0 is the LSB.
HD 20-bit modeSD/HD = LOW20bit/10bit = HIGH
Chroma data input in SMPTE mode SMPTE_BYPASS =HIGHDVB_ASI = LOWData input in Data-Through mode SMPTE_BYPASS = LOWDVB_ASI = LOW
HD 10-bit modeSD/HD = LOW20bit/10bit = LOW
High impedance in all modes.
SD 20-bit modeSD/HD = HIGH20bit/10bit = HIGH
Chroma data input in SMPTE mode SMPTE_BYPASS = HIGHDVB_ASI = LOWData input in Data-Through modeSMPTE_BYPASS = LOWDVB_ASI = LOWHigh impedance in DVB-ASI modeSMPTE_BYPASS = LOWDVB_ASI = HIGH
SD 10-bit modeSD/HD = HIGH20bit/10bit = LOW
High impedance in all modes.
40, 49, 60 IO_GND – Power Ground connection for digital I/O buffers. Connect to digital GND.
41, 53, 61 IO_VDD – Power Power supply connection for digital I/O buffers. Connect to +3.3V DC digital.
Table 1-1: Pin Descriptions (Continued)
Pin Number
Name Timing Type Description
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GS1532 Data Sheet
51, 52, 54-59, 62,
63
DIN[10:19] Synchronous with PCLK
Input PARALLEL DATA BUSSignal levels are LVCMOS/LVTTL compatible.DIN19 is the MSB and DIN10 is the LSB.
HD 20-bit modeSD/HD = LOW20bit/10bit = HIGH
Luma data input in SMPTE modeSMPTE_BYPASS = HIGHDVB_ASI = LOWData input in Data-Through modeSMPTE_BYPASS = LOWDVB_ASI = LOW
HD 10-bit modeSD/HD = LOW20bit/10bit = LOW
Multiplexed Luma and Chroma data input in SMPTE modeSMPTE_BYPASS = HIGHDVB_ASI = LOWData input in Data-Through modeSMPTE_BYPASS = LOWDVB_ASI = LOW
SD 20-bit modeSD/HD = HIGH20bit/10bit = HIGH
Luma data input in SMPTE modeSMPTE_BYPASS = HIGHDVB_ASI = LOWData input in Data-Through modeSMPTE_BYPASS = LOWDVB_ASI = LOWDVB-ASI data input in DVB-ASI mode SMPTE_BYPASS = LOWDVB_ASI = HIGH
SD 10-bit modeSD/HD = HIGH20bit/10bit = LOW
Multiplexed Luma and Chroma data input in SMPTE modeSMPTE_BYPASS = HIGHDVB_ASI = LOWData input in data through modeSMPTE_BYPASS = LOWDVB_ASI = LOWDVB-ASI data input in DVB-ASI modeSMPTE_BYPASS = LOWDVB_ASI = HIGH
67 DETECT_TRS Non Synchronous
Input CONTROL SIGNAL INPUTSignal levels are LVCMOS/LVTTL compatible.Used to select the timing mode of the device.When set HIGH, the device will lock the internal flywheel to the embedded TRS timing signals in the parallel input data.When set LOW, the device will lock the internal flywheel to the externally supplied H, V, and F input signals.
Table 1-1: Pin Descriptions (Continued)
Pin Number
Name Timing Type Description
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GS1532 Data Sheet
69 PCLK – Input PARALLEL DATA BUS CLOCKSignal levels are LVCMOS/LVTTL compatible.
HD 20-bit mode PCLK = 74.25MHz or 74.25/1.001MHz
HD 10-bit mode PCLK = 148.5MHz or 148.5/1.001MHz
SD 20-bit mode PCLK = 13.5MHz
SD 10-bit mode PCLK = 27MHz
72 LOCKED Synchronous with PCLK
Output STATUS SIGNAL OUTPUTSignal levels are LVCMOS / LVTTL compatible.The LOCKED signal will be HIGH whenever the device has correctly received and locked to SMPTE compliant data in SMPTE mode or DVB-ASI compliant data in DVB-ASI mode, or when the device has achieved lock in Data-Through mode.It will be LOW otherwise.
73, 74 VCO, VCO Analog Input Differential inputs for the external VCO reference signal. For single ended devices such as the GO1555/GO1525*, VCO should be AC coupled to VCO_GND. VCO is nominally 1.485GHz.*For new designs use GO1555
75 VCO_GND – Output Power
Ground reference for the external voltage controlled oscillator. Connect to pins 2, 4, 6, and 8 of the GO1555/GO1525*. This pin is an output.Should be isolated from all other grounds.*For new designs use GO1555
76 VCO_VCC – Output Power
Power supply for the external voltage controlled oscillator. Connect to pin 7 of the GO1555/GO1525*. This pin is an output.Should be isolated from all other power supplies. *For new designs use GO1555
77 LF Analog Output Control voltage to external voltage controlled oscillator. Nominally +1.25V DC.
78 CP_CAP Analog Input PLL lock time constant capacitor connection. Normally connected to VCO_GND through 2.2nF.
79 LB_CONT Analog Input Control voltage to set the loop bandwidth of the integrated reclocker. Normally connected to VCO_VDD through 15kΩ.
80 CP_GND – Power Ground connection for the charge pump. Connect to analog GND.
Table 1-1: Pin Descriptions (Continued)
Pin Number
Name Timing Type Description
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GS1532 Data Sheet
2. Electrical Characteristics
2.1 Absolute Maximum Ratings
2.2 DC Electrical Characteristics
Parameter Value/Units
Supply Voltage Core -0.3V to +2.1V
Supply Voltage I/O -0.3V to +4.6V
Input Voltage Range (any input) -2.0V to + 5.25V
Ambient Operating Temperature -20°C < TA < 85°C
Storage Temperature -40°C < TSTG < 125°C
Lead Temperature (soldering, 10 sec) 230°C
ESD Protection On All Pins 1kV
NOTES:1. See reflow solder profiles (Solder Reflow Profiles on page 18)2. MIL STD 883 ESD protection applied to all pins on the device.
Table 2-1: DC Electrical Characteristics
TA = 0°C to 70°C, unless otherwise specified.
Parameter Symbol Conditions Min Typ Max Units Test Levels
Notes
System
Operation Temperature Range TA – 0 – 70 °C – 1
Digital Core Supply Voltage CORE_VDD – 1.65 1.8 1.95 V 1 1
Digital I/O Supply Voltage IO_VDD – 3.0 3.3 3.6 V 1 1
Charge Pump Supply Voltage CP_VDD – 3.0 3.3 3.6 V 1 1
Phase Detector Supply Voltage
PD_VDD – 1.65 1.8 1.95 V 1 1
Input Buffer Supply Voltage BUFF_VDD – 1.65 1.8 1.95 V 1 1
Cable Driver Supply Voltage CD_VDD – 1.71 1.8 1.89 V 1 1
External VCO Supply Voltage Output
VCO_VCC – 2.25 2.50 2.75 V 1 –
+1.8V Supply Current I1V8 – – – 245 mA 1 4
+3.3V Supply Current I3V3 – – – 45 mA 1 –
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GS1532 Data Sheet
Total Device Power PD – – – 590 mW 5 4
ESD Protection on all Pins – – 1 – – kV – 2
Digital I/O
Input Logic LOW VIL – – – 0.8 V 1 –
Input Logic HIGH VIH – 2.1 – – V 1 –
Output Logic LOW VOL 8mA – 0.2 0.4 V 1 –
Output Logic HIGH VOH 8mA IO_VDD - 0.4
– – V 1 –
Input
RSET Voltage VRSET RSET=281Ω 0.54 0.6 0.66 V 1 3
Output
Output Common Mode Voltage VCMOUT 75Ω load, RSET=281Ω, SD and HD
0.8 1.0 1.2 V 1 –
TEST LEVELS1. Production test at room temperature and nominal supply voltage with
guardbands for supply and temperature ranges.2. Production test at room temperature and nominal supply voltage with
guardbands for supply and temperature ranges using correlated test.3. Production test at room temperature and nominal supply voltage.4. QA sample test.5. Calculated result based on Level 1, 2, or 3.6. Not tested. Guaranteed by design simulations.7. Not tested. Based on characterization of nominal parts.8. Not tested. Based on existing design/characterization data of similar
product.9. Indirect test.
NOTES1. All DC and AC electrical parameters within specification.2. MIL STD 883 ESD protection will be applied to all pins on the
device.3. Set by the value of the RSET resistor.4. SDO outputs enabled.
Table 2-1: DC Electrical Characteristics (Continued)
TA = 0°C to 70°C, unless otherwise specified.
Parameter Symbol Conditions Min Typ Max Units Test Levels
Notes
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GS1532 Data Sheet
2.3 AC Electrical Characteristics
Table 2-2: AC Electrical Characteristics
TA = 0°C to 70°C, unless otherwise shown
Parameter Symbol Conditions Min Typ Max Units Test Levels
Notes
System
Device Latency – 10-bit SD – 21 – PCLK 6 –
– 20-bit HD – 19 – PCLK 6 –
– DVB-ASI – 11 – PCLK 6 –
Reset Pulse Width treset – 1 – – ms 7 3
Parallel Input
Parallel Clock Frequency fPCLK – 13.5 – 148.5 MHz 1 –
Parallel Clock Duty Cycle DCPCLK – 40 50 60 % 1 –
Input Data Setup Time tSU – 2 – – ns 1 1
Input Data Hold Time tIH – 1.5 – – ns 1 1
Serial Digital Output
Serial Output Data Rate DRSDO – – 1.485,1.485/1.001,
270
– Gb/sGb/sMb/s
1 –
Serial Output Swing ∆VSDD RSET = 281Ω Load = 75Ω
– 800 – mVp-p 1 –
Serial Output Rise Time20% ~ 80%
trSDO ORL compensation using recommended circuit — HD signal
– 200 260 ps 1 –
trSDO ORL compensation using recommended circuit — SD signal
400 550 1500 ps 1 –
Serial Output Fall Time20% ~ 80%
tfSDO ORL compensation using recommended circuit — HD signal
– 235 260 ps 1 –
tfSDO ORL compensation using recommended circuit — SD signal
400 550 1500 ps 1 –
Serial Output Intrinsic Jitter tIJ Pseudorandom and pathological HD signal
– 90 125 ps 1 –
tIJ Pseudorandom and pathological SD signal
– 270 350 ps 1 –
Serial Output Duty Cycle Distortion
DCDSDO HD (1.485Gb/s) – 10 – ps 1 2
DCDSDO SD (270Mb/s) – 20 – ps 1 2
21498 - 8 February 2007 16 of 51
GS1532 Data Sheet
GSPI
GSPI Input Clock Frequency fSCLK – – – 6.6 MHz 1 –
GSPI Input Clock Duty Cycle DCSCLK – 40 50 60 % 6,7 –
GSPI Input Data Setup Time – – 0 – – ns 6,7 –
GSPI Input Data Hold Time – – – – 1.43 ns 6,7 –
GSPI Output Data Hold Time – – 2.10 – – ns 6,7 –
GSPI Output Data Delay Time
– – – – 7.27 ns 6,7 –
TEST LEVELS1. Production test at room temperature and nominal supply
voltage with guardbands for supply and temperature ranges.2. Production test at room temperature and nominal supply
voltage with guardbands for supply and temperature ranges using correlated test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.5. Calculated result based on Level 1, 2, or 3.6. Not tested. Guaranteed by design simulations.7. Not tested. Based on characterization of nominal parts.8. Not tested. Based on existing design/characterization data of
similar product.9. Indirect test.
NOTES1. With 15pF load.2. Serial Duty Cycle Distortion is defined here to be the difference
between the width of a ‘1’ bit, and the width of a ‘0’ bit.3. See Device Power Up on page 46, Figure 3-13.
Table 2-2: AC Electrical Characteristics (Continued)
TA = 0°C to 70°C, unless otherwise shown
Parameter Symbol Conditions Min Typ Max Units Test Levels
Notes
21498 - 8 February 2007 17 of 51
GS1532 Data Sheet
2.4 Solder Reflow ProfilesThe device is manufactured with Matte-Sn terminations and is compatible with both standard eutectic and Pb-free solder reflow profiles. The recommended standard eutectic reflow profile is shown in Figure 2-1. MSL qualification was performed using the maximum Pb-free reflow profile shown in Figure 2-2.
Figure 2-1: Standard Eutectic Solder Reflow Profile
Figure 2-2: Maximum Pb-free Solder Reflow Profile (Preferred)
25˚C
100˚C
150˚C
183˚C
230˚C220˚C
Time
Temperature
6 min. max
120 sec. max
60-150 sec.
10-20 sec.
3˚C/sec max
6˚C/sec max
25˚C
150˚C
200˚C
217˚C
260˚C250˚C
Time
Temperature
8 min. max
60-180 sec. max
60-150 sec.
20-40 sec.
3˚C/sec max
6˚C/sec max
21498 - 8 February 2007 18 of 51
GS1532 Data Sheet
2.5 Input/Output Circuits All resistors in ohms, all capacitors in farads, unless otherwise shown.
Figure 2-3: Serial Digital Output
Figure 2-4: VCO Control Output & PLL Lock Time Capacitor
Figure 2-5: PCLK Input
SDO
SDO
300CP_CAP
LF
VDD
42K
63K
PCLK
21498 - 8 February 2007 19 of 51
GS1532 Data Sheet
Figure 2-6: VCO Input
Figure 2-7: PLL Loop Bandwidth Control
VDD25
25
VCO
VCO
1.5K
5K
865mV 7.2K
LB_CONT
21498 - 8 February 2007 20 of 51
21
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uary
20
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51
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53
2 D
ata
Shee
t
2.6
Hos
t In
terf
ace
Map
s
REG
ISTE
R NA
ME
ADDR
ESS
1514
1312
1110
98
76
54
32
10
LINE
_352
M_f
21C
hNo
t Use
dNo
t Use
dNo
t Use
dNo
t Use
dNo
t Use
db1
0b9
b8b7
b6b5
b4b3
b2b1
b0LI
NE_3
52M
_f1
1Bh
Not U
sed
Not U
sed
Not U
sed
Not U
sed
Not U
sed
b10
b9b8
b7b6
b5b4
b3b2
b1b0
1Ah
FF_L
INE_
END_
F119
hNo
t Use
dNo
t Use
dNo
t Use
dNo
t Use
dNo
t Use
dNo
t Use
db9
b8b7
b6b5
b4b3
b2b1
b0FF
_LIN
E_ST
ART_
F118
hNo
t Use
dNo
t Use
dNo
t Use
dNo
t Use
dNo
t Use
dNo
t Use
db9
b8b7
b6b5
b4b3
b2b1
b0FF
_LIN
E_EN
D_F0
17h
Not U
sed
Not U
sed
Not U
sed
Not U
sed
Not U
sed
Not U
sed
b9b8
b7b6
b5b4
b3b2
b1b0
FF_L
INE_
STAR
T_F0
16h
Not U
sed
Not U
sed
Not U
sed
Not U
sed
Not U
sed
Not U
sed
b9b8
b7b6
b5b4
b3b2
b1b0
AP_L
INE_
END_
F115
hNo
t Use
dNo
t Use
dNo
t Use
dNo
t Use
dNo
t Use
dNo
t Use
db9
b8b7
b6b5
b4b3
b2b1
b0AP
_LIN
E_ST
ART_
F114
hNo
t Use
dNo
t Use
dNo
t Use
dNo
t Use
dNo
t Use
dNo
t Use
db9
b8b7
b6b5
b4b3
b2b1
b0AP
_LIN
E_EN
D_F0
13h
Not U
sed
Not U
sed
Not U
sed
Not U
sed
Not U
sed
Not U
sed
b9b8
b7b6
b5b4
b3b2
b1b0
AP_L
INE_
STAR
T_F0
12h
Not U
sed
Not U
sed
Not U
sed
Not U
sed
Not U
sed
Not U
sed
b9b8
b7b6
b5b4
b3b2
b1b0
RAST
ER_S
TRUC
TURE
411
hNo
t Use
dNo
t Use
dNo
t Use
dNo
t Use
dNo
t Use
db1
0b9
b8b7
b6b5
b4b3
b2b1
b0RA
STER
_STR
UCTU
RE3
10h
Not U
sed
Not U
sed
Not U
sed
Not U
sed
Not U
sed
b10
b9b8
b7b6
b5b4
b3b2
b1b0
RAST
ER_S
TRUC
TURE
20F
hNo
t Use
dNo
t Use
dNo
t Use
dNo
t Use
db1
1b1
0b9
b8b7
b6b5
b4b3
b2b1
b0RA
STER
_STR
UCTU
RE1
0Eh
Not U
sed
Not U
sed
Not U
sed
Not U
sed
b11
b10
b9b8
b7b6
b5b4
b3b2
b1b0
0Dh
0Ch
VIDE
O_F
ORM
AT_B
0Bh
VF4-
b7VF
4-b6
VF4-
b5VF
4-b4
VF4-
b3VF
4-b2
VF4-
b1VF
4-b0
VF3-
b7VF
3-b6
VF3-
b5VF
3-b4
VF3-
b3VF
3-b2
VF3-
b1VF
3-b0
VIDE
O_F
ORM
AT_A
0Ah
VF2-
b7VF
2-b6
VF2-
b5VF
2-b4
VF2-
b3VF
2-b2
VF2-
b1VF
2-b0
VF1-
b7VF
1-b6
VF1-
b5VF
1-b4
VF1-
b3VF
1-b2
VF1-
b1VF
1-b0
09h
08h
07h
06h
05h
VIDE
O_S
TAND
ARD
04h
Not U
sed
VDS-
b4VD
S-b3
VDS-
b2VD
S-b1
VDS-
b0IN
T_PR
OG
STD_
LOCK
NOT
USED
NOT
USED
NOT
USED
NOT
USED
NOT
USED
NOT
USED
NOT
USED
NOT
USED
03h
EDH_
FLAG
02h
Not U
sed
ANC-
UES
ANC-
IDA
ANC-
IDH
ANC-
EDA
ANC-
EDH
FF-U
ESFF
-IDA
FF-ID
HFF
-EDA
FF-E
DHAP
-UES
AP-ID
AAP
-IDH
AP-E
DAAP
-EDH
01h
IOPR
OC_
DISA
BLE
00h
Not U
sed
Not U
sed
Not U
sed
Not U
sed
Not U
sed
Not U
sed
Not U
sed
H_CO
NFIG
Not U
sed
352M
_INS
ILLE
GAL
_RE
MAP
EDH_
CRC_
INS
ANC_
CSUM
_IN
SCR
C_IN
SLN
UM_
INS
TRS_
INS
21
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uary
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2.6
.1 H
ost
Inte
rfac
e M
ap (
Rea
d O
nly
Reg
iste
rs)
REG
ISTE
R NA
ME
ADDR
ESS
1514
1312
1110
98
76
54
32
10
1Ch
1Bh
1Ah
19h
18h
17h
16h
15h
14h
13h
12h
RAST
ER_S
TRUC
TURE
411
hb1
0b9
b8b7
b6b5
b4b3
b2b1
b0RA
STER
_STR
UCTU
RE3
10h
b10
b9b8
b7b6
b5b4
b3b2
b1b0
RAST
ER_S
TRUC
TURE
20F
hb1
1b1
0b9
b8b7
b6b5
b4b3
b2b1
b0RA
STER
_STR
UCTU
RE1
0Eh
b11
b10
b9b8
b7b6
b5b4
b3b2
b1b0
0Dh
0Ch
0Bh
0Ah
09h
08h
07h
06h
05h
VIDE
O_S
TAND
ARD
04h
VDS-
b4VD
S-b3
VDS-
b2VD
S-b1
VDS-
b0IN
T_PR
OG
STD_
LOCK
03h
02h
01h
00h
21
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uary
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ata
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2.6
.2 H
ost
Inte
rfac
e M
ap (
R/W
Con
figu
rabl
e R
egis
ters
)
REG
ISTE
R NA
ME
ADDR
ESS
1514
1312
1110
98
76
54
32
10
LINE
_352
M_f
21C
hb1
0b9
b8b7
b6b5
b4b3
b2b1
b0LI
NE_3
52M
_f1
1Bh
b10
b9b8
b7b6
b5b4
b3b2
b1b0
1Ah
FF_L
INE_
END_
F119
hb9
b8b7
b6b5
b4b3
b2b1
b0FF
_LIN
E_ST
ART_
F118
hb9
b8b7
b6b5
b4b3
b2b1
b0FF
_LIN
E_EN
D_F0
17h
b9b8
b7b6
b5b4
b3b2
b1b0
FF_L
INE_
STAR
T_F0
16h
b9b8
b7b6
b5b4
b3b2
b1b0
AP_L
INE_
END_
F115
hb9
b8b7
b6b5
b4b3
b2b1
b0AP
_LIN
E_ST
ART_
F114
hb9
b8b7
b6b5
b4b3
b2b1
b0AP
_LIN
E_EN
D_F0
13h
b9b8
b7b6
b5b4
b3b2
b1b0
AP_L
INE_
STAR
T_F0
12h
b9b8
b7b6
b5b4
b3b2
b1b0
11h
10h
0Fh
0Eh
0Dh
0Ch
VIDE
O_F
ORM
AT_B
0Bh
VF4-
b7VF
4-b6
VF4-
b5VF
4-b4
VF4-
b3VF
4-b2
VF4-
b1VF
4-b0
VF3-
b7VF
3-b6
VF3-
b5VF
3-b4
VF3-
b3VF
3-b2
VF3-
b1VF
3-b0
VIDE
O_F
ORM
AT_A
0Ah
VF2-
b7VF
2-b6
VF2-
b5VF
2-b4
VF2-
b3VF
2-b2
VF2-
b1VF
2-b0
VF1-
b7VF
1-b6
VF1-
b5VF
1-b4
VF1-
b3VF
1-b2
VF1-
b1VF
1-b0
09h
08h
07h
06h
05h
04h
03h
EDH_
FLAG
02h
ANC-
UES
ANC-
IDA
ANC-
IDH
ANC-
EDA
ANC-
EDH
FF-U
ESFF
-IDA
FF-ID
HFF
-EDA
FF-E
DHAP
-UES
AP-ID
AAP
-IDH
AP-E
DAAP
-EDH
01h
IOPR
OC_
DISA
BLE
00h
H_CO
NFIG
352M
_INS
ILLE
GAL
_RE
MAP
EDH_
CRC_
INS
ANC_
CSUM
_IN
SCR
C_IN
SLN
UM_
INS
TRS_
INS
GS1532 Data Sheet
3. Detailed Description
3.1 Functional OverviewThe GS1532 is a multi-rate serializer with an integrated cable driver. When used in conjunction with the external GO1555/GO1525* Voltage Controlled Oscillator, a transmit solution at 1.485Gb/s, 1.485/1.001Gb/s or 270Mb/s is realized.
The device has three different modes of operation which must be set by the application layer through external device pins.
When SMPTE mode is enabled, the device will accept 10-bit multiplexed or 20-bit demultiplexed SMPTE compliant data at both HD and SD signal rates. The device’s additional processing features are also enabled in this mode.
In DVB-ASI mode, the GS1532 will accept an 8-bit parallel DVB-ASI compliant transport stream on its upper input bus. The serial output data stream will be 8b/10b encoded and stuffed.
The GS1532’s third mode allows for the serializing of data not conforming to SMPTE or DVB-ASI streams.
The provided serial digital outputs feature a high impedance mode, output mute on loss of parallel clock and adjustable signal swing. The output slew rate is automatically controlled by the SD/HD setting.
In the digital signal processing core, several data processing functions are implemented including SMPTE 352M and EDH data packet generation and insertion, and automatic video standards detection. These features are all enabled by default, but may be individually disabled via internal registers accessible through the GSPI host interface.
Finally, the GS1532 contains a JTAG interface for boundary scan test implementations.
*For new designs use GO1555
3.2 Parallel Data InputsData inputs enter the device on the rising edge of PCLK as shown in Figure 3-1.
The input data format is defined by the setting of the external SD/HD, SMPTE_BYPASS and DVB_ASI pins and may be presented in 10-bit or 20-bit format. The input data bus width is controlled independently from the internal data bus width by the 20bit/10bit input pin.
21498 - 8 February 2007 24 of 51
GS1532 Data Sheet
Figure 3-1: PCLK to Data Timing
3.2.1 Parallel Input in SMPTE Mode
When the device is operating in SMPTE mode, (see SMPTE Mode on page 27), both SD and HD data may be presented to the input bus in either multiplexed or demultiplexed form depending on the setting of the 20bit/10bit input pin.
In 20-bit mode, (20bit/10bit = HIGH), the input data format should be word aligned, demultiplexed luma and chroma data. Luma words should be presented to DIN[19:10] while chroma words should occupy DIN[9:0].
In 10-bit mode, (20bit/10bit = LOW), the input data format should be word aligned, multiplexed luma and chroma data. The data should be presented to DIN[19:10]. DIN[9:0] will be high impedance in this mode.
3.2.2 Parallel Input in DVB-ASI Mode
When operating in DVB-ASI mode, (see DVB-ASI mode on page 29), the GS1532 automatically configures the input port for 10-bit operation regardless of the setting of the 20bit/10bit pin.
The device will accept 8-bit data words on DIN[17:10] such that DIN17 = HIN is the most significant bit of the encoded transport stream data and DIN10 = AIN is the least significant bit.
In addition, DIN19 and DIN18 will be configured as the DVB-ASI control signals INSSYNCIN and KIN respectively. See DVB-ASI mode on page 29 for a description of these DVB-ASI specific input signals.
DIN[9:0] will be high impedance when the GS1532 is operating in DVB-ASI mode.
3.2.3 Parallel Input in Data-Through Mode
When operating in Data-Through mode, (see Data-Through Mode on page 29), the GS1532 passes data presented to the parallel input bus to the serial output without performing any encoding or scrambling.
The input data bus width accepted by the device in this mode is controlled by the setting of the 20bit/10bit pin.
PCLK
DIN[19:0] DATA
Control signal input
tIS tIH
21498 - 8 February 2007 25 of 51
GS1532 Data Sheet
3.2.4 Parallel Input Clock (PCLK)
The frequency of the PCLK input signal required by the GS1532 is determined by the input data format. Table 3-1 below lists the possible input signal formats and their corresponding parallel clock rates. Note that DVB-ASI input will always be in 10-bit format, regardless of the setting of the 20bit/10bit pin.
Table 3-1: Parallel Data Input Format
Input Data Format DIN [19:10]
DIN [9:0] PCLK
Control Signals
20bit/10bit
SD/HD
SMPTE_BYPASS DVB_ASI
SMPTE MODE
20bit DEMULTIPLEXED SD LUMA CHROMA 13.5MHz HIGH HIGH HIGH LOW
10bit MULTIPLEXED SD LUMA / CHROMA
HIGH IMPEDANCE
27MHz LOW HIGH HIGH LOW
20bit DEMULTIPLEXED HD LUMA CHROMA 74.25 or74.25/ 1.001MHz
HIGH LOW HIGH LOW
10bit MULTIPLEXED HD LUMA / CHROMA
HIGH IMPEDANCE
148.5 or148.5/ 1.001MHz
LOW LOW HIGH LOW
DVB-ASI MODE
10bit DVB-ASI DVB-ASIDATA
HIGH IMPEDANCE
27MHz HIGH HIGH LOW HIGH
LOW HIGH LOW HIGH
DATA-THROUGH MODE
20bit DEMULTIPLEXED SD DATA DATA 13.5MHz HIGH HIGH LOW LOW
10bit MULTIPLEXED SD DATA HIGH IMPEDANCE
27MHz LOW HIGH LOW LOW
20bit DEMULTIPLEXED HD DATA DATA 74.25 or74.25/ 1.001MHz
HIGH LOW LOW LOW
10bit MULTIPLEXED HD DATA HIGH IMPEDANCE
148.5 or148.5/ 1.001MHz
LOW LOW LOW LOW
21498 - 8 February 2007 26 of 51
GS1532 Data Sheet
3.3 SMPTE ModeThe GS1532 is said to be in SMPTE mode when the SMPTE_BYPASS pin is set HIGH and the DVB_ASI pin is set LOW.
In this mode, the parallel data will be scrambled according to SMPTE 259M or 292M, and NRZ-to-NRZI encoded prior to serialization.
3.3.1 Internal Flywheel
The GS1532 has an internal flywheel which is used in the generation of internal / external timing signals, and in automatic video standards detection. It is operational in SMPTE mode only.
The flywheel consists of a number of counters and comparators operating at video pixel and video line rates. These counters maintain information about the total line length, active line length, total number of lines per field / frame and total active lines per field / frame for the received video standard.
When DETECT_TRS is LOW, the flywheel will be locked to the externally supplied H, V, and F timing signals.
When DETECT_TRS is HIGH, the flywheel will be locked to the embedded TRS signals in the parallel input data. Both 8-bit and 10-bit TRS code words will be identified by the device.
The flywheel 'learns' the video standard by timing the horizontal and vertical reference information supplied a the H, V, and F input pins, or contained in the TRS ID words of the received video data. Full synchronization of the flywheel to the received video standard therefore requires one complete video frame.
Once synchronization has been achieved, the flywheel will continue to monitor the received TRS timing or the supplied H, V, and F timing information to maintain synchronization.
3.3.2 HVF Timing Signal Extraction
As discussed above, the GS1532's internal flywheel may be locked to externally provided H, V, and F signals when DETECT_TRS is set LOW by the application layer.
The H signal timing should also be configured via the H_CONFIG bit of the internal IOPROC_DISABLE register as either active line based blanking or TRS based blanking, (see Packet Generation and Insertion on page 32).
Active line based blanking is enabled when the H_CONFIG bit is set LOW. In this mode, the H input should be HIGH for the entire horizontal blanking period, including the EAV and SAV TRS words. This is the default H timing assumed by the device.
When H_CONFIG is set HIGH, TRS based blanking is enabled. In this case, the H input should be set HIGH for the entire horizontal blanking period as indicated by the H bit in the associated TRS words.
21498 - 8 February 2007 27 of 51
GS1532 Data Sheet
The timing of these signals is shown in Figure 3-2.
Figure 3-2: H, V, F Timing
H:V:F TIMING - HD 20-BIT INPUT MODE
PCLK
LUMA DATA OUT
CHROMA DATA OUT
H
XYZ(eav)0000003FF
XYZ(eav)0000003FF
V
F
XYZ(sav)0000003FF
XYZ(sav)0000003FF
H;V:F TIMING AT SAV - HD 10-BIT INPUT MODE
0000003FF3FF XYZ(sav)000000 XYZ
(sav)
PCLK
H
V
F
H:V:F TIMING AT EAV - HD 10-BIT INPUT MODE
PCLK
0000003FF3FF XYZ(eav)000000 XYZ
(eav) MULTIPLEXED Y/Cr/Cb DATA OUT
H
V
F
MULTIPLEXED Y/Cr/Cb DATA OUT
H:V:F TIMING - SD 20-BIT INPUT MODE
PCLK
CHROMA DATA OUT
LUMA DATA OUT
H
0003FF
XYZ(eav)000
V
F
0003FF
XYZ(SAV)000
H:V:F TIMING - SD 10-BIT INPUT MODE
MULTIPLEXED Y/Cr/Cb DATA OUT
PCLK
H
V
F
XYZ(eav)0000003FF XYZ
(sav)0000003FF
H SIGNAL TIMING:
H_CONFIG = LOW
H_CONFIG = HIGH
21498 - 8 February 2007 28 of 51
GS1532 Data Sheet
3.4 DVB-ASI modeThe GS1532 is said to be in DVB-ASI mode when the SMPTE_BYPASS pin is set LOW and the DVB_ASI and SD/HD pins are set HIGH.
In this mode, all SMPTE processing functions are disabled, and the 8-bit transport stream data will be 8b/10b encoded prior to serialization.
3.4.1 Control Signal Inputs
In DVB-ASI mode, the DIN19 and DIN18 pins will be configured as DVB-ASI control signals INSSYNCIN and KIN respectively.
When INSSYNCIN is set HIGH, the device will insert K28.5 sync characters into the data stream. This function is used to assist system implementations where the GS1532 may be preceded by an external data FIFO. Parallel DVB-ASI data may be clocked into the FIFO at some rate less than 27MHz. The INSSYNCIN input may then be connected to the FIFO empty signal, thus providing a means of padding up the data transmission rate to 27MHz. See Figure 3-3.
NOTE: 8b/10b encoding will take place after K28.5 sync character insertion.
KIN should be set HIGH whenever the parallel data input is to be interpreted as any special character defined by the DVB-ASI standard (including the K28.5 sync character). This pin should be set LOW when the input is to be interpreted as data.
NOTE: When operating in DVB-ASI mode, DIN[9:0] become high impedance.
Figure 3-3: DVB-ASI FIFO Implementation using the GS1532
3.5 Data-Through ModeThe GS1532 may be configured by the application layer to operate as a simple parallel-to-serial converter. In this mode, the device presents data to the output buffer without performing any scrambling or encoding.
Data-through mode is enabled only when both the SMPTE_BYPASS and DVB_ASI pins are set LOW.
88
AIN ~ HIN
PCLK = 27MHz
INSSYNCIN
SDO
CLK_IN
CLK_OUT
FIFO SDO
WRITE_CLK<27MHz
FE
TS
KIN
GS1532
KIN
READ CLK=27MHz
21498 - 8 February 2007 29 of 51
GS1532 Data Sheet
3.6 Additional Processing FunctionsThe GS1532 contains an additional data processing block which is available in SMPTE mode only, (see SMPTE Mode on page 27).
3.6.1 Input Data Blank
The video input data may be 'blanked' by the GS1532. In this mode, all input video data except TRS words are set to the appropriate blanking levels by the device. Both the horizontal and vertical ancillary data spaces will also be set to blanking levels.
This function is enabled by setting the BLANK pin LOW.
3.6.2 Automatic Video Standard Detection
The GS1532 can detect the input video standard by using the timing parameters extracted from the received TRS ID words or supplied H, V, and F timing signals (see Internal Flywheel on page 27). This information is presented to the host interface via the VIDEO_STANDARD register (Table 3-2).
Total samples per line, active samples per line, total lines per field/frame and active lines per field/frame are also calculated and presented to the host interface via the RASTER_STRUCTURE registers (Table 3-3). These line and sample count registers are updated once per frame at the end of line 12. This is in addition to the information contained in the VIDEO_STANDARD register.
After device reset, the four RASTER_STRUCTURE registers default to zero.
Table 3-2: Host Interface Description for Video Standard Register
Register Name Bit Name Description R/W Default
VIDEO_STANDARDAddress: 004h
15 – Not Used. – –
14-10 VD_STD[4:0] Video Data Standard (see Table 3-4). R 0
9 INT_PROG Interlace/Progressive: Set LOW if detected video standard is PROGRESSIVE and is set HIGH if it is INTERLACED.
R 0
8 STD_LOCK Standard Lock: Set HIGH when flywheel has achieved full synchronization.
R 0
7-0 – Not Used. – –
21498 - 8 February 2007 30 of 51
GS1532 Data Sheet
3.6.2.1 Video Standard Indication
The video standard codes reported in the VD_STD[4:0] bits of the VIDEO_STANDARD register represent the SMPTE standards as shown in Table 3-4.
In addition to the 5-bit video standard code word, the VIDEO_STANDARD register also contains two status bits. The STD_LOCK bit will be set HIGH whenever the flywheel has achieved full synchronization. The INT_PROG bit will be set LOW if the detected video standard is progressive and HIGH if the detected video standard is interlaced.
The VD_STD[4:0], STD_LOCK and INT_PROG bits of the VIDEO_STANDARD register will default to zero after device reset. The VD_STD[4:0] and INT_PROG bits will also default to zero if the SMPTE_BYPASS pin is asserted LOW or if the LOCKED output is LOW. The STD_LOCK bit will retain its previous value if the PCLK is removed.
Table 3-3: Host Interface Description for Raster Structure Registers
Register Name Bit Name Description R/W Default
RASTER_STRUCTURE1Address: 00Eh
15-12 – Not Used. – –
11-0 RASTER_STRUCTURE_1[11:0] Words Per Active Line R 0
RASTER_STRUCTURE2Address: 00Fh
15-12 – Not Used. – –
11-0 RASTER_STRUCTURE_2[11:0] Words Per Total Line. R 0
RASTER_STRUCTURE3Address: 010h
15-11 – Not Used. – –
10-0 RASTER_STRUCTURE_3[10:0] Total Lines Per Frame R 0
RASTER_STRUCTURE4Address: 011h
15-11 – Not Used. – –
10-0 RASTER_STRUCTURE_4[10:0] Active Lines Per Field R 0
Table 3-4: Supported Video Standards
VD_STD[4:0] SMPTE Standard
Video Format Length of HANC
Length of Active Video
Total Samples
SMPTE352M Lines
00h 296M (HD) 1280x720/60 (1:1) 358 1280 1650 13
01h 296M (HD) 1280x720/60 (1:1) - EM 198 1440 1650 13
02h 296M (HD) 1280x720/30 (1:1) 2008 1280 3300 13
03h 296M (HD) 1280x720/30 (1:1) - EM 408 2880 3300 13
04h 296M (HD) 1280x720/50 (1:1) 688 1280 1980 13
05h 296M (HD) 1280x720/50 (1:1) - EM 240 1728 1980 13
06h 296M (HD) 1280x720/25 (1:1) 2668 1280 3960 13
07h 296M (HD) 1280x720/25 (1:1) - EM 492 3456 3960 13
08h 296M (HD) 1280x720/24 (1:1) 2833 1280 4125 13
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GS1532 Data Sheet
3.6.3 Packet Generation and Insertion
In addition to input data blanking and automatic video standards detection, the GS1532 may also calculate, assemble and insert into the data stream various types of ancillary data packets and TRS ID words.
09h 296M (HD) 1280x720/24 (1:1) - EM 513 3600 4125 13
0Ah 274M (HD) 1920x1080/60 (2:1) or 1920x1080/30 (PsF)
268 1920 2200 10, 572
0Bh 274M (HD) 1920x1080/30 (1:1) 268 1920 2200 18
0Ch 274M (HD) 1920x1080/50 (2:1) or1920x1080/25 (PsF)
708 1920 2640 10, 572
0Dh 274M (HD) 1920x1080/25 (1:1) 708 1920 2640 18
0Eh 274M (HD) 1920x1080/25 (1:1) - EM 324 2304 2640 18
0Fh 274M (HD) 1920x1080/25 (PsF) - EM 324 2304 2640 10, 572
10h 274M (HD) 1920x1080/24 (1:1) 818 1920 2750 18
11h 274M (HD) 1920x1080/24 (PsF) 818 1920 2750 10, 572
12h 274M (HD) 1920x1080/24 (1:1) - EM 338 2400 2750 18
13h 274M (HD) 1920x1080/24 (PsF) - EM 338 2400 2750 10, 572
14h 295M (HD) 1920x1080/50 (2:1) 444 1920 2376 10, 572
15h 260M (HD) 1920x1035/60 (2:1) 268 1920 2200 10, 572
16h 125M (SD) 1440x487/60 (2:1)(Or dual link progressive)
268 1440 1716 3, 276
17h 125M (SD) 1440x507/60 (2:1) 268 1440 1716 3, 276
19h 125M (SD) 525-line 487 generic – – 1716 3, 276
1Bh 125M (SD) 525-line 507 generic – – 1716 3, 276
18h ITU-R BT.656(SD)
1440x576/50 (2:1)(Or dual link progressive)
280 1440 1728 9, 322
1Ah ITU-R BT.656(SD)
625-line generic (EM) – – 1728 9, 322
1Dh Unknown HD – – – – –
1Eh Unknown SD – – – – –
1Ch, 1Fh Reserved – – – – –
NOTE: Though the GS1532 will work correctly on and serialize both 59.94Hz and 60Hz formats, it will not distinguish between them.
Table 3-4: Supported Video Standards (Continued)
VD_STD[4:0] SMPTE Standard
Video Format Length of HANC
Length of Active Video
Total Samples
SMPTE352M Lines
21498 - 8 February 2007 32 of 51
GS1532 Data Sheet
These features are only available when the device is set to operated in SMPTE mode and the IOPROC_EN/DIS pin is set HIGH. Individual insertion features may be enabled or disabled via the IOPROC_DISABLE register (Table 3-5).
All of the IOPROC_DISABLE register bits default to '0' after device reset, enabling all of the processing features. To disable any individual error correction feature, the host interface must set the corresponding bit HIGH in this register.
Table 3-5: Host Interface Description for Internal Processing Disable Register
Register Name Bit Name Description R/W Default
IOPROC_DISABLEAddress: 000h
15-9 – Not Used. – –
8 H_CONFIG Horizontal sync timing input configuration. Set LOW when the H input timing is based on active line blanking (default). Set HIGH when the H input timing is based on the H bit of the TRS words. See Figure 3-2.
R/W 0
7 – Not Used. – –
6 352M_INS SMPTE352M packet insertion. In HD mode, 352M packets are inserted in the Y channel only when one of the bytes in the VIDEO_FORMAT_A or VIDEO_FORMAT_B registers are programmed with non-zero values. The IOPROC_EN/DIS pin and SMPTE_BYPASS pin must also be set HIGH. Set HIGH to disable.
R/W 0
5 ILLEGAL_REMAP Illegal Code Remapping. Detection and correction of illegal code words within the active picture area (AP). The IOPROC_EN/DIS pin and SMPTE_BYPASS pin must also be set HIGH. Set HIGH to disable.
R/W 0
4 EDH_CRC_INS Error Detection & Handling (EDH) Cyclical Redundancy Check (CRC) error correction. In SD mode the GS1532 will generate and insert EDH packets. The IOPROC_EN/DIS pin and SMPTE_BYPASS pin must also be set HIGH. Set HIGH to disable.
R/W 0
3 ANC_CSUM_INS Ancillary Data Checksum insertion. The IOPROC_EN/DIS pin and SMPTE_BYPASS pin must also be set HIGH. Set HIGH to disable.
R/W 0
2 CRC_INS Y and C line-based CRC insertion. In HD mode, line-based CRC words are inserted in both the Y and C channels. The IOPROC_EN/DIS pin and SMPTE_BYPASS pin must be also set HIGH. Set HIGH to disable
R/W 0
1 LNUM_INS Y and C line number insertion - HD mode only. The IOPROC_EN/DIS pin and SMPTE_BYPASS pin must be set HIGH. Set HIGH to disable.
R/W 0
0 TRS_INS Timing Reference Signal Insertion. Occurs only when IOPROC_EN/DIS is HIGH and SMPTE_BYPASS is HIGH. Set HIGH to disable.
R/W 0
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GS1532 Data Sheet
3.6.3.1 SMPTE 352M Payload Identifier Insertion
The GS1532 can generate and insert SMPTE 352M payload identifier ancillary data packets into the data stream, based on information programmed into the host interface.
When this feature is enabled, the device will automatically generate the ancillary data preambles, (DID, SDID, DBN, DC), and calculate the checksum. The SMPTE 352M packet will be inserted into the data stream according to the line numbers programmed in the LINE_352M registers (Table 3-6).
The insertion process will only take place if one or more of the four VIDEO_FORMAT registers (Table 3-7) have been programmed with non-zero values. In addition, the GS1532 requires the 352M_INS bit of the IOPROC_DISABLE register be set LOW.
NOTE 1: For the purpose of determining the line and pixel position for insertion, the GS1532 will differentiate between PsF and interlaced formats by interrogating bits 14 and 15 of the VIDEO_FORMAT_A register.
The packets will be inserted immediately after the EAV word in SD video streams and immediately after the line-based CRC word in the Y channel of HD video streams.
NOTE 2: It is the responsibility of the user to ensure that there is sufficient space in the horizontal blanking interval for the insertion of the SMPTE 352M packets.
If there are other ancillary data packets present, the SMPTE 352M packet will be inserted in the first available location in the horizontal ancillary space. Ancillary data must be adjacent to the EAV in SD streams or to the line based-CRC in HD streams. Where there is insufficient space available, the 352M packets will not be inserted.
Table 3-6: Host Interface Description for SMPTE 352M Packet Line Number Insertion Registers
Register Name Bit Name Description R/W Default
LINE_352M_f1Address: 01Bh
15-11 – Not Used. – –
10-0 LINE_0_352M[10:0] Line number where SMPTE352M packet is inserted in field 1.
R/W 0
LINE_352M_f2Address: 01Ch
15-11 – Not Used. – –
10-0 LINE_1_352M[10:0] Line number where SMPTE352M packet is inserted in field 2.
R/W 0
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GS1532 Data Sheet
3.6.3.2 Illegal Code Remapping
If the ILLEGAL_REMAP bit of the IOPROC_DISABLE register is set LOW, the GS1532 will remap all codes within the active picture between the values of 3FCh and 3FFh to 3FBh. All codes within the active picture area between the values of 000h and 003h will be remapped to 004h.
In addition, 8-bit TRS and ancillary data preambles will be remapped to 10-bit values if this feature is enabled.
3.6.3.3 EDH Generation and Insertion
When operating in SD mode, (SD/HD = HIGH), the GS1532 will generate and insert complete EDH packets into the data stream. Packet generation and insertion will only take place if the EDH_CRC_INS bit of the IOPROC_DISABLE register is set LOW.
The GS1532 will generate all of the required EDH packet data including all ancillary data preambles, (DID, DBN, DC), reserved code words and checksum. Calculation of both full field (FF) and active picture (AP) CRC's will be carried out by the device.
SMPTE RP165 specifies the calculation ranges and scope of EDH data for standard 525 and 625 component digital interfaces. The GS1532 will utilize these standard ranges by default.
If the received video format does not correspond to 525 or 625 digital component video standards as determined by the flywheel pixel and line counters, then one of two schemes for determining the EDH calculation ranges will be employed:
1. Ranges will be based on the line and pixel ranges programmed by the host interface; or
2. In the absence of user-programmed calculation ranges, ranges will be determined from the received TRS ID words or supplied H, V, and F timing signals (see Internal Flywheel on page 27).
Table 3-7: Host Interface Description for SMPTE 352M Payload Identifier Registers
Register Name Bit Name Description R/W Default
VIDEO_FORMAT_BAddress: 00Bh
15-8 SMPTE352MByte 4
SMPTE 352M Byte 4 information must be programmed in this register when 352M_INS = LOW.
R/W 0
7-0 SMPTE352MByte 3
SMPTE 352M Byte 3 information must be programmed in this register when 352M_INS = LOW.
R/W 0
VIDEO_FORMAT_AAddress: 00Ah
15-8 SMPTE352MByte 2
SMPTE 352M Byte 2 information must be programmed in this register when 352M_INS = LOW.
R/W 0
7-0 SMPTE 352MByte 1
SMPTE 352M Byte 1 information must be programmed in this register when 352M_INS = LOW.
R/W 0
21498 - 8 February 2007 35 of 51
GS1532 Data Sheet
The registers available to the host interface for programming EDH calculation ranges include active picture and full field line start and end positions for both fields. Table 3-8 shows the relevant registers, which default to '0' after device reset.
If any or all of these register values are zero, then the EDH CRC calculation ranges will be determined from the flywheel generated H signal. The first active and full field pixel will always be the first pixel after the SAV TRS code word. The last active and full field pixel will always be the last pixel before the start of the EAV TRS code words.
EDH error flags (EDH, EDA, IDH, IDA and UES) for ancillary data, full field and active picture will also be inserted. These flags must be programmed into the EDH_FLAG registers of the device by the application layer (Table 3-9).
NOTE 1: It is the responsibility of the user to ensure that the EDH flag registers are updated once per field.
The prepared EDH packet will be inserted at the appropriate line of the video stream according to RP165. The start pixel position of the inserted packet will be based on the SAV position of that line such that the last byte of the EDH packet (the checksum) will be placed in the sample immediately preceding the start of the SAV TRS word.
NOTE 2: It is also the responsibility of the user to ensure that there is sufficient space in the horizontal blanking interval for the EDH packet to be inserted.
Table 3-8: Host Interface Description for EDH Calculation Range Registers
Register Name Bit Name Description R/W Default
AP_LINE_START_F0Address: 012h
15-10 – Not Used. – –
9-0 AP_LINE_START_F0[9:0] Field 0 Active Picture start line data used to set EDH calculation range outside of RP 165 values.
R/W 0
AP_LINE_END_F0Address: 013h
15-10 – Not Used. – –
9-0 AP_LINE_END_F0[9:0] Field 0 Active Picture end line data used to set EDH calculation range outside of RP 165 values.
R/W 0
AP_LINE_START_F1Address: 014h
15-10 – Not Used. – –
9-0 AP_LINE_START_F1[9:0] Field 1 Active Picture start line data used to set EDH calculation range outside of RP 165 values.
R/W 0
AP_LINE_END_F1Address: 015h
15-10 – Not Used. – –
9-0 AP_LINE_END_F1[9:0] Field 1 Active Picture end line data used to set EDH calculation range outside of RP 165 values.
R/W 0
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GS1532 Data Sheet
FF_LINE_START_F0Address: 016h
15-10 – Not Used. – –
9-0 FF_LINE_START_F0[9:0] Field 0 Full Field start line data used to set EDH calculation range outside of RP 165 values.
R/W 0
FF_LINE_END_F0Address: 017h
15-10 – Not Used. – –
9-0 FF_LINE_END_F0[9:0] Field 0 Full Field end line data used to set EDH calculation range outside of RP 165 values.
R/W 0
FF_LINE_START_F1Address: 018h
15-10 – Not Used. – –
9-0 FF_LINE_START_F1[9:0] Field 1 Full Field start line data used to set EDH calculation range outside of RP-165 values.
R/W 0
FF_LINE_END_F1Address: 019h
15-10 – Not Used. – –
9-0 FF_LINE_END_F1[9:0] Field 1 Full Field end line data used to set EDH calculation range outside of RP-165 values.
R/W 0
Table 3-8: Host Interface Description for EDH Calculation Range Registers (Continued)
Register Name Bit Name Description R/W Default
Table 3-9: Host Interface Description for EDH Flag Register
Register Name Bit Name Description R/W Default
EDH_FLAGAddress: 002h
15 – Not Used. – –
14 ANC-UES Ancillary Unknown Error Status flag will be generated and inserted when IOPROC_EN/DIS and SMPTE_BYPASS pins are HIGH and EDH_CRC_INS bit is LOW. SD mode only.
R/W 0
13 ANC-IDA Ancillary Internal device error Detected Already flag will be generated and inserted when IOPROC_EN/DIS and SMPTE_BYPASS pins are HIGH and EDH_CRC_INS bit is LOW. SD mode only.
R/W 0
12 ANC-IDH Ancillary Internal device error Detected Here flag will be generated and inserted when IOPROC_EN/DIS and SMPTE_BYPASS pins are HIGH and EDH_CRC_INS bit is LOW. SD mode only.
R/W 0
11 ANC-EDA Ancillary Error Detected Already flag will be generated and inserted when IOPROC_EN/DIS and SMPTE_BYPASS pins are HIGH and EDH_CRC_INS bit is LOW. SD mode only.
R/W 0
10 ANC-EDH Ancillary Error Detected Here flag will be generated and inserted when IOPROC_EN/DIS and SMPTE_BYPASS pins are HIGH and EDH_CRC_INS bit is LOW. SD mode only.
R/W 0
9 FF-UES Full Field Unknown Error flag will be generated and inserted when IOPROC_EN/DIS and SMPTE_BYPASS pins are HIGH and EDH_CRC_INS bit is LOW. SD mode only.
R/W 0
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GS1532 Data Sheet
8 FF-IDA Full Field Internal device error Detected Already flag will be generated and inserted when IOPROC_EN/DIS and SMPTE_BYPASS pins are HIGH and EDH_CRC_INS bit is LOW. SD mode only.
R/W 0
7 FF-IDH Full Field Internal device error Detected flag will be generated and inserted when IOPROC_EN/DIS and SMPTE_BYPASS pins are HIGH and EDH_CRC_INS bit is LOW. SD mode only.
R/W 0
6 FF-EDA Full Field Error Detected Already flag will be generated and inserted when IOPROC_EN/DIS and SMPTE_BYPASS pins are HIGH and EDH_CRC_INS bit is LOW. SD mode only.
R/W 0
5 FF-EDH Full Field Error Detected Here flag will be generated and inserted when IOPROC_EN/DIS and SMPTE_BYPASS pins are HIGH and EDH_CRC_INS bit is LOW. SD mode only.
R/W 0
4 AP-UES Active Picture Unknown Error Status flag will be generated and inserted when IOPROC_EN/DIS and SMPTE_BYPASS pins are HIGH and EDH_CRC_INS bit is LOW. SD mode only.
R/W 0
3 AP-IDA Active Picture Internal device error Detected Already flag will be generated and inserted when IOPROC_EN/DIS and SMPTE_BYPASS pins are HIGH and EDH_CRC_INS bit is LOW. SD mode only.
R/W 0
2 AP-IDH Active Picture Internal device error Detected Here flag will be generated and inserted when IOPROC_EN/DIS and SMPTE_BYPASS pins are HIGH and EDH_CRC_INS bit is LOW. SD mode only.
R/W 0
1 AP-EDA Active Picture Error Detected Already flag will be generated and inserted when IOPROC_EN/DIS and SMPTE_BYPASS pins are HIGH and EDH_CRC_INS bit is LOW. SD mode only.
R/W 0
0 AP-EDH Active Picture Error Detected Here flag will be generated and inserted when IOPROC_EN/DIS and SMPTE_BYPASS pins are HIGH and EDH_CRC_INS bit is LOW. SD mode only.
R/W 0
Table 3-9: Host Interface Description for EDH Flag Register (Continued)
Register Name Bit Name Description R/W Default
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GS1532 Data Sheet
3.6.3.4 Ancillary Data Checksum Generation and Insertion
The GS1532 will calculate checksums for all detected ancillary data packets presented to the device. These calculated checksum values are inserted into the data stream prior to serialization.
Ancillary data checksum generation and insertion will only take place if the ANC_CSUM_INS bit of the IOPROC_DISABLE register is set LOW.
3.6.3.5 Line Based CRC Generation and Insertion
The GS1532 will generate and insert line based CRC words into both the Y and C channels of the data stream. This feature is only available in HD mode and is enabled by setting the CRC_INS bit of the IOPROC_DISABLE register LOW.
3.6.3.6 HD Line Number Generation and Insertion
In HD mode, the GS1532 will calculate and insert line numbers into the Y and C channels of the output data stream.
Line number generation is in accordance with the relevant HD video standard as determined by the device, (see Automatic Video Standard Detection on page 30).
This feature is enabled when SD/HD = LOW, and the LNUM_INS bit of the IOPROC_DISABLE register is set LOW.
3.6.3.7 TRS Generation and Insertion
The GS1532 can generate and insert 10-bit TRS code words into the data stream as required. This feature is enabled by setting the TRS_INS bit of the IOPROC_DISABLE register LOW.
TRS word generation will be performed in accordance with the timing parameters generated by the flywheel which will be locked either to the received TRS ID words or the supplied H, V, and F timing signals (see Internal Flywheel on page 27).
3.7 Parallel-To-Serial ConversionThe parallel data output of the internal data processing blocks is fed to the parallel-to-serial converter. The function of this block is to generate a serial data stream from the 10-bit or 20-bit parallel data words and pass the stream to the integrated cable driver.
21498 - 8 February 2007 39 of 51
GS1532 Data Sheet
3.8 Serial Digital Data PLLTo obtain a clean clock signal for serialization and transmission, the input PCLK is locked to an external reference signal via the GS1532's integrated phase-locked loop. This PLL is also responsible for generating all internal clock signals required by the device.
Internal division ratios for the locked PCLK are determined by the setting of the SD/HD and 20bit/10bit pins as shown in Table 3-10.
3.8.1 External VCO
The GS1532 requires the GO1555/GO1525* external voltage controlled oscillator as part of its internal PLL.
Power for the external VCO is generated entirely by the GS1532 from an integrated voltage regulator. The internal regulator uses +3.3V supplied on the CP_VDD / CP_GND pins to provide +2.5V on the VCO_VCC / VCO_GND pins.
The external VCO produces a 1.485GHz reference signal for the PLL, input on the VCO pin of the device. Both reference and control signals should be referenced to the supplied VCO_GND as shown in the recommended application circuit of Typical Application Circuit on page 47.
*For new designs use GO1555
3.8.2 Lock Detect Output
The lock detect block controls the serial digital output signal and indicates to the application layer the lock status of the device via the LOCKED output pin.
LOCKED will be asserted HIGH if and only if the internal data PLL has locked the PCLK signal to the external VCO reference signal and one of the following is true:
1. The device is set to operate in SMPTE mode and has detected SMPTE TRS words in the serial stream; or
2. The device is set to operate in DVB-ASI mode and has detected K28.5 sync characters in the serial stream; or
Table 3-10: Serial Digital Output Rates
Supplied PCLK Rate Serial DigitalOutput Rate
Pin Settings
SD/HD 20bit/10bit
74.25 or74.25/1.001 MHz
1.485 or1.485/1.001Gb/s
LOW HIGH
148.5 or148.5/1.001MHz
1.485 or1.485/1.001Gb/s
LOW LOW
13.5MHz 270Mb/s HIGH HIGH
27MHz 270Mb/s HIGH LOW
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GS1532 Data Sheet
3. The device is set to operate in Data-Through mode.
3.8.3 Loop Bandwidth Adjustment
For new designs the GO1555 is recommended for use with the GS1532. The recommended application ciruit can be seen in Section 4.1 Typical Application Circuit.
Designs using the GO1525 VCO use different loop bandwidth components. The application circuit is shown in Figure 3-4.
NOTE: When using the GS1532 with the GS4911B clock generator a narrower loop bandwidth for the GS1532 serializer should be used. For more details please refer to section 2.5 of the GS4911B Reference Design.
Figure 3-4: Typical Application Circuit using GO1525
3.9 Serial Digital OutputThe GS1532 contains an integrated current mode differential serial digital cable driver with automatic slew rate control.
To enable the output, SDO_EN/DIS must be set HIGH by the application layer. Setting the SDO_EN/DIS signal LOW will cause the SDO and SDO output pins to become high impedance, resulting in reduced device power consumption.
With suitable external return loss matching circuitry, the GS1532's serial digital outputs will provide a minimum output return loss of -15dB at SD rates. Gennum recommends using the GS1528 SDI Dual Slew-Rate Cable Driver to meet output return loss specifications at HD rates.
LO
CK
V C O _ V C C
+ 1 . 8 V _ A
+ 3 . 3 V
V C O _ V C C
1234
727374757677787980
C P _ V D DP D _ G N DP D _ V D D
LO
CK
ED
VC
OV
CO
VC
O_
GN
DV
CO
_V
CCLF
CP
_C
AP
LB
_C
ON
TC
P_
GN
D
G O 1 5 2 5
5
4 8
2
713
6
VC
TR
G N D G N D
GN
D
VC
CO
/PNC
GN
D
1 0 n
0
1 0 n
1 0 0 n
1 0 n
0
1 u
2 n 2
1 u 1 0 n1 0 n
0
1 u
1 0 n
G N D _ A
G N D _ A
G N D _ V C O
G N D _ V C O
G N D _ V C O
G N D _ V C O
G N D _ V C O
G N D _ V C O
G N D _ V C O
G N D _ V C O
V C O _ V C C
1 5 K
G S 1 5 3 2
21498 - 8 February 2007 41 of 51
GS1532 Data Sheet
The integrated cable driver uses a separate power supply of +1.8V DC supplied via the CD_VDD and CD_GND pins.
3.9.1 Output Swing
Nominally, the voltage swing of the serial digital output is 800mVp-p single-ended into a 75Ω load. This is set externally by connecting the RSET pin to CD_VDD through 281Ω .
The output swing may be decreased by increasing the value of the RSET resistor. The relationship is approximated by the curve shown in Figure 3-5.
Alternatively, the serial digital output swing can drive 800mVp-p into a 50Ω load. Since the output swing is reduced by a factor of approximately one third when the smaller load is used, the RSET resistor must be 187Ω to obtain 800mVp-p.
Figure 3-5: Serial Digital Output Swing
3.9.2 Serial Digital Output Mute
The GS1532 will automatically mute the serial digital output when the LOCKED output signal is LOW. In this case, the SDO and SDO signals are set to a constant voltage level.
3.10 GSPI Host InterfaceThe GSPI, or Gennum Serial Peripheral Interface, is a 4-wire interface provided to allow the host to enable additional features of the device and /or to provide additional status information through configuration registers in the GS1532.
The GSPI comprises a serial data input signal SDIN, serial data output signal SDOUT, an active low chip select CS, and a burst clock SCLK. The burst clock must have a duty cycle between 40% and 60%.
Because these pins are shared with the JTAG interface port, an additional control signal pin JTAG/HOST is provided. When JTAG/HOST is LOW, the GSPI interface is enabled.
50Ω load
300
400
500
600
700
800
900
1000
250 300 350 400 450 500 550 600 650 700
RSET(Ω)
∆VS
DO
(mV
p-p
)
200
75Ω load
21498 - 8 February 2007 42 of 51
GS1532 Data Sheet
When operating in GSPI mode, the SCLK, SDIN, and CS signals are provided by the host interface. The SDOUT pin is a high-impedance output allowing multiple devices to be connected in parallel and selected via the CS input. The interface is illustrated in the Figure 3-6 below.
All read or write access to the GS1532 is initiated and terminated by the host processor. Each access always begins with a 16-bit command word on SDIN indicating the address of the register of interest. This is followed by a 16-bit data word on SDIN in write mode, or a 16-bit data word on SDOUT in read mode.
Figure 3-6: Gennum Serial Peripheral Interface (GSPI)
3.10.1 Command Word Description
The command word is transmitted MSB first and contains a read/write bit, nine reserved bits and a 6-bit register address. Set R/W = '1' to read and R/W = '0' to write from the GSPI.
Command words are clocked into the GS1532 on the rising edge of the serial clock SCLK. The appropriate chip select signal, CS, must be asserted low a minimum of 1.5ns (t0 in Figure 3-9 and Figure 3-10) before the first clock edge to ensure proper operation.
Each command word must be followed by only one data word to ensure proper operation.
Figure 3-7: Command Word
Figure 3-8: Data Word
SCLK
CS
SDOUT
SDIN
SCLK
CS
SDIN
SDOUT
Application Host GS1532
R/W RSV RSV RSV A0A1A2A3A4A5RSVRSVRSVRSVRSV RSV
MSB LSB
D15 D14 D13 D12 D0D1D2D3D4D5D6D7D8D9D11 D10
MSB LSB
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GS1532 Data Sheet
3.10.2 Data Read and Write Timing
Read and write mode timing for the GSPI interface is shown in Figure 3-9 and Figure 3-10 respectively. The maximum SCLK frequency allowed is 6.6MHz.
When writing to the registers via the GSPI, the MSB of the data word may be presented to SDIN immediately following the falling edge of the LSB of the command word. All SDIN data is sampled on the rising edge of SCLK.
When reading from the registers via the GSPI, the MSB of the data word will be available on SDOUT 12ns (t5) following the falling edge of the LSB of the command word, and thus may be read by the host on the very next rising edge of the clock. The remaining bits are clocked out by the GS1532 on the negative edges of SCLK.
Figure 3-9: GSPI Read Mode Timing
Figure 3-10: GSPI Write Mode Timing
3.10.3 Configuration and Status Registers
Table 3-11 summarizes the GS1532's internal status and configuration registers.
All of these registers are available to the host via the GSPI and are all individually addressable.
Where status registers contain less than the full 16 bits of information, two or more registers may be combined at a single logical address.
SDOUT
R/W RSV RSV A0A1A2A3A4A5RSVRSVRSVRSVRSVRSV
D15 D14 D13 D12 D0D1D2D3D4D5D6D7D8D9D11 D10
SCLK
CS
SDIN RSV
t0 t2
t3input data setup time
dutycycle t4 period t5
t6output datahold time
R/W RSV RSV A0A1A2A3A4A5RSVRSVRSVRSVRSVRSV D15 D14 D13 D12 D0D1D2D3D4D5D6D7D8D9D11 D10
SCLK
CS
SDIN RSV
t0 t2
t3input data setup time
dutycycle t4 period
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GS1532 Data Sheet
3.11 JTAGWhen the JTAG/HOST input pin of the GS1532 is set HIGH, the host interface port will be configured for JTAG test operation. In this mode, pins 27 through 30 become TMS, TDO, TDI, and TCK. In addition, the RESET_TRST pin will operate as the test reset pin.
Boundary scan testing using the JTAG interface will be enabled in this mode.
There are two methods in which JTAG can be used on the GS1532:
1. As a stand-alone JTAG interface to be used at in-circuit ATE (Automatic Test Equipment) during PCB assembly; or
2. Under control of the host for applications such as system power on self tests.
When the JTAG tests are applied by ATE, care must be taken to disable any other devices driving the digital I/O pins. If the tests are to be applied only at ATE, this can be accomplished with tri-state buffers used in conjunction with the JTAG/HOST input signal. This is shown in Figure 3-11.
Figure 3-11: In-Circuit JTAG
Table 3-11: GS1532 Internal Registers
Address Register Name See Section
000h IOPROC_DISABLE Section 3.6.3
002h EDH_FLAG Section 3.6.3.3
004h VIDEO_STANDARD Section 3.6.2
00Ah - 00Bh VIDEO_FORMAT Section 3.6.3.1
00Eh - 011h RASTER_STRUCTURE Section 3.6.2
012h - 019h EDH_CALC_RANGES Section 3.6.3.3
01Bh - 01Ch LINE_352M Section 3.6.3.1
Application HOST GS1532
CS_TMS
SCLK_TCK
SDIN_TDI
SDOUT_TDO
JTAG_HOST
In-circuit ATE probe
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GS1532 Data Sheet
Alternatively, if the test capabilities are to be used in the system, the host may still control the JTAG/HOST input signal, but some means for tri-stating the host must exist in order to use the interface at ATE. This is represented in Figure 3-12.
Figure 3-12: System JTAG
Please contact your Gennum representative to obtain the BSDL model for the GS1532.
3.12 Device Power UpThe GS1532 has a recommended power supply sequence. To ensure correct power up, power the CORE_VDD pins before the IO_VDD pins.
Device pins may also be driven prior to power up without causing damage.
To ensure that all internal registers are cleared upon power-up, the application layer must hold the RESET_TRST signal LOW for a minimum of 1ms after the core power supply has reached the minimum level specified in the DC Electrical Characteristics Table, (Table 2-1). See Figure 3-13.
3.13 Device ResetIn order to initialize all internal operating conditions to their default states the application layer must hold the RESET_TRST signal LOW for a minimum of treset = 1ms.
When held in reset, all device outputs will be driven to a high-impedance state.
Figure 3-13: Reset Pulse
Application HOST GS1532
CS_TMS
SCLK_TCK
SDIN_TDI
SDOUT_TDO
JTAG_HOSTIn-circuit ATE probe
Tri-State
CORE_VDD
RESET_TRSTtreset
+1.65V+1.8V
Reset Reset
treset
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GS1532 Data Sheet
4. Application Reference Design
4.1 Typical Application Circuit
LO
CK
S D / H D b2 0 b i t / 1 0 b i t bI O P R O C _ E N / D I S b
D A T A 0
D A T A 7
D A T A 1 2
D A T A 1
D A T A 8
D A T A 1 3D A T A 1 4
D A T A 1 6
D A T A 3
D A T A 6
D A T A 2
D A T A 1 1
D A T A 4
D A T A 1 7
D A T A 1 0
D A T A 1 5
D A T A 1 8
D A T A 9
D A T A 5
DE
TE
CT
_T
RS
SD
O_
EN
/DIS
b
JTA
G/H
OS
Tb
D A T A 1 9
I O P R O C _ E N / D I S b
2 0 b i t / 1 0 b i t b
+ 1 . 8 V
+ 3 . 3 V
+ 1 . 8 V _ A
+ 1 . 8 V
+ 3 . 3 V
+ 3 . 3 V
V C O _ V C C
+ 1 . 8 V _ A
+ 1 . 8 V _ A
+ 3 . 3 V
V C O _ V C C
+ 1 . 8 V _ A
G S 1 5 3 2
123456789
1 01 11 21 31 41 51 61 71 81 92 0
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
4 14 24 34 44 54 64 74 84 95 05 15 25 3
5 55 4
5 65 75 85 96 0
6162636465666768697071727374757677787980
C P _ V D DP D _ G N DP D _ V D DN C
D V B _ A S I
S D / H D2 0 b i t / 1 0 b i tI O P R O C _ E N / D I S
S M P T E _ B Y P A S SR S E TC D _ V D D
SD
O_
EN
/DIS
CD
_G
ND
SD
OS
DO
RE
SE
T_T
RS
TJT
AG
/HO
ST
CS
_TM
SS
DO
UT
_T
DO
SD
IN_
TD
IS
CL
K_
TC
KN
CB
LA
NK
CO
RE
_G
ND
F V H CO
RE
_V
DD
DIN
0D
IN1
IO_
GN
D
I O _ V D DD I N 2
D O U T 3D I N 4D I N 5D I N 6D I N 7D I N 8
I O _ G N DD I N 9
D I N 1 0D I N 1 1
I O _ V D D
D I N 1 3D I N 1 2
D I N 1 4D I N 1 5D I N 1 6D I N 1 7
I O _ G N D
IO_
VD
DD
IN1
8D
IN1
9C
OR
E_
VD
DN
CN
CD
ET
EC
T_
TR
SC
OR
E_
GN
DP
CL
K
LO
CK
ED
VC
OV
CO
VC
O_
GN
DV
CO
_V
CCLF
CP
_C
AP
LB
_C
ON
TC
P_
GN
D
R 1
G O 1 5 5 5
5
4 8
2
713
6
VC
TR
G N D G N D
GN
D
VC
CO
/PNC
GN
D
1 0 n
L
R 1
2 8 1 + / - 1 %
1 u
1 u
C
0
B N C
1 0 n
1 0 n
R
L
C 5 51 0 n
R
C
1 0 0 n
10 n
1 0 n
B N C
1 0 n
4 u 7
1 0 n
1 0 n
0
1 u
12
1 u
4 u 7
4 7 n
1 u 1 0 n
1 0 n
7 5
1 0 n
0
1 0 n
1 u
1 0 n
FVH
P C L K
D A T A [ 1 9 . . 0 ]
D V B _ A S I
S D / H D b
R E S E T _ T R S T b
L O C KB L A N K b
S M P T E _ B Y P A S S b
S C L K _ T C K
S D O U T _ T D OS D I N _ T D I
C S b _ T M S
J T A G / H O S T b
D E T E C T _ T R S
S D O _ E N / D I S b
2 0 b i t / 1 0 b i t b
I O P R O C _ E N / D I S b
N O T E : T o g u a r a n t e e - 1 5 d B O u t p u t R e t u r n L o s sa t H D r a t e s , i t i s r e c o m m e n d e d t h a t t h e G S 1 5 2 8M u l t i - R a t e C a b l e D r i v e r b e u s e d .
R , L , C f o r m t h e o u t p u t r e t u r n l o s s c o m p e n s a t i o n n e t w o r k .V a l u e s a r e s u b j e c t t o c h a n g e .
J T A G / H O S T b
D E T E C T _ T R S
S D O _ E N / D I S b
S M P T E _ B Y P A S S b
S D / H D b
D V B _ A S I
PC
LK
B L A N K bL O C K
BL
AN
Kb
D V B _ A S I
S M P T E _ B Y P A S S b
G N D _ A
G N D _ A
G N D _ A
G N D _ A
G N D _ A
G N D _ D
G N D _ D
G N D _ D
G N D _ D
G N D _ A
G N D _ D
G N D _ V C O
G N D _ V C O
G N D _ V C O
G N D _ V C O
G N D _ V C O
G N D _ V C O
G N D _ V C O
G N D _ V C O
R S VN CN CN C
N C
N CN CN CN C
NC
NC
V C O _ V C C
G N D _ A
N O T E : T h e v a l u e o f R 1 u s e d f o r t h e p u l l - u pr e s i s t o r s h o u l d b e 7 5 o h m w h e n t h e o u t p u t s a r ec o n n e c t e d d i r e c t l y t o a 7 5 o h m c a b l e a s s h o w nh e r e .T h e v a l u e o f R 1 s h o u l d b e 5 0 o h m w h e n t h eo u t p u t s a r e i n t e r f a c e d t o t h e G S 1 5 2 8 A C a b l eD r i v e r . P l e a s e s e e G e n n u m ' s R e f e r e n c e D e s i g n :" I n t e r f a c i n g t h e G S 1 5 3 2 t o t h e G S 1 5 2 8 M u l t i - r a t eC a b l e D r i v e r " .
3 3
D o n o t p o p u l a t e R2
R 2
N O T E : F o r G O 1 5 2 5 l o o p b a n d w i d t h c o m p o n e n t v a l u e s s e e S e c t i o n 3 . 8 . 3 .
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GS1532 Data Sheet
5. References & Relevant Standards
SMPTE 125M Component video signal 4:2:2 – bit parallel interface
SMPTE 260M 1125 / 60 high definition production system – digital representation and bit parallel interface
SMPTE 267M Bit parallel digital interface – component video signal 4:2:2 16 x 9 aspect ratio
SMPTE 274M 1920 x 1080 scanning analog and parallel digital interfaces for multiple picture rates
SMPTE 291M Ancillary Data Packet and Space Formatting
SMPTE 292M Bit-Serial Digital Interface for High-Definition Television Systems
SMPTE 293M 720 x 483 active line at 59.94 Hz progressive scan production – digital representation
SMPTE 296M 1280 x 720 scanning, analog and digital representation and analog interface
SMPTE 352M Video Payload Identification for Digital Television Interfaces
SMPTE RP165 Error Detection Checkwords and Status Flags for Use in Bit-Serial Digital Interfaces for Television
SMPTE RP168 Definition of Vertical Interval Switching Point for Synchronous Video Switching
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GS1532 Data Sheet
6. Package & Ordering Information
6.1 Package Dimensions
TOLERANCES OF FORM AND POSITION
SYMBOL
MIN NOM MAX MIN NOM MAX
MILLIMETER INCH
80L
b
e
aaa
ccc
bbb
D2
E2
0.22
0.65 BSC 0.026 BSC
12.35
0.20
0.20
0.10
0.008
0.008
0.004
0.486
0.48612.35
0.30 0.38 0.009 0.012 0.015
NOTES:Diagram shown is representative only. Table X is fixed for all pin sizes, and Table Y is specific to the 80-pin package.
Table Y
ddd 0.13 0.005
Table X
CONTROL DIMENSIONS ARE IN MILLIMETERS.
1. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH.2. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08mm. DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD IS 0.07mm FOR 0.4mm AND 0.5mm PITCH PACKAGES.
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GS1532 Data Sheet
6.2 Packaging Data
6.3 Ordering Information
Parameter Value
Package Type 14mm x 14mm 80-pin LQFP
Package Drawing Reference JEDEC MS026
Moisture Sensitivity Level 3
Junction to Case Thermal Resistance, θj-c 11.6°C/W
Junction to Air Thermal Resistance, θj-a (at zero airflow) 39.9°C/W
Psi 0.6°C/W
Pb-free and RoHS Compliant (GS1532-CFE3) Yes
Part Number Pb-free and RoHS Compliant
Package Temperature Range
GS1532-CF No 80-pin LQFP 0°C to 70°C
GS1532-CFE3 Yes 80-pin LQFP 0°C to 70°C
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GS1532 Data Sheet
CAUTIONELECTROSTATIC SENSITIVE DEVICESDO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION
DOCUMENT IDENTIFICATIONDATA SHEETThe product is in production. Gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible.
7. Revision History
Version ECR PCN Date Changes and / or Modifications
3 133556 – March 2004 Register addresses in Tables 2, 3, 5, 6, 7, 8, 9 and 11 are shown in DECIMAL. They should be shown in HEX (as per master Table in Section 2.5). Pins 65 and 66 were not shown on Pin Description Table.
4 133860 – May 2004 Converted GS1532 data sheet to new template format. Added note to host interface pins. Moved ESD to maximum absolute ratings. Adjusted Input Data Setup Time in AC Electrical Characteristics. Text in Table 4-2 and text in section 4.6.2.1 changed to read “INT_PROG” and "Interlace/Progressive: Set LOW if detected video standard is PROGRESSIVE and is set HIGH if it is INTERLACED”. Added Pb-free and Green availability and ordering information. Corrected minor typing errors.
5 134909 – April 2005 Updated document status to Data Sheet. Added description to Solder Reflow Profiles. Clarified setting of VD_STD[4:0], INT_PROG and STD_LOCK bits following a reset and/or removal of PCLK. Modified Typical Application Circuit to add interfacing note for GS1532 to GS1528A Cable Driver. Added Packaging Data section. Changed ‘Green’ references to RoHS Compliant.
6 136983 – June 2005 Restored missing overlines to pin names. Rephrased RoHS compliance statement. Added note on 59.94Hz and 60Hz formats to Table 3-4.
7 142223 41245 October 2006 Modified internal register addresses to hexidecimal values in Table 3-11. Added built-in ClockCleanerTM feature to document title and functional block diagram. Specified that serializer can reject >300ps pclk jitter in Description section on page 1. Corrected VIDEO_FORMAT register labels in description of bit 6 (352M_INS) in Table 3-5.
8 143760 42774 February 2007 Recommended GO1555 VCO for new designs. Updated Section 4.1 Typical Application Circuit. Added Section 3.8.3 Loop Bandwidth Adjustment.
GENNUM CORPORATIONMailing Address: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3Shipping Address: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946GENNUM JAPAN CORPORATIONShinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo, 160-0023 Japan Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505GENNUM UK LIMITED25 Long Garden Walk, Farnham, Surrey, England GU9 7HXTel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent infringement.GENNUM and the G logo are registered trademarks of Gennum Corporation.© Copyright 2002 Gennum Corporation. All rights reserved. Printed in Canada.www.gennum.com
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