grid · may 2007 visit us at page 2 your networking partner ® there ever a vacation from this...

M AY 2 0 0 7 V i s i t u s a t w w w . e - G R I D . n e t P a g e 1

GRID.pdf

Vis i t us at e-GRID.netMay 2007

Upcoming Conferences

May 7-10: AIAA Infotech@Aerospace Conf and Exhibit -- Doubletree Hotel, Rohnert Park [more]

May 20-25: DISPLAY WEEK: SID Int'l Symposium - Long Beach Convention Center, Long Beach [more]

June 4-8: 44th Design Automation Conference (DAC’07) - San Diego - Early registration Deadline: May 7 [more]

June 7-8: Frontiers in Biomedical Devices 2007 - Irvine, CA [more]

Updates? Visit www.e-grid.net

CHAPTER MEETINGS

SF-PES - 5/4 | PG&E's Modular Protection, Automation, & Control (MPAC) Initiative - installation control, reduced costs ... [more]

SCV-EDS - 5/8 | The Future of Complementary Bipolar - wide bandwidth, high output drive and exceptional symmetry ... [more]

SCV-CIS - 5/9 | "Cognitive" Memory and its Applications - a new system with integrated memory and pattern recognition ... [more]

SCV-CPMT - 5/9 | The Packaging Challenges and Solutions for Solfocus Concentrated Photovoltaic (CPV) Modules ... [more]

SCV-ComSoc - 5/9 | FTTP/GPON: Gigabit Passive Optical Networks - last-mile upgrades from telecoms ... [more]

SCV-Nano - 5/15 | Integrated Optofluidic Chips for Single Molecule Analysis - optical waveguides for both liquids and light ... [more]

SCV-CNSV - 5/15 | System-on-a-Chip Technology and Tools - applications; uses in interface technology; design tools ... [more]

SCV-EMB - 5/16 | Intelligent Medical Vigilance System: Detection of Physiological Signals Using a Mattress Cover with Pressure Sensors for Med/Surg Patients - reducing risk with resource limits ... [more]

OEB-IAS - 5/17 | Power System Harmonics Mitigation for Industrial Applications - working with electronics based loads ... [more]

SCV-SSC - 5/17 | Active Filters, NICs and NACs - active filter limitations using a little mathematics and basic theory ... [more]

SF-GOLD - 5/17 | IEEE GOLD Networking night at Noe's - connect with fellow IEEE Graduates Of the Last Decade ... [more]

SCV-LEOS - 5/22 | LEOS 30th Anniversary Program: A Conversa-tion with Dr. Townes, Nobel Laureate - and two colleagues ... [more]

SCV-CE - 5/22 | Lighting TVs and Screens with Lasers - a new level of performance and reliability ... [more]

SCV-Mag - 5/22 | Synergistic Integration of NV Flash and Hard Disk Drives - creation of the Hybrid HDD (HHDD) ... [more]

SF-IAS - 5/22 | Arc Flash Software - ... [more]

SCV-PSES - 5/22 | How Did it All Start? Computer History Museum Tour - back when computers weren't as safe and ubiquitous ... [more]

SCV-CPMT - 5/24 | Volume Production of Ultra-Thin Chips - thinning and singulation for high throughput rates, yields ... [more]

SCV-Rel - 5/30 | Designed Experiments and Reliability - redefine the problem to simplify and optimize ... [more]

SF-PES - 5/30 | The Renaissance of Nuclear Power - annual banquet plus two speakers ... [more]

SCV-CPMT - 6/13 | uPILR MicroContacts: A Next-Generation Chip-Scale Packaging Solution - a new fab process for density and routing efficiency ... [more]

SF-GOLD - 7/15 | IEEE GOLD Networking Event & Hike at Land's End - explore the beauty of the SF coast with IEEE Grads ... [more]

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MARKETPLACE – Services page 3

Tutorials from local Chapters MTT, CAS [more]Power Amplifiers for Wireless Applications May 5 Broadband Circuit Analysis/Design in CMOS May 19

CPMT [more]Challenges in Preassembly: Thin Silicon Dice and Developments in Chip Separation May 24

Computer [more]Multicore: the New Face of Computing June 2 SCV Section Short Course [more]ZigBee and IEEE 802.15.4 - What's the Buzz? May 31 Professional Skills Courses [more]- Working Across Cultures - Breakthrough Project Management - Managing Time & Multiple Priorities - Management Essentials more

Conference Call for Papers

Nov. 4-7: Asilomar Conference on Signals, Systems, & Computers - Pacific Grove - Abstracts Due Jun 1 [more]

http://www.e-grid.net/

M A Y 2 0 0 7 V i s i t u s a t w w w . e - G R I D . n e t P a g e 2

Your Networking Partner ®

May 2007 • Volume 54 • Number 5

IEEE-SFBAC ©2007

IEEE GRID is the monthly newsmagazine of the San Francisco Bay Area Council of the Institute of Electrical and Electronics Engineers, Inc. As a medium for news for technologists, managers and professors, the editorial objectives of IEEE GRID are to inform readers of newsworthy IEEE activities sponsored by local IEEE units (Chapters, Affinity Groups) taking place in and around the Bay Area; to publicize locally sponsored conferences and seminars; to publish paid advertising for conferences, workshops, symposia and classes coming to the Bay Area; and advertise services provided by local firms and entrepreneurs. IEEE GRID is published as the GRID Online Edition

residing at www.e-GRID.net, in a handy printable GRID.pdf edition at the end of each month, and also as the e-GRID sent by email twice each month to more than 24,000 Bay Area members and other professionals.

Editor: Paul Wesling IEEE GRID PO Box 2110 Cupertino CA 95015-2110 Tel: 408 331-0114 / 510 500-0106 / 415 367-7323 Fax: 408 904-6997 Email: edi tor@e-gr id.net www.e-GRID.net

From the editor . . . As soon as we master one new technology, i t

seems as though two more come along! Isn’ t there ever a vacat ion from th is onslaught of new developments?!

Wel l , i t doesn’ t seem that we’ l l get any rest

dur ing the next decade or two, judging by some of the topics I ’m seeing at the Chapter meet ings th is month. The Nanotechnology group’s ta lk is about s ingle-molecule spectroscopy (page 15), whi le a l l of a sudden there are new appl icat ions for compl imentary bipolar at Electron Devices’ meet ing (page 11). Sensors embedded in a mattress cover can now moni tor pat ients (EMB meet ing, page 17) and also the appl icat ion of lasers to l ight ing TV screens from Consumer Electronics (page 22).

And then there’s some fun! The SF GOLD

(Grads Of the Last Decade) team is having a networking get- together (page 20) and then a h ike on the headlands of San Francisco (page 31) – I th ink they’d let a few “older people” h ike wi th them, i f you showed up. How great can that be?! And a chance to hear from (and about) a Nobel Pr ize Winner, the co- inventor of the MASER and LASER (page 22) at LEOS’ 50th anniversary event.

So, leaf through th is issue of the GRID.pdf

and f ind one or two events that ’ l l s tretch your own knowledge. The fun part of being an engineer/developer is that we are the ones who have the pr ivi lege of learning – and then applying – al l of th is new stuf f .

Paul Wesl ing, edi tor

NOTE: This PDF version of the IEEE GRID – the GRID.pdf – is a monthly publication and is issued a few days before the first of the month. It is not updated after that. Please refer to the Online edition and Interactive Calendar for the latest information: www.e-GRID.net

DIRECTORS

Santa Clara Valley Fred Jones

Tom Coughlin

Oakland East Bay Bill DeHope

Victor Stepanians

San Francisco Sandra Ellis Dan Sparks

OFFICERS Chair: Tom Coughlin

Secretary: Bill DeHope Treasurer: Dan Sparks

IEEE-SFBAC PO Box 2110

Cupertino, CA 95015-2110

IEEE GRID


Patent Agent Jay Chesavage, PE

MSEE Stanford 3833 Middlefield Road, Palo Alto 94303

[email protected]

www.File-EE-Patents.com TEL: 650-619-5270 FAX: 650-494-3835

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650-961-5900

[email protected] www.thermengr.com

Device Thermal Characterization Package Thermal Characterization Thermal Test Boards Thermal Test Equipment & Fixtures

Do you provide a service? Would you like more inquiries?

• Access 25,000 engineers and managers • IEEE Members across the Bay Area • Monthly and Annual Rates available

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GRID.pdf

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• Multiphysics, Multidisciplinary Engng • CFD, Stress, Heat Transfer, Fracture • Fatigue, Creep, Electromagnetics • Dynamics, Design Optimization • Linear/Nonlinear Finite Element Analyses

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US & Canada

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- System Engineering - Test & Measurement - Schematic Capture & PCB layout- Expert Witness

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7–10 May 2007 Doubletree Hotel Sonoma Wine Country

Rohnert Park, California

Infotech@Aerospace is AIAA's premier interactive forum addressing information-enabled aerospace, encompassing the technologies, systems, and capabilities that are shaping the 21st century. This unique workshop/conference provides an opportunity for interaction among experts from a wide range of technology areas, engineering disciplines, and user communities to further the conceptualization, development, integration, and fielding of systems.

Sponsored by Organized by IEEE Professional Skills Courses Working Across Cultures

– Date/Time: Thurs, May 10, 8:30 AM – 4:30 PM – Location: TIBCO Software, Palo Alto – Fee: $375 for IEEE Members; $450 non-members

Breakthrough Project Management – Date/Time: Thurs-Fri, May 17-18, 8:30AM – 4:30PM – Location: Exar Corp, Fremont – Fee: $600 for IEEE Members; $675 non-members

Managing Time & Multiple Priorities – Date/Time: Tues, June 12, 9:00 AM – 1:00 PM – Location: Synopsys, Sunnyvale – Fee: $275 for IEEE Members; $325 non-members

The principal venue for unmanned vehicles constituencies...

• Intelligent and autonomous systems • Unmanned systems and vehicles • Robotics • Advanced communications • Sensors • Computer and software systems • Digital avionics • Command and control (C2) • Guidance and navigation • Human–machine interaction • Modeling and simulation … and more!

Save $100 through 10 April 2007!

For more information, visit

www.aiaa.org/events/infotech@aerospace SCV Chapters, Engineering Management & Components, Packaging and Manufacturing Technology Societies

Management Essentials new! – Date/Time: Thurs-Fri, June 14-15, 8:30 AM –

4:30 PM – Location: Trimble Navigation, Sunnyvale – Fee: $600 for IEEE Members; $675 non-members

Improve your skills – register for one of these classes, or for others coming up this spring. Bring a team!

For complete course information, schedule, and registration form, see our website:

www.EffectiveTraining.com

Attend the most comprehensive forum devoted to aerospace technologies and systems … and their integration!

http://www.aiaa.org/events/infotech@aerospace

http://www.effectivetraining.com/calendar.php?loc=local


A. Communications Systems: 1. Error Control Coding, 2. CDMA, 3. Modulation and Detection, 4. Performance Bounds, 5. Synchronization, 6. Ultra Wideband, 7. OFDM / Multicarrier, 8. Wireless

B. MIMO Communications and Signal Processing: 1. Space-Time Coding and Decoding, 2. Channel Estimation and Equalization, 3. Multi-User and Multi-Access Methods, 4. Cooperative Diversity.

C. Networks: 1. Transmission Techniques for Ad Hoc Networks, 2. Wireless Sensor Networks, 3. Network Information Theory, 4. Optical Networks.

D. Adaptive Systems and Processing: 1. Adaptive Filtering, 2. Fast Algorithms for Adaptive Filtering, 3. Frequency -Domain and Subband Adaptive Filtering.

E. Array Processing and Statistical Signal Processing: 1. Array Processing and Beamforming, 2. Sonar and Acoustical Array Processing, 3. Radar Array Processing, 4. Remote Sensing, 5. Signal Separation, 6. Estimation and Detection, 7. Non-Gaussian and Nonlinear Methods, 8. Identification.

F. Biomedical Signal and Image Processing: 1. Medical Image Analysis, 2. Imaging Modalities, 3. Advances in Medical Imaging, 4. Biomedical Signal Processing, 5. Biomedical Applications, 6. Bioinformatics, 7. Image Registration and Multi-modal Imaging, 8. Image Reconstruction, 9. Computer Aided Diagnosis, 10. Functional Imaging, 11. Visualization.

G. Multi-rate and Digital Signal Processing: 1. Filter Design, Theory, and Implementation, 2. Wavelets, 3. Quantization, 4. Sampling, 5. Signal Representations and Spectral Analysis.

H. Architecture and Implementation: 1. Program-mable and Reconfigurable Architectures, 2. SOC Architectures, 3. Low-power methods, 4. Compilers and Tools, 5. Integrated Algorithm and Architecture Implementation, 6. Computer Arithmetic, 7. Numerical Processing.

I. Speech, Image and Video Processing: 1. Speech Processing, 2. Speech Coding, 3. Speech Recognition, 4. Narrowband / Wideband Speech and Audio Coding, 5. Document Processing, 6. Models for Signal and Image Processing, 7. Image and Video Coding, 8. Image and Video Segmentation, 9. Image and Video Analysis, 10. Image / Video Security, Retrieval and Watermarking, 11. Image and Video Enhancement / Filtering, 12. Biometrics and Security.

CALL FOR PAPERS 41st

Annual Asilomar Conference on Signals, Systems, and Computers

Asilomar Hotel and Conference Grounds, Pacific Grove, California November 4 – 7, 2007

www.asilomarssc.org Authors are invited to submit abstracts before June 1, 2007, in the following areas:

Prospective authors are invited to submit a 50 to 100 word abstract and an extended summary (500 to 1000 words, plus figures). Submissions must include the title of the paper, each author's name and affiliation, and the technical area(s) in which the paper falls with number(s) from the above list. Please visit the conference website ( www.asilomarssc.org ) for specific information on the electronic submission process. No more than FOUR submissions are allowed per contributor, as author or co-author. All submissions must be received by June 1, 2007. Notifications of acceptance will be mailed by late August 2007, and author information will be available on the conference website by mid September 2007. Full papers will be due at the conference and published in the spring of 2008. All technical questions should be directed to the Technical Program Chair, Dr. Maïté Brandt-Pearce, e-mail: [email protected], or the General Chair, Dr. Victor DeBrunner, e-mail: [email protected].

CONFERENCE COMMITTEE General Chair: Victor DeBrunner, Florida State University

Technical Program Chair: Maïté Brandt-Pearce, University of Virginia Conference Coordinator: Monique P. Fargues, Naval Postgraduate School

Publication Chair: Michael Matthews, ATK Mission Research Publicity Chair: Murali Tummala, Naval Postgraduate School

Finance Chair: Frank Kragh, Naval Postgraduate School

The site for the 2007 Conference is at the Asilomar Conference Grounds, in Pacific Grove, CA. The grounds border the Pacific Ocean and are close to Monterey, Carmel, and the scenic Seventeen Mile Drive in Pebble Beach. The Conference is organized in cooperation with the Naval Postgraduate School, Monterey, CA, and ATK Mission Research, Monterey, CA. The IEEE Signal Processing Society is a technical co-sponsor of the conference.

http://www.asilomarssc.org/

http://www.asilomarssc.org/




The ASME Nanotechnology Institute, in cooperation with the IEEE’s Engineering in Medicine and Biology Society, is pleased to announce the 2nd Frontiers in Biomedical Devices conference, to be held June 7-8 in Irvine. Leading authorities in the commercial and academic arenas will focus their expertise in nine technical tracks plus posters:

• Imaging & Monitoring the Environment • Simulation & Modeling • Device Testing • Bio-Sensors & Diagnostics • Device Design & Development • Therapeutic Devices • Next Generation Device Technology • Clinical & Regulatory • Posters / Student Posters

Our program will be co-chaired by Abe Lee, Ph.D. of the University of California's Henry Samueli School of Engineering's Biomedical Engineering Department, and co-chaired by Walt Baxter, Ph.D. of Medtronic Cardiac Rhythm Management.

WHO SHOULD ATTEND Medical device engineers, research scientists, government & academic personnel, and those involved in medical device research, discovery, clinical evaluation and delivery of medical devices are encouraged to attend. The conference also includes an evening reception/ exhibition/poster session/panel session (with OCTANe) on June 7th at the hotel. Posters will be presented and displayed during the conference. The Hyatt Regency Irvine hotel is conveniently located near the John Wayne Airport. For more information and to register,

visit: www.asmeconferences.org/biomed07 Sponsorships & Table-Top Exhibits Available Contact Brandy Smith at [email protected] or 917-596-0306

J u n e 7- 8, 2 0 0 7 I r v i n e, C a l i f o r n i a

2nd Frontiers in Biomedical Devices Conference

http://www.asmeconferences.org/biomed07


http://www.ieee.org/join/


Soon, thousands of us will converge in San Diego to attend the Design Automation Conference, the largest and most prestigious annual event focused on the design of electronic circuits and systems. DAC is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 210 of the leading EDA, silicon and IP providers.

The DAC technical program is made up of 14 tutorials, 7 workshops, 17 DAC Pavilion presentations and 62 technical sessions divided into 11 tracks: Business; System-Level and Embedded Systems Design; MEGa; Low Power and Thermal; Analog and Circuit; Interconnect, Reliability and DFM; Verification and Test; Synthesis and FPGA; Physical Design; Beyond the Die; and New and Emerging Technologies. Business Track: (all-day Tuesday) Innovation or Extinction - the choice is yours! The business track begins with a morning keynote, and continues with an all-day management seminar presented by a group of luminaries: Geoffrey Moore, Raul Camposano and Jim Smith. Keynote Speakers: Designing a New Automotive DNA Lawrence D. Burns, VP-R&D, General Motors Perspective of the Future Semiconductor Industry: Challenges and Solutions Oh-hyun Kwon, President, System LSI Division, Samsung Design without Borders – ATribute to the Legacy of A. Richard Newton Prof. Jan M. Rabaey, Director Gigascale Systems Research Center, UC-Berkeley

Sponsors Special Sessions: • 1000-core Chips • Function Verification of ESL • Synthetic Biology • Trusted Hardware • Silicon Measurement • Virtual Automotive • Future Interconnect • WACI Theme Day:

This year's DAC Theme Day, on Wednesday July 26, will focus on Automotive Electronics. The modern car can now truly be described as a "networked computing platform," and the theme will highlight this issue in the context of electronic design automation. 44th DAC Workshops (Sunday and Monday) - 4th UML for SoC Design Workshop - Low Power Coalition Workshop: Standards for Low Power Design Intent - Design and Verification of Low Power ICs - Hardware Dependent Software (HDS) - Introduction to Chips and EDA for a Non-Technical Audience - Workshop for Women in Design Automation: Managing Your Career - 3rd Integrated Design Systems Workshop Advance Registration rates through May 7

Substantial discount for IEEE and ACM members, students

“Free Monday” exhibits pass Access the Advance Program on the website:

www.DAC.com

44th Design Automation Conference

San Diego June 4-8, 2007Technical Theme:

Automotive Electronics

http://www.dac.com/


Display Week: The SID International Symposium,

Seminar and Exhibition, now in its 45th year, is the premier international gathering of scientists, engineers, manufacturers and users in the electronic-display industry. The event provides access to a wide range of technology and applications from high-definition flat-panel displays using both emissive and liquid-crystal technology to the latest in OLED displays and large-area projection-display systems. One can find state-of-the-art information on the latest in image processing, systems software and display processor hardware, human factors and applied vision, and exciting new applications such as multimedia and the electronic cinema.

With more than 550 booths and 8,000 attendees, Display Week is the leading North American show for the electronic-display industry. Display Week 2007 will take place May 20-25 at the Long Beach Convention Center in Long Beach, CA.

Events at SID this year:

Business Conference (Mon & Tues, May 21 & 22) Presentations at the Conference will be given by the highest-level executives of the leading display industrial organizations. A networking reception will be held on Monday evening and the Conference will include the Display Week 2007 Keynote Addresses on Tuesday morning and continue the rest of the day. Investors Conference (Tues & Wed, May 22 & 23) Company presentations from leading public and private display companies, intended to appeal primarily to securities analysts, portfolio managers, investors, M&A specialists, and display company executives. Display Technology Seminars (Mon, May 21) These twelve 90-minute seminars on diverse topics related to the information display field are held on Monday, May 21. Registering for the Display Technology Seminars entitles you to attend any combination of seminars Exhibition Tuesday, May 22 10:30 AM - 6:30 PM Wednesday, May 23 9:00 AM - 5:00 PM Thursday, May 24 9:00 AM - 2:00 PM

Sunday Short Courses Fundamentals of Vision and Color Fundamentals of Display Optics Fundamentals of Video for the 21st Century Fundamentals of Microdisplays

Tutorials • Active Matrix Addressing Technologies for Flat Panel Displays • Flat Panel Display Measurements • Liquid-Crystal Electro-Optical Modes for Active-Matrix Displays • Optimizing Color Calibration and Characterization of AMLCDs • Mobile Displays • TFT-LCD Product Trends and Impact on Supply and Demand

Separate registration is allowed for the Workshops and Tutorials

Technical Sessions (May 22-25) 69 sessions of invited and contributed papers with over 280 oral presentations and 200 poster presentations, including: Active Matrix Devices: • Poly-Si TFTs • Poly-Si AMOLEDs • LCD TV • AMLCDs Integrated with Sensors • Mobile Display Devices • Flexible AM Displays • Organic TFTs Applications: • Medical Displays • High Dynamic Range/Wide Color Gamut • Human Vision for Mobile Displays Display Applications: • Video Processing • Display Power and Interface Optimization • Driving Circuits • High-Frame-Rate Driving • LED Backlight Driving Display Manufacturing: • Substrates and Coatings • Ink-Jet Printing • Deposition Methods • Packaging • Plasma and FEDs Display Measurements: • Metrology and Instrumentation • Motion Blur and LCDs Display Systems: • Novel Displays and Imaging Systems • Flat Fluorescent Lamps • Optical Backlight Designs • Stereoscopic and 3D Imaging • LED Backlighting Liquid Crystal Technology: • LCholesteric LCDs • Fast-Switching LCDs • Ferroelectrics • Wide Viewing Angle • Electronic Paper • LCDs for Mobile Applications • Novel Displays and Components • Emissive Reflective Displays OLED: • OLED Displays • White OLEDs I • OLED Lifetime • Transport • Manufacturing • Optics and Modeling • Materials • Solution-Processed OLEDs PROJECTION: • Advanced Projection Systems • Projection Key Components • Novel Projection Light Sources

… and more! See the Advance Program.

For complete information on Display Week 2007, visit the official conference Web site:

www.sid2007.org

Early-Bird Rates through May 4

DISPLAY WEEK SID INTERNATIONAL SYMPOSIUM, SEMINAR & EXHIBITION

May 20-25, 2007 Long Beach Convention Center, Long Beach

http://www.sid2007.org/


Join us in Silicon Valley for a special full-day tutorial on the hottest new wireless standard, IEEE 802.15.4, the basis for the ZigBee wireless networking standard. ZigBee and 802.15.4 promise low power consumption for low-bandwidth applications – in some cases exceeding battery shelf life! Presented from the viewpoint of a consulting embedded systems engineer, this tutorial will introduce you to the theory and networking structure of 802.15.4 and ZigBee as well as the practical integration of this network into embedded systems. Hands-on code will be presented and demonstrated as well as live demos of working hardware.

Charles Lord, P.E., our course instructor, is a consulting engineer with over 25 years of experience in the embedded systems, RF, military, and medical device/pharmaceutical fields. He is a frequent speaker for IEEE and quality/regulatory meetings and conferences. His company, Triangle Advanced Design and Automation, is based in Cary, NC. Register online TODAY!

www.tadatraining.com/santaclara

You must pre-register by May 24, 2007

SCV CPMT Chapter half-day Short Course:

Challenges in Preassembly: Thin Silicon Dice and Developments

in Chip Separation

Thursday, May 24 11:45 AM – 5:30 PM Ramada Inn, Sunnyvale

Preassembly of thin chips – linking front-end and back-end semiconductor processing to turn wafers into chips – has two main spheres: wafer-thinning and chip-separation. This half-day class will introduce the technologies and methods used for thinning wafers down for ultra-thin applications. An overview regarding the different process-flows will be given. The methods used and the physical processes involved will be studied in detail. Different processes of backside-treatment, improving the mechanical performance of the chips, will be presented. Current and future technologies for chip-separation will be discussed. The various separation processes and their pros and cons will be discussed. Emerging technologies will also be presented and evaluated. Topics and solutions regarding the handling of thin wafers and assembly of thin chips will also be briefly covered.

Instructor: Werner Kröninger, Infineon Technologies AG, Germany

Topics to be covered: ● The IEEE 802.15.4 Standard – the basics ● A comparison: Bluetooth vs ZigBee ● What is required to create a ZigBee-certified device ● What alternatives exist for low-power networking applications ● Example: an 802.15.4 device with Freescale and TI chipsets ● Programming examples:

● Simple MAC ● Full 802.15.4 MAC ● ZigBee stack ● Demos of point-to-point and star topology simple networks

including code ● Demo of a full ZigBee network ● Discussion of the physical and network layers (the RF link) ● Updates on ZigBee 2006 and the new 802.15.4-2006 standard Course fee: (includes lunch, refreshments) IEEE Members $299 Non-members $349 Retired, Unemployed, and Full-Time Undergrad Students $199

(On-site registration will be $40 more and availability of materials cannot be guaranteed.)

Participants receive a hardcopy of the slides presented and a CD of the code examples presented. Bring your fully-charged laptop!

Course Outline: • Applications for thin dice • Wafer thinning technologies: grinding,

wet-etch, polish, dry-etch • Inside silicon: The process of grinding • Wafer-bow and wafer-warp • Backside-treatment, chip thickness and strength • Relevant for packaging: Surface roughness • Limits to thinning wafers • Separating the dice: Current and emerging technologies • Shipping and handling of thinned dice or wafers • Assembly of thinned dice

Registration Fee: IEEE Members: $95 Non-members: $125 (includes lunch)

Who Should Attend: Engineers and technical managers involved in packaging, CSP, SiP, and SOP, etc., will benefit from this class, as will manufacturing and quality engineers.

For full information, visit the Chapter website:

www.cpmt.org/scv

Announcing a Special Tutorial for the IEEE Santa Clara Valley Section!

“ZigBee and IEEE 802.15.4 - What's the Buzz?”

Thursday, May 31, 2007

8:30 AM – 4:00 PM (registration 8-8:30AM)

at National Semiconductor, Building E Auditorium 2900 Semiconductor Drive, Santa Clara

http://www.tadatraining.com/santaclara

http://www.cpmt.org/scv/courses/thinchip.html


SCV Chapter, Microwave Theory and Techniques

Everyone is going wireless these days. From Google’s wireless network in Mountain View, to Sprint/Nextel’s use of WiMax for their wireless business, to cities like San Francisco and Philadelphia planning low-cost wireless networks, to the govern-ment’s transformational communications initiative – the desire to be “untethered” is widespread. This wireless vision has gone way past voice on cell phones and now includes laptop mobility, internet access on cell phones, mobile navigation devices, battlefield connectivity, and other applications. Within these systems, the requirements for RF power are demanding. Specifically, the ability to get the required power into the small space dictated by mobile devices is a challenging task. Needless to say, the power amplifier can be, and often is, a critical if not an enabling component. Engineers need to be able to understand the factors driving these requirements as well as the tools and “weapons” at their disposal for solving these challenges This short course gives an overview of key areas such as wireless applications being deployed and the state of power amplifier technologies and devices, and delves into details of power amplifier design techniques and packaging needed to meet these future challenges.

IEEE SCV-CAS TUTORIAL

Broadband and RF Circuit Analysis and Design in CMOS Technology Part II

Saturday May 19, 2007 – 8:30 AM – 1:00 PM

a t Cadence Design Systems – Bldg 5 2655 Seely Ave, San Jose

This tu tor ia l , a cont inuat ion of the Sept 2006

event , wi l l famil iar ize engineer ing professionals with both class ic and innovat ive new broadbanding techniques for CMOS technology amplif iers appropria te for s ta te-of- the-ar t communicat ion system appl icat ions, wi th a focus on Distributed Amplif iers . A unif ied circuit broadbanding s t ra tegy is d iscussed, as is a pract ical methodology for the monoli th ic rea l iza t ion of narrowband radio-frequency (RF) amplif iers . Because broadband and RF design necessar i ly entai ls the incorporation of sui table matching f i l ters in s ignal f low paths , a reasonably extensive discussion of loss less f i l ter archi tectures is incorporated in the tu tor ia l . Al l theoret ic and conceptual d isclosures are ver if ied through the resul ts of rea l is t ic SPICE simulat ions.

A short-course with leading industry researchers and distinguished professors covering WLAN, WiMAX,

cell and emerging 60GHz+ applications

Talks: “WiMax and the need for PA’s” “Next Generation Satellites and the Need for PA’s” “Power Amplifier Overview” “mmWave CMOS PA’s“ “Design of Power Amplifiers Using High Voltage

Breakdown GaN Devices” “The Evolution of GSM Handset Power Amplifiers” “PA Packaging”

Advance registration (before April 20)

$50 for IEEE members $65 for non-Members

Attendees will receive a free IMS2006 CDROM worth $75

Includes lunch and preprints of the presentations. More information, and to register:

www.mtt-scv.org/may_mtg.html

Instructor: Dr. John Choma, Fellow, Scintera Networks, and Professor of EE & Systems Archi-tecture Engineering, Univ of Southern California

Registration: 8:30 – 9:00 AM (includes pastries/coffee) Sponsored lunch: 12:15 – 1:00 PM

Tutorial Outline: 9:00: “Introduction and Overview” by Dr. William Kao 9:15: “Tutorial Part III” by Dr. John Choma 10:45: “Tutorial Part IV” by Dr. John Choma

Topics: Overview of MOS Transistor Modeling; Noise Sources In NMOS and PMOS Devices; Gain and Bandwidth Optimi-zation in Common Source Amplifiers; Broadband Architectures; Lossless Filters; Linearity Considerations

A CD of all lecture material and related notes will be provided to all attendees.

Registration Fee: IEEE Member $40 Non-Member $50

Registration Deadline May 5 (postmarked by May 5) After May 5 – if Space Available, $5.00 Surcharge See full Tutorial Description for prerequisites and other details:

www.ewh.ieee.org/r6/scv/cas

Power Amplifiers for Wireless Applications Saturday, May 5, 2007

8:00 AM: Registration 8::30–4:00: Presentations

Includes refreshment breaks, lunch at Stanford Linear Accelerator Ctr

http://www.mtt-scv.org/may_mtg.html

http://www.ewh.ieee.org/r6/scv/cas/index.html


PG&E's Modular Protection, Automation, & Control (MPAC)

Initiative Speaker: Anthony Haroian, PG&E Time: Noon - 1:00 PM Cost: Free lunch for IEEE members;

$5 for non-members Place: Pacific Gas & Electric Office, 77 Beale St,

Conference Room 307, San Francisco RSVP: by May 2nd to Shirin Tabatabai,

[email protected] Web: www.ewh.ieee.org/r6/san_francisco/pes

Anthony Haroian has managed the MPAC program since November of 2005 and is part of the Resource Strategy and Initiative Management Department. His duties include the development of resource plans, budgeting, and system planning. He also collaborates closely with the System Automation and Asset Management departments. Anthony has 17 years of energy experience in substation engineering, power plant development and construction, and high pressure natural gas transmission. He has a BS in Electrical Engineering and is a registered Professional Engineer in California and Oregon.

How does a modern utility reduce costs, increase

standardization, and bring its control buildings up-to-date with the latest technology? This presentation demonstrates PG&E’s successes in this area.

In 2002, PG&E began to develop new integrated protection and automation design standards to be used in designing control building modifications for existing and new substations. The development of these new standards was part of a larger strategy focusing on the replacement of aging infrastructure, improved reliability, and increased system visibility. Included in this strategy was the Modular Protection Automation Control (MPAC) concept which targeted improved installation control, reduced installation time and reduced costs. This presentation will discuss the MPAC solution, the technology behind it and its business case.

FRIDAY May 4SF Power Engineering


The Future of Complementary Bipolar

Speaker: Dennis Monticelli, National Semiconductor Time: Social at 6:00 PM, Presentation at 6:15 PM Cost: none Place: National Semiconductor Corp. Building E-1

- Auditorium CMA, 2900 Semiconductor Drive, Santa Clara

RSVP: not required Web: www.ewh.ieee.org/r6/scv/eds

Dennis M. Monticelli received his BSEE from the University of California at Santa Barbara in 1974 and joined National Semiconductor Corp. upon graduation. For 16 years he worked on a wide variety of analog and mixed signal development projects, both as a circuit designer and as Design Manager. He was selected to lead the newly formed Power Management business unit in 1991 and promoted to Vice President in 1995. In 2000, he was named a National Fellow. Mr. Monticelli currently serves as CTO for National Semiconductor with responsibility for strategic planning of technology and business.

Mr. Monticelli has authored numerous papers in the professional and trade press. He currently holds 20 patents in the area of circuit design and is a member of the National Semiconductor Patent Hall of Fame. In 1977 he received the Outstanding Paper Award at the IEEE International Solid State Circuits Conference (ISSCC). In 1994 he served as Program Chairman for that conference.

New applications with a need for simultaneous

wide bandwidth, high output drive, and exceptional symmetry have spawned new advances in an old technology, the Complementary Bipolar. This talk will briefly cover the history and applications, then go on to describe the circuits and modern processes that have recently appeared. The talk concludes with a look ahead at technical trends and new challenges in complementary bipolar technology.

TUESDAY May 8SCV Electron Devices


"Cognitive" Memory and its Applications

Speaker: Professor Bernard Widrow, EE Dept,

Stanford University Time: Presentation at 7:00 PM Cost: none Place: Stanford Univ, Packard 101 (free parking

after 4 PM) RSVP: not required Web: email to [email protected]

Bernard Widrow received the S.B., S.M., and Sc.D. degrees in Electrical Engineering from the Massachusetts Institute of Technology in 1951, 1953, and 1956, respectively. He joined the MIT faculty and taught there from 1956 to 1959. In 1959, he joined the faculty of Stanford University, where he is currently Professor of Electrical Engineering.

He began research on adaptive filters, learning processes, and artificial neural models in 1957. Together with M.E. Hoff, Jr., his first doctoral student at Stanford, he invented the LMS algorithm in Autumn of 1959. Today, this is the world’s most widely used learning algorithm. He has continued working on adaptive signal processing, adaptive controls, and neural networks since that time.

Dr. Widrow is a Life Fellow of the IEEE and a Fellow of AAAS. He received the IEEE Centennial Medal in 1984, the IEEE Alexander Graham Bell Medal in 1986, the IEEE Signal Processing Society Medal in 1986, the IEEE Neural Networks Pioneer Medal in 1991, the IEEE Millennium Medal in 2000, and the Benjamin Franklin Medal for Engineering from the Franklin Institute of Philadelphia in 2001. He was inducted into the National Academy of Engineering in 1995, and into the Silicon Valley Engineering Council Hall of Fame in 1999.

Dr. Widrow is a past president and currently a member of the Governing Board of the International Neural Network Society. He is a member of the AdCom of the IEEE Computational Intelligence Society. He is associate editor of several journals and is the author of over 100 technical papers and 18 patents. He is co-author of “Adaptive Signal Processing” and “Adaptive Inverse Control,” both Prentice-Hall books. A new book, “Quantization Noise,” is in preparation.

Regarding the workings of the human mind, memory and pattern recognition seem to be intertwined. You generally do not have one without the other. Taking inspiration from life experience, a new form of computer memory has been devised. Certain conjectures about human memory are key to the central idea. The design of a practical and useful “cognitive” memory system is contemplated, a memory system that may also serve as a model for many aspects of human memory.

The new memory does not function like a computer memory where specific data is stored in specific numbered registers and retrieval is done by reading the contents of the specified memory register, or done by matching key words as with a document search. Incoming sensory data would be stored at the next available empty memory location, and indeed could be stored redundantly at several empty locations. The stored sensory data would neither have key words nor would it be located in known or specified memory locations.

Sensory inputs concerning a single object or subject are stored together as vectors in a single “file folder” or “memory folder.” When the contents of the folder are retrieved, sights, sounds, tactile feel, smell, etc., are obtained all at the same time. Sensor fusion is a memory phenomenon. The sensory signals are not fused, but they are simply recorded together in the same folder and retrieved together.

Retrieval would be initiated by a prompt signal from a current set of sensory inputs or patterns. A search through the memory would be made to locate stored data that correlates with or relates to the present real-time sensory inputs. The search would be done by a retrieval system that makes use of autoassociative artificial neural networks.

Applications of cognitive memory systems have been made to visual aircraft identification, aircraft navigation, and human facial recognition. Other applications to speech recognition and control systems are being explored.

WEDNESDAY May 9SCV Computational Intelligence

Patent Agent Jay Chesavage, PE

MSEE Stanford 3833 Middlefield Road, Palo Alto 94303

[email protected]

www.File-EE-Patents.com TEL: 650-619-5270 FAX: 650-494-3835


The Packaging Challenges and Solutions for Solfocus Concentrated Photovoltaic

(CPV) Modules Speaker: Wayne Miller, Director of Engineering,

Solfocus, Inc Time: 6:30 PM dinner (optional); 7:30 PM

Presentation Cost: Seated dinner served at 6:30 - $25 if

reserved by April 9; $30 after & at door Place: Ramada Inn, 1217 Wildwood Ave (Fwy

101 frontage road near Lawrence Expy), Sunnyvale

RSVP: through PayPal on website, or by email to Janis Karklins, [email protected]

Web: www.cpmt.org/scv Wayne Miller is Director of Engineering for SolFocus’

Gen1 CPV Solar Modules. He joined the company in 2006 to take the young company’s CPV technology and evolve it to prototype and then commercially available, high-volume products for the production of cost-competitive solar energy. His expertise in all aspects of engineering from concept through to product introduction and ongoing support and improvement has been critical to the company as it moves from the start-up phase to being a major global supplier.

Prior to joining SolFocus Mr. Miller was Director of Systems Engineering for In Focus Systems where he led product development for the company’s complete line of digital projection products. Previously he was a Senior Product Design Manager at Apple Computer with responsibility for leading product design for all desktop computer platforms, iMacs, and input devices, and before that was Senior Director of Engineering at Credence where he managed global engineering services and was responsible for the Interface Products business unit.

Mr. Miller holds 18 patents. He received his B.S. and M.S. in mechanical engineering from Northeastern University.

Worldwide energy consumption is expected to double in the next 20 years, and negative effects on the climate from classic fossil-fuel based power plants are accelerating. The current climate means that it’s now critical for clean-energy technologies such as solar photovoltaic (PV) to deliver lower-cost energy and to rapidly scale up to terawatt capacity.

Traditionally, the solar energy industry has relied on silicon to generate power. But silicon is expensive. Today the solar industry is facing a silicon feedstock shortage, while at the same time module production capacity is expected to double, driving up costs through increased competition for material. Power grids are struggling to keep up with peak demand loads, as evidenced by recent blackouts in the U.S., as well as China, Europe and other industrialized nations. Key flat-panel PV suppliers are beginning serious investigations and investment into concentrator photovoltaics (CPV).

Concentrator photovoltaic systems provide a practical solution to the silicon supply shortage by focusing sunlight onto much smaller photovoltaic receivers. Recent technological advances in high-efficiency receivers based on triple-junction cells enable CPV systems to require only 0.1% of the active material of flat-panel silicon PV.

The concentrator photovoltaic (CPV) designs of SolFocus, built on a long tradition of scientific advances by the solar industry, employ tailored imaging and non-imaging concentrator optics. These innovative modules are primarily fabricated of glass, which provides high specular reflectance and structural integrity.

Our CPV designs have several advantages over the comparative silicon flat panel PV: • 1000-fold reduction in active semiconductor material

area to generate the same amount of electricity • Semiconductor operating at nearly double the

efficiency of most flat-panel PV • The cost of solar electricity reduced to less than half of

today's cost Our proprietary design yields optimal form and

function, delivering an elegant, compact solution that can be replicated at sites around the world. Our patented optical design combined with record-setting efficiency dramatically lower the cost of power harnessed from the sun and delivered to its point of use, making solar energy a cost-effective, clean source of electricity.

There are some unique electro-mechanical packaging challenges associated with CPV systems, from the multi-junction PV die to the configuration and position of the opto-mechanical components. Wayne Miller leads the engineering team for the 1st generation product at Solfocus and will describe how the Solfocus engineering team has solved these problems and produced a high efficiency PV module.

WEDNESDAY May 9SCV Components, Packaging and Manufacturing Technology

Bernie Siegal

650-961-5900

[email protected] www.thermengr.com

Device Thermal Characterization Package Thermal Characterization Thermal Test Boards Thermal Test Equipment & Fixtures


FTTP/GPON: Gigabit Passive Optical Networks

Speaker: Don McCullough, VP Marketing,

Entrisphere Inc. Time: Presentation at 6:00 PM Cost: none Place: National Semiconductor, Building E,

Conference Room, 2900 Semiconductor Dr, Santa Clara

RSVP: not required Web: www.comsocscv.org

As VP of marketing, Don McCullough leads out-bound marketing and product management for the GPON product line at Ericsson. Don joined Ericsson along with the rest of the Entrisphere team in February 2007 when Ericsson acquired Entrisphere. Prior to the acquisition Don had been the Director and then VP of marketing for Entrisphere since 2003. He has 18 years of experience in developing and marketing high-bandwidth telecom access systems to deliver the triple play of services. He has worked in both start ups and public companies. Don holds an MBA from the Fuqua School of Business at Duke University.

Telecom carriers are upgrading their access

networks, or last mile, to offer competitive new service such as VoIP, IPTV and high speed data services. After a decade of getting more bandwidth out of their copper plant using DSL technology, carriers are turning to fiber using Passive Optical Networks, or PONs, to get even more. Verizon has deployed PON to over 3 million customers; carriers in Asia have deployed even more PON. But a new global standard is emerging, Gigabit PON or GPON. This presentation will show an over view of existing PON standards, Broadband PON (B-PON) and Ethernet PON (EPON), as well as GPON. It will provide market approaches to the various PON technologies and will present technology differences between them. Finally, the presentation will try to make sense of the directions that the PON market is likely to take over the next few years.

WEDNESDAY May 9SCV Communications

Valon Technology, LLC

valontechnology.com

[email protected]

RF and Wireless Product Design & Development

- System Engineering - Test & Measurement - Schematic Capture & PCB layout- Expert Witness

Redwood City (650) 369-0575


Integrated Optofluidic Chips for Single Molecule Analysis

Speaker: Dr. Holger Schmidt, Associate Professor of

Electrical Engineering, University of California, Santa Cruz

Time: Registration & light lunch 11:30 AM. Presentation at 12:00 Noon

Cost: IEEE Members and Students $5. Non-Members $10

Place: National Semiconductor Building E-1 CMA Room, 2900 Semiconductor Drive, Santa Clara

RSVP: on our web site: www.ieee.org/nano Web: www.ieee.org/nano

Holger Schmidt studies the fundamental physics of optical interactions between light and matter, with applications in the development of novel electronic and photonic devices. His research interests include integrated optofluidics for single molecule studies and biomedical applications, nano-magneto-optics, atomic spectroscopy on a chip, and nonlinear optics.

Dr. Schmidt earned a diploma in physics from the University of Stuttgart, Germany, and M.S. and Ph.D. degrees in electrical and computer engineering from UC Santa Barbara. Before joining the UCSC faculty, he was a postdoctoral fellow in the semiconductor laser group at the Massachusetts Institute of Technology. Since his arrival at UCSC in 2001, Dr. Schmidt received an NSF Career Award in 2001, and a Keck Futures Nano Award in 2005.

Recently, there has been a growing interest in

optofluidics, the combination of microfluidics and optics on a single chip. A new approach to this field has been developed based on liquid-core antiresonant reflecting optical waveguides (ARROWs). These waveguides can simultaneously guide both liquids and light and have the potential for creating fully planar optofluidic systems with ultrahigh sensitivity. In this talk, Dr. Schmidt will review the physical principle and fabrication of hollow-core ARROWs. He will then describe their application to single-molecule spectroscopy. In particular, He will discuss the detection and manipulation of single biomolecules in an ARROW-based optofluidic device and the addition of nanoscale structures for enhanced functionality.

TUESDAY May 15SCV Nanotechnology


System-on-a-Chip Technology and Tools

Speaker: Jason G. Baumbach, Cypress

Semiconductor Time: Presentation at 7:00 PM Cost: none Place: KeyPoint Credit Union, 2805 Bowers Ave.,

Santa Clara RSVP: not required Web: www.CaliforniaConsultants.org

Jason G. Baumbach is a Field Applications Engineer (FAE) at Cypess Semiconductor. After graduating from the University of Dayton in 1992, he served in the US Air Force for seven years where he worked on a variety of military-related technology products including adaptive optics. In 1999 he joined Cypress Semiconductor as an applications engineer and has had a variety of technical roles in three product lines.

Jason has one patent issued and three patents pending, and has presented at the Network Systems Design Conference, Communications Design Conference, ION-GPS and other conferences. As an FAE, he currently works with customers on a variety of embedded systems including networking equipment, consumer devices and medical/industrial equipment.

Jason Baumbach will show how System-On-Chip (SoC) technology reduces component count and lowers bill-of-materials costs by describing its use in the following applications:

* backlight control * voltage sequencing * voltage monitoring * temperature sensing * peripheral USB interfaces Jason will also describe the use of SoC in the

following user interface technologies: * resistive touchscreens * capacitive touchscreens (both surface

and projected capacitance) * capacitive buttons/sliders/touchpads * capacitive proximity detection * piezoelectric pressure sensors * pyroelectric infrared proximity detection Jason will then demonstrate use of the

Programmable System-On-Chip (PSoC) Express visual embedded design tool to generate a complete application ready to program into a device. In under 15 minutes, he will create a design that performs potentiometer position sensing, drives a 4-digit 7-segment LED with the voltage read from the pot, drives LEDs as a bargraph for the pot, and acts as an I2C master to read CapSense buttons from a device acting as an I2C slave.

Jason will also describe how Cypress Semiconductor's CYPros program helps consultants find clients. A CYPros Certified Consultant is an independent consultant who has demonstrated competence in Cypress's USB, WirelessUSB and PSoC (Programmable System-on-Chip) Mixed Signal Arrays products. Cypress provides an online method to allow its customers to find CYPros Certified Consultants.

CNSV and Cypress are teaming to help CNSV members become CYPros Certified Consultants.

TUESDAY May 15SCV Consultants' Network of Silicon Valley


Intelligent Medical Vigilance System: Detection of

Physiological Signals Using a Mattress Cover with Pressure Sensors for Med/Surg Patients

Speaker: Eben Kermit, Manager of Field Service,

Hoana Medical Time: optional dinner with the speaker, Stanford

Hospital cafeteria, at 6:15 PM; Presentation at 7:30 PM

Cost: none Place: Clark Center Auditorium, Stanford Univ

(free parking after 4 PM) RSVP: not required Web: www.ieee.org/scv/embs

Eben Kermit is a biomedical engineer and long time member of the IEEE/EMBS Santa Clara group where he has held various roles including chairman. He is the manager of field service for Hoana Medical, a medical device start-up company headquartered in Honolulu, Hawaii.

The initial concept of using pressure sensors for physiological monitoring came from the CEO and founder, Patrick Sullivan, who recognized the potential for using available technology for a novel application. Dr. Sullivan is a physicist and visionary, who has a extensive history of applied research in remote sensing and sensor technology.

Mr. Kermit joined Hoana in late 2005 and has contributed to the development and clinical evaluation of the LG1 system which is now in commercial distribution. He holds an MSEE from California State University - Sacramento

Med/Surg patients are at risk in hospitals due to inadequate monitoring and failure to rescue. There is a continuing trend to move patients out of ICU beds and into med/surg areas earlier than in the past. We also face a looming nursing shortage, making these busy caretakers responsible for a greater number of patients while at the same time these patients may be at an increased acuity level. Many patients will enter the hospital under increasingly challenging conditions for resources. The E.R., the O.R. and ICU all have a low staff-to-patient ratio and all routinely use physiological monitoring (ECG, NIBP, Respiratory Rate, Temperature, Pulse Oximetry, etc.) as an adjunct to clinical assessment by caregivers. These monitored parameters, also referred to as "vital signs" form a basis for both patient care and patient wellness. Physiological data are frequently used to confirm status or as an indication for clinical intervention. One significant point that differentiates these (E.R, O.R and ICU patients), is that they are mostly non-ambulatory and are confined to bed, where physiological monitoring can be done directly.

It is a rare case for a patient to be discharged directly from the ICU. In most cases, the patient is staged through a med/surg unit or step-down care area prior to discharge or transfer. On the med/surg floor, the staff-to-patient ratios increase relative to the ICU. Caregivers are responsible for more patients than their colleagues in the ICU. The intervals between assessments become less frequent. Also, the level of patient activity and mobility increases, as these patients recover strength and function. The challenge for physiological assessment is make meaningful measurements that augment clinical care without restricting patients via electrodes, wires, cuffs or other sensors that "tether" them to the equipment. The LG1™ system has been designed to provide basic information (heart rate and respiratory rate) from patients who are in beds with a specially equipped mattress cover.

The LG1 Intelligent Medical Vigilance™ System consists of two components: the Bedside Unit and the Passive Sensor Array (PSA). The Bedside unit houses the electronics, keypads and display, while the PSA consists of a mattress "coverlet" and an array of thin, flexible, sensors. These embedded sensors provide information from the patient lying in the bed without restriction. Proprietary algorithms translate the "raw" data into measured heart rate, respiratory rate, and bed exit status (in-bed sensor). The Bedside Unit displays these data and interfaces with the hospital's existing nurse call system.

WEDNESDAY May 16SCV Engineering in Medicine and Biology


Power System Harmonics Mitigation for Industrial

Applications

Speaker: Ben Banerjee, Power Quality Sales Application Engineer, Square D Company

Time: No-host social at 5:30 PM; Presentation at 6:15 PM; Dinner at 7:15 PM Presentation continues at 8:00 PM

Cost: $20 for IEEE members; $25 for non-members

Place: Marie Callender's Restaurant - The Garden Room; 2090 Diamond Blvd, Concord (near Concord Hilton Hotel)

RSVP: Please make reservations by May 16, by contacting Gregg Boltz at [email protected] or telephone (925) 210-2571

Web: www.e-grid.net/docs/0705-oeb-ias.pdf

B. Ben Banerjee (IEEE M’ 72) holds a B.E.E degree from the University of Calcutta, India and M.E.E degree from the University of South Carolina, Columbia, SC. Presently, he is working as Power Quality Sales Application Engineer in the PQ Solution Group of Square D Company, San Francisco Field Office. Prior to that, he worked for seventeen years as Power Conditioning & Advanced Motor-Drives Manager, in the Power Quality Business Group of Electric Power Research Institute (EPRI), Palo Alto, where he was responsible for technology & application development for power quality mitigation hardware system, advanced energy storage for power quality solutions, and advanced motors and drives system for end-use sectors. Prior to joining EPRI, he was Engineering Manager for Square D Company, Columbia, SC. In this position, he was responsible for the design and application of products such as LV and MV MCC, motor controllers for material handling, and VFDs. He has participated in NEMA Standards Subcommittees, organized EPRI-sponsored National motors & Drives Steering Committee, and is the author/ co-author of several IEEE technical papers. His work at EPRI has generated more than thirty patents for EPRI and about eighty EPRI technical reports.

Typical power distribution systems at industrial facilities contain substantial non-linear loads. For example, a typical Water/Wastewater (W/WW) facility will have several electric motors as a large percentage of connected loads. In order to achieve energy conservation and mainly for process improvement and automation, many of these electric motors are fed by Variable Frequency Drives (VFDs). Depending upon the type and size of W/WW facility, one may see Ozone Generator System (OGS), UV System (UVS), and other Renewable Energy Measures like Solar Electric (Photovoltaic System or PV) as connected loads. The VFDs, OGS, UVS, and PV are all Power Electronics based equipment, non-linear in nature, and are harmonics-producing loads. This presentation will look into the power system harmonics present in industrial facilities, specifically covering topics such as:

• Definition of Non-Linear Loads • Harmonics Fundamentals • Sources & Effects of Harmonics • 6-Pulse & 18-Pulse VFDs • IEEE 519 Harmonics Standard • Various cost-effective mitigation techniques • Other application issues

THURSDAY May 17OEB Industry Applications


Active Filters, NICs and NACs Speaker: Mr. Allen Podell, Podell Consulting Time: Refreshments/networking at 6:00 PM, talk

at 6:30 PM Cost: none Place: National Semiconductor Building E

Auditorium, 2900 Semiconductor Dr., Santa Clara

RSVP: by email to [email protected] Web: www.ewh.ieee.org/r6/scv/ssc

Allen Podell, an IEEE Life Fellow, has designed

monolithic and discrete circuits on gallium arsenide, silicon, sapphire, and plastic. With a solid foundation in device-circuit interaction, he specializes in the practical realization of modern circuit techniques. An author of over 70 technical papers, he founded three companies (Anzac Electronics, Podell Associates, and Pacific Monolithics) and he holds 60 US patents ranging from IMPATT diodes, silicon power transistors, and 3-decade bandwidth microwave components to stereo demodulators, food processors, pasta makers, antennas, gallium arsenide integrated circuits- and more recently, high power, wideband components. Previously, as VP of Technology at Besser Associates and later at Podell Consulting, he has taught advanced wireless design courses and provided consulting services from Turkey to Taiwan.

As circuit designers close in on their goal of putting

the entire universe on a chip, there still remains a problem with filtering. The environment, ever denser with signals of uncoordinated, diverse modulation schemes, demands that reliable techniques for separating out the desired signals be used. Often these filters take more space than the remaining circuitry. IC designers are legislating that the laws of physics be rewritten to enable their miniaturization quest to be realized, and the government is listening. NICs, NACs, and various active filter techniques enable lossless filters and wideband antennas that fit on the head of a pin. Are there limitations to these active techniques, or will technology conquer all? Is conservation of energy out of date? Using a little mathematics and basic theory, the talk will try to convey an intuitive understanding of active filter limitations. Finally, a harmonic balance simulator will be used to validate the ideas presented, and to show how close to the limits we can come in practice.

THURSDAY May 17SCV Solid State Circuits


IEEE GOLD Networking night at Noe's

Event: the opportunity to connect and network with

fellow IEEE Graduates Of the Last Decade Time: 6:30 PM Cost: none; food and drink will be provided. Place: Noe's in San Francisco, 1199 Church St (at

24th), San Francisco RSVP: by email to [email protected] Web: Alex Goldhammer, [email protected]

Don't miss out on this fun event and the

opportunity to connect and network with fellow IEEE Graduates Of the Last Decade (GOLD). Food and drink will be provided.

Email Alex for full details!

THURSDAY May 17SF Grads of the Last Decade (GOLD)


LEOS 30th Anniversary Program: A Conversation with Dr. Townes,

Nobel Laureate

Speakers: Dr. Charles H. Townes, UC-Berkeley (retired), with Prof. Anthony E. Siegman, Stanford Univ, and Prof. Elsa Garmire, Dartmouth Univ

Time: Social/refreshments at 6:30 PM; presentations at 7:30 PM

Cost: $20, through the MIT Alumni registration service (click on "nonalumni")

alum.mit.edu/smarTrans/user/Register.dyn?eventID=13242&groupID=154

Place: PARC Auditorium, 3333 Coyote Hill Blvd., Palo Alto

RSVP: no walk-ins; by May 20, preregister at MIT Alumni registration service (above)

Web: www.ieee.org/scv/leos

Prof. Anthony Siegman, Stanford University, Past President, Optical Society of America (1999), received undergraduate and graduate degrees from Harvard, UCLA and Stanford, and then served on the Electrical Engineering and Applied Physics faculties at Stanford from 1956 through 1998. During his career he supervised some 40 PhD students, wrote three books and many technical papers including a widely known text and reference book on “LASERS,” and received many professional honors including election to the National Academy of Engineering in 1973 and the National Academy of Sciences in 1988. Following his retirement in 1998 he served as president of the Optical Society of America and has since been engaged in technical writing, professional society activities, and technical and legal consulting.

Prof. Elsa Garmire, Professor of Engineering, Dartmouth, Past President, Optical Society of America (1995), received her A.B. Physics at Harvard University 1961 and Ph.D., Physics at M.I.T. 1965 as a student of Dr. Townes. After post-doctoral work at Caltech, she joined the University of Southern California where she was named Professor of Electrical Engineering and director of the Center for Laser Studies. She came to Dartmouth's School of Engineering in 1995 and served for 2 years as dean before making the decision to shift her focus back to research and teaching. Her honors include American Physical Society (1994) Fellow, National Academy of Engineering (1989) Life Member, Institute of Electronics and Electrical Engineers (1980) Fellow and Life Member and Optical Society of America (1981) Fellow. She holds several patents on optical technologies.

Her research interests include non-linear optics; integrated optics and semiconductor photonic devices; lasers; electro-optics; and fiber optics.

Educated at Furman University, Duke University and Caltech, Dr. Charles Townes was a member of Technical staff of Bell Telephone Laboratories from 1933 to 1947. He worked extensively during WWII on radar bombing systems. Joining the physics faculty at Columbia University in 1948, he applied microwave techniques from WWII radar research to spectroscopy.

His conceptualization of the MASER in the early 1950’s and his demonstration of the first amplification and generation of electromagnetic wave by stimulated emission was achieved in 1954. Working with Dr. A. L. Schawlow, they then showed, in an important paper in the late 1950’s, that the maser principle could be extended to the optical and infrared region. The first optical maser (which became known as the laser) was achieved in 1960 and launched one of the greatest technological innovations of the past century. .

After serving in Washington at the Institute for Defense Analysis from 1959 to 1961, he was appointed Provost and Professor of Physics at MIT in 1961. In 1967 he was appointed University Professor at UC-Berkeley, a post he holds to this day.

In addition to the 1964 Nobel Prize in Physics and 27 honorary degrees, Dr. Townes recently received the Templeton Prize for contributions to understanding of religion.

His 1964 Nobel citation reads: "Fundamental work in the field of quantum electronics, which has led to the construction of oscillators and amplifiers based on the maser-laser principle"

TUESDAY May 22SCV Lasers and Electro Optics


Lighting TVs and Screens with Lasers

Speaker: Jean-Michel Pelaprat, CEO, Novalux Time: Pizza and drinks at 6:30 PM; Presentation

at 7:00 PM Cost: $5 for members, $10 for non-members Place: Oak room at HP, 19447 Pruneridge Avenue

(Building 48), Cupertino RSVP: not required Web: ewh.ieee.org/r6/scv/ce

This talk is about how lasers will be used to bring a

new level of performance and reliability to video projection systems used in TVs and even large screen digital cinema theaters.

TUESDAY May 22SCV Consumer Electronics


Synergistic Integration of NV Flash and Hard Disk Drives:

Creating the Hybrid HDD (HHDD) Speaker: Debasis Baral, HDD Labs, Samsung

Information Systems America Time: Cookies and drinks at 7:30 PM;

Presentation at 8:00 PM Cost: none Place: KOMAG, 1710 Automation Parkway,

San Jose RSVP: not required Web: www.ewh.ieee.org/r6/scv/mag

Dr. Debasis Baral received

his B.Sc and M.Sc degree in Physics from Presidency College, Calcutta and Delhi University respectively. Subsequently he joined the Materials Science department of Northwestern University, Illinois and received his Ph. D degree for his work on mechanical, magnetic and thermoelectric properties of compositionally modulated (multi-layer) thin metallic films. Debasis came to the Valley in 1983 and worked for the last 24 years at Memorex, Maxtor, Conner Peripherals, Western Digital and Samsung Information Systems America. Currently he is Vice President of SISA - HDD labs and oversees development of high-capacity 3.5" drives and drive integration technologies for all form factor drives. He has published several papers and patents related to disk drive technology.

Recently Samsung has introduced Hybrid Hard Disk Drives (HHDD) in the market. These drives have integrated non-volatile flash memories with rotating disk drives and have shown better user experience with Microsoft’s latest OS -Vista. In this presentation, we will explain basic the principles of integration and operation of the HHDD and discuss advantages and disadvantages of using flash memories along with large-capacity hard drives. Finally we will review competing disk drives - SSD (Solid State Drive), HDD (Hard Disk Drive) and HHDD (Hybrid Hard Disk Drive) and their roles in user applications.

TUESDAY May 22SCV Magnetics

VOICE COIL MOTORS Design - Control - Fabricate - Test

J. Arthur Wagner, Ph.D. 1649 Fair Orchard Ave.

San Jose, CA 95125

[email protected] (408) 269-7044 (408) 206-3049 cell


How Did it All Start? Computer History Museum Tour

Docents: trained tour guides from the Museum Time: Social and dinner at 5:45 PM with docents;

Tour at 7:00 PM Cost: for dinner, no cost for tour Place: dinner at Fiesta Del Mar Restaurant, 1005

N. Shoreline Blvd., Mountain View; Tour at the Computer History Museum, 1401 N Shoreline Blvd, Mountain View

RSVP: none for dinner, but required for tour, to Gary Eldridge at [email protected]

Web: www.ewh.ieee.org/r6/scv/pses

The IEEE PSES SVC chapter has arranged a

special guided tour of the Computer History Museum. Today’s computers are ubiquitous and generally very safe. Taking a look at the historical record can tell us how that has changed – for the better. It also may throw light on the reasons for some of the ITE safety requirements we encounter and deal with today.

The mission of the Computer History Museum is to preserve and present for posterity the artifacts and stories of the information age. As such, the Museum plays a unique role in the history of the computing revolution and its worldwide impact on the human experience.

Established in 1996, the Computer History Museum is a public benefit organization dedicated to the preservation and celebration of computing history. It is home to one of the largest collections of computing artifacts in the world, a collection comprising over 13,000 objects, 20,000 images, 5,000 moving images, 4,000 linear feet of cataloged documentation and 5,000 titles or several hundred gigabytes of software.

In addition to tours of its extensive collection -- including pre-computing objects, software, hardware and underlying technology, graphics systems, networking, Internet, and computing precursor systems -- the Museum's first phase programs include public lectures, seminars, workshops, and artifact restoration and other volunteer-led projects.

There is limited capacity, so sign up early. Note: Because the tour is scheduled for 7:00 pm,

please be punctual! We will not have the usual business meeting and announcements.

TUESDAY May 22SCV Product Safety Engineering

MET Laboratories

EMC – Product Safety

US & Canada

• Electromagnetic Compatibility • Product Safety Cert. • Environmental Simulation • Full TCB Services • Design Consultations • MIL-STD testing • NEBS (Verizon ITL & FOC) • Telecom • Wireless, RFID (BQTF & EPCglobal Test Lab)

Facilities in Union City and Santa Clara

www.metlabs.com [email protected] 510-489-6300


Arc Flash Software

Speaker: Chet Davis, President, ESA Time: Social at 5:30 PM; Presentation at 6:00 PM,

dinner at 7:00 PM Cost: $20 for dinner Place: Sinbad's Restaurant, Pier 2 on the

Embarcadero, San Francisco RSVP: by email to Jack Lin, [email protected] Web: www.ewh.ieee.org/r6/san_francisco/ias

More details on the website.

TUESDAY May 22SF Industry Applications


Volume Production of Ultra-Thin Chips: Thinning and Singulation

Speaker: Werner Kröninger, Infineon Technologies

(Regensburg, Germany) Time: lunch at 11:45 AM, Presentation at

12:15 PM Cost: $15 for lunch Place: Ramada Inn, 1217 Wildwood Ave (Fwy 101

frontage road near Lawrence Expy), Sunnyvale

RSVP: through PayPal on website, or by email to John Jackson, [email protected]

Web: www.cpmt.org/scv Werner Kröninger received his masters degree in physics from the University of Regensburg in 1989. In 1989 and 1990 he worked for the Fraunhofer Institut (ISC) in Würzburg, as scientific collaborator investigating glasses, ceramics and ormoceres (organically modified ceramics). From 1990 to 1995 he was with Rodenstock Precision Optics, Munich, developing optical systems as a member of the technology group and managing projects in the industrial optics devision. Since 1995 he has been working at Infineon Technologies, Regensburg. He worked as a senior process engineer for several front-end fields like CVD, epitaxy and tungsten. From 1997 to 2003 he was the responsible manager for preassembly. Today he is working for the corporate group responsible for new developments in wafer-finishing for logic devices as principal preassembly manager. He holds several patents and has numerous international publications.

Singulation can easily be the most critical step in semiconductor processing -- where a die is physically freed from a wafer. So much torque and force is used during this step that if precautionary steps are not taken, the freed chips may exhibit low strength and chipping damage. The process of singulation is more critical as wafers become more packed, larger in size, thinner and filled with fragile layers. Driven by stacked die and miniaturization, the industry has moved towards thinner silicon wafers of less then 100um in thickness. Singulation of highly thinned wafers without chipping with high die strength at high throughput rates can be a real challenge. Engineers must establish a delicate balance between conservation of silicon real estate packing up the streets and high yield singulation. Has conventional rotary-blade dicing reached its limit with the advent of extremely thin, highly processed and embrittled wafers? Will laser dicing take over? How about separating by thinning? Dice before Grind (DBG) promises to be a reliable method to singulate highly thinned and fragile dies. DBG works by reversing the backgrind-to-dicing process flow and instead the wafer is ground after dicing. This brings a paradigm change. Superior strengths on ultrathin chips in mass production have been achieved. The presentation will focus on the many challenges of transferring thin silicon chips in high-volume production. Please note that Werner Kroninger is instructor for a half-day Short Course following this lunch talk. Register for both the lunch talk and Course! See:

Page 8 in this GRID

THURSDAY May 24SCV Components, Packaging and Manufacturing Technology


Designed Experiments and Reliability

Speaker: Ed Russell, National Semiconductor Time: Refreshments at 6:30 PM; Presentation at

7:00 PM Cost: none Place: Oak room at HP, 19447 Pruneridge Avenue

(Building 48), Cupertino RSVP: not required Web: www.ewh.ieee.org/r6/scv/rl/events.htm

Ed Russell is a statistician at National Semiconductor in the SPICE Modeling group. He is currently working on analysis of electrical design rules and corner models, and is beginning implementation of statistical procedures for analog design. Prior to working at National, Ed was a statistician at Sun Microsystems where he developed and taught statistical procedures for 65nm and 45nm CMOS design. Before joining Sun, he served as the Director of Reliability for Cypress Semiconductors and, in addition, provided company wide statistical consulting with a general focus on test, product characterization, and process development for new technology. Ed also has held various management and individual contributor roles with AMD in both Austin and Sunnyvale working principally in reliability and yield improvement. While at AMD, Ed set up several SPC programs in the product lines, test, and logistics and served as the statistical programs manager at Sematech on assignment.

In addition to his role as a statistician in the semiconductor industry, Ed was Chevron’s and Gulf Oil’s expert in 3D signal processing, worked on evaluating the performance of the US High Level Nuclear Waste Repository, and has been heavily involved in software development and systems analysis. Ed received an MS degree in Mathematical Statistics from Purdue University with a concentration in Tests of Hypothesis and Decision Theory. After graduation, he continued his education with a focus on Biostatistics at the University of Washington, Multivariate Statistics at Ohio State, and Geophysics at The University of Houston.

Generally, the goal of a reliability analysis of

lifetime data is to develop an estimate of how failures occur over time for a family of stress conditions. In either software or hardware reliability, experiments can be performed to determine if two or more alternatives (of e.g.: process, procedures, or design) may lead to significantly different reliability in a product. The speaker first presents a type of designed experiment for a very unusual setting -- choosing a procedural behavior among all possible procedural behaviors to optimize a general binary outcome to a 1 state (success or win) in the presence of multiple unknown countering procedures attempting to force a 0 state (failure or loss).

Initially, it's not at all clear that the subject is suitable for designed experiments of any kind due to extremely long runtimes, an environment which actively changes over time, and that there are typically between 2100 to 23000 likely micro-behaviors at each stage of approximately 400 stages, most likely all correlated to some extent in both instance and across time, which may be considered the X's. To make matters even worse, the Y for which it is desired to optimize the behavior is not at all obvious. Should this setting be considered a reliability problem (failures do occur in time) or some other kind of experiment? The speaker shows how to cut through the muck and redefine the problem in a tractable manner.

The subject of the experiment is: How to win a "turns" based computer game -- at the highest level of the game -- in just 8 "runs" of the game. Given that a single game could take weeks to complete, 8 runs is very "expensive." Is it possible to reduce the "cost?" The concepts behind setting up a similar type of experiment with multiply censored data will be addressed and an analysis will be demonstrated. Finally, a few comments will be made on better methods for software and hardware design using statistical procedures.

WEDNESDAY May 30SCV Reliability

ANSYS Channel Partner

• Multiphysics, Multidisciplinary Engng • CFD, Stress, Heat Transfer, Fracture • Fatigue, Creep, Electromagnetics • Dynamics, Design Optimization • Linear/Nonlinear Finite Element Analyses

Ozen Engineering (408) 732-4665

[email protected] www.ozeninc.com


The Renaissance of Nuclear Power

Speakers: Professor Jasmina Vujic, Department of

Nuclear Engineering, UC Berkeley, and Daniel Hirsch, lecturer in nuclear policy, UC Santa Cruz

Time: Social at 5:00 PM, dinner at 6:00 PM, Presentations and panel at 7:00 PM

Cost: $30 for IEEE members, $35 for non-members, $15 for Students (thru May 18)

Place: Monte Cristo Cafe. 4 Embarcadero Center, San Francisco (validated parking)

RSVP: reservation form to Jon Eric Thalman, [email protected]

Web: www.ewh.ieee.org/r6/san_francisco/pes

Professor Jasmina Vujic is Chair of the Department of Nuclear Engineering at UC Berkeley. She teaches undergraduate courses in nuclear engineering, nuclear reactor theory, and radiation protection and control; as well as graduate courses in nuclear reactor theory and numerical methods in reactor design and analysis. Her research interests include methods for the neutronic analysis of nuclear reactors, radiation shielding, and medical applications of radiation; neutron and photon transport theory; and reactor core design and analysis.

Daniel Hirsch is a lecturer in nuclear policy at the

University of California, Santa Cruz, where he founded and was the first Director of the Stevenson Program on Nuclear Policy. He is also President of the Committee to Bridge the Gap, a 37-year-old non-profit public policy organization focused on issues of nuclear safety, waste disposal, proliferation, and disarmament.

With growing concern about increasing carbon emissions and the potential for global warming, interest is increasing in the development of nuclear power as a source of carbon-free electrical energy. We have invited two experts in the field to share disparate insights and perspectives about the future of nuclear power in California and the nation.

Please download the registration and meal selection form from the website and make your payment prior to the dinner.

WEDNESDAY May 30SF Power Engineering


Multicore: the New Face of Computing --

Promises and Challenges Speakers: Professors and practitioners Time: Registration at 8:30 AM; program from 9:00

AM - 4:30 PM Cost: $45 for IEEE members, $55 for non-

members, $25 for Students, higher on-site (includes lunch)

Place: Stanford's Braum Auditorium RSVP: please reserve on the website Web: www.natea.org/sv/conferences/nfic/

2007/nfic_2007.php

This joint IEEE-NATEA conference on an emerging technology is aimed to provide IEEE and NATEA members with an inexpensive but solid overview of a technology that may affect their work and careers in the near future. This annual Saturday conference series has been traditionally held at Stanford on a Saturday. This year the date is June 2nd at the Bio-X facility or Braun Auditorium (TBD). Over the past 8 years we have covered such topics as RFID, SOC, Bioinformatics and Nanotechnology.

With the advent of the Sony PS3 and its utilization of a powerful multicore technology, new opportunities for other non-game scientific and technology applications present themselves. To date there has been some appreciation of this new and significant change in high-end computation. Utilization in such research as protein folding has been suggested. This conference seeks to summarize where this technology stands and what issues must be addressed to bring the exciting and powerful world of multicore computing to fruition in the scientific and technical communities to unleash its promise.

The conference will present a technical overview of the hardware and software issues involved in this significant change in computing including such issues as compilation, scalability graphics co-processing and potential applications in the scientific domain.

See the website for the full program, or contact Dale Gutierrez at [email protected].

SATURDAY June 2SCV Computer


uPILR MicroContacts: A Next-Generation Chip-Scale

Packaging Solution Speaker: Dr. Belgacem Haba, Tessera, Inc. Time: 6:30 PM dinner (optional); 7:30 PM

Presentation Cost: Seated dinner served at 6:30 - $25 if

reserved by June 11; $30 after & at door Place: Ramada Inn, 1217 Wildwood Ave (Fwy 101

frontage road near Lawrence Expy), Sunnyvale

RSVP: through PayPal on website, or by email to Janis Karklins, [email protected]

Web: www.cpmt.org/scv Dr. Bel Haba joined Tessera as a Fellow in October 2002 and became CTO of Advanced Packaging and Interconnect in April 2006. He is responsible for overseeing next-generation research and development activities for Tessera, Inc. Dr. Haba is also a founder of SiliconPipe Inc., a high-speed interconnect start-up company based in Silicon Valley. Prior to that, he managed the packaging research and development division at Rambus. From 1991 to 1996, he managed advanced research and development projects at the NEC Central Research Laboratories in Japan and, prior to that, worked for IBM at its T.J. Watson Research Center in New York. During his tenure at NEC and IBM, Dr. Haba's activities included the applications of lasers in the field of microelectronics. Dr. Haba received his bachelor's degree in solid state physics from the University of Bab-Ezouar, Algeria in 1980. He holds two master's degrees in applied physics, materials science and engineering from Stanford University, where he also earned a Ph.D. in materials science and engineering in 1988. Dr. Haba holds 85 U.S. patents, and over 130 worldwide patents and patent applications. He has authored numerous technical publications and has also participated in many conferences worldwide

Hand-held communication and entertainment products will continue to dominate the consumer markets worldwide and, with each generation offering more and more features and/or capability, system level integration and miniaturization becomes more of a priority. And even though the actual applications and functionality of the new product offering expands, the customer is expecting each generation to be smaller and lighter that its predecessor. A number of single-die and stacked-die package innovations have been developed for this broad market but many supplier companies are not meeting acceptable manufacturing yields and the difficulty of simultaneous testing of multiple mixed-die technology is not always practical. Without implementing more innovative package methods, the functional capability of the newer generation of hand-held and portable products may never reach expectation or achieve manufacturing cost objectives. The challenge manufacturers face when competing in the world marketplace is to offer a product that will meet all performance and functionality expectations without increasing product size or cost. Increased electronic functionality can be achieved through the development of more complex silicon integration but that route generally requires a great deal of capital resources and an excessive amount of time. Multiple-die package concepts are often proving superior to the system-on-chip alternative because it minimizes risk and has the potential for economically integrating several different but complementary functions. The information presented in this paper will review several package-on-package configurations and introduce a new packaging technology. A non-solder ball package, called "MicroContact", is based on a new substrate fabrication process developed to improve IC package density and circuit routing efficiency. In addition, the basic MicroContact package assembly methodology will be described and examples of high density stacked memory and mixed function variations shown. We will discuss the MicroContact effect on pitch, socketless testing, low profile, and reliability especially on lead free drop test.

WEDNESDAY June 13SCV Components, Packaging and Manufacturing Technology


IEEE GOLD Networking Event & Hike at Land's End

Event: Come explore the SF coast and the Cliff

House nearby. Time: 2:00 PM Cost: none Place: parking lot at Point Lobos Ave. and Merrie

Way, SF RSVP: by email to [email protected] Web: Alex Goldhammer, [email protected]

Come explore the beauty of the San Francisco

coast while meeting up with fellow IEEE Graduates Of the Last Decade (GOLD). We'll spend some time after the hike at the Cliff House nearby.

Send email to Alex Goldhammer for details!

SUNDAY July 15SF Grads Of the Last Decade (GOLD)

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