greendroid ppt
TRANSCRIPT
Introduction
• The GreenDroid mobile application processor is a 45-nm multicore research prototype that targets the Android mobile-phone software stack.
• It can execute general-purpose mobile programs with 11 times less energy than today’s most energy-efficient designs, at similar or better performance levels.
Working
It does this through the use of ahundred or so automaticallygenerated, highly specialized, energy-reducing cores, called conservationcores.
Major technological problem for
Microprocessor Architects
Necessity
• A key technological problem for microprocessor architects is the utilization wall.
• The utilization wall says that, with each process generation, the percentage of transistors that a chip design can switch at full frequency drops exponentially because of power constraints.
• A direct consequence of this is Dark Silicon
• Dark Silicon—large swaths of a chip’s silicon area that must remain mostly passive to stay within the chip’s power budget.
• Currently, only about 1 percent of a modest-sized 32-nm mobile chip can switch at full frequency within a 3-W power budget.
• With each process generation, dark silicon gets exponentially cheaper, whereas the power budget is becoming exponentially more valuable.
What is Power Budget ??
• A power budget shows where all the possible power will be used by a device to by breaking it down into components and categories.
• In some situations, you might be told up front that you will have 3W available to run your design.
• However, sometimes as designers start by calculating the total power a system needs and then taking actions such as replacing parts or redesigning circuits to cut back power to an acceptable level.
The Utilization Wall
• Scaling theoryTransistor and power budgets no longer balanced
Exponentially increasing problem!
Classical scalingDevice count S2
Device frequency S
Device power (cap) 1/S
Device power (Vdd) 1/S2
Utilization 1
Leakage limited scalingDevice count S2
Device frequency S
Device power (cap) 1/S
Device power (Vdd) ~1
Utilization 1/S2
Expected utilization for fixed area
and power budget
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
90nm 65nm 45nm 32nm
The Utilization Wall
• Experimental results• Replicated small data path
• More ‘Dark Silicon’ than active
• Observations in the wild• Flat frequency curve
• “Turbo Mode”
• Increasing cache/processor ratio
Utilization @ 300mm2
& 80w
3.3%
6.5%
17.6%
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
90nm
TSMC
45nm
TSMC
32nm
ITRS
Utilization Wall: Dark Implications for Multicore
4 cores @ 3 GHz
4 cores @ 2x3 GHz
(12 cores dark)
2x4 cores @ 3 GHz
(8 cores dark)
(Industry’s Choice)
.…
65 nm 32 nm
.…
.…
Spectrum of tradeoffs
between # cores and
frequency.
e.g.; take
65 nm32 nm;
i.e. (s =2)
Key Insights
The research leverages two key insights:
• First, it makes sense to find architectural techniques that trade this cheap resource, dark silicon, for the more valuable resource, energy efficiency.
• Second, specialized logic can attain 10X to 1,000X better energy efficiency over general-purpose processors.
Approach
• The approach is to fill a chip’s dark silicon area with specialized cores to save energy on common applications.
• These cores are automatically generated from the code base that the processor is intended to run—that is, the Android mobile-phone software stack.
• The cores feature a focused re-configurability so that they can remain useful even as the code they target evolves.
Dark Silicon
The GreenDroid architecture
• The GreenDroid architecture uses specialized, energy-efficient processors, called conservation cores, or c-cores to execute frequently used portions of the application code.
• Collectively, the c-cores span approximately 95 percent of the execution time of team’s test Android-based workload.
The high-level architecture of a GreenDroid system
The system comprises an array of 16 non-identical tiles.
Each tile holds components common to every tile—the CPU, on-chip network (OCN), and shared Level 1 (L1) data cache—and provides space for multiple conservation cores (c-cores) of various sizes
The c-cores are tightly coupled to the host CPU via the L1 data cache and a specialized interface
Conservation Cores
• Specialized cores for reducing energy• Automatically generated from hot
regions of program source
• Patching support future proofs HW
• Fully automated toolchain• Drop-in replacements for code
• Hot code implemented by C-Core, cold code runs on host CPU
• HW generation/SW integration
• Energy efficient• Up to 16x for targeted hot code
D cache
Host
CPU(general purpose)
I cache
Hot code
Cold code
C-Core
Figure shows the projected energy savings in GreenDroid and the origin of these savings.
The savings come from two sources
• First, c-cores don’t require instruction fetch, instruction decode, a conventional register file, or any of the associated structures. Removing these reduces energy consumption by 56 percent.
• The second source of savings (35 % of energy) comes from the specialization of the c-cores’ data path.
• The result is that average per-instruction energy drops from 91 pJper instruction to just 8 pJ per instruction.
20
Conclusions
• Over the next five to 10 years, the breakdown of conventional silicon scaling and the resulting utilization wall will exponentially increase the amount of dark silicon in both desktop and mobile processors.
• The GreenDroid prototype demonstrates that c-cores offer a new technique to convert dark silicon into energy savings and increased parallel execution under strict power budgets.
• The estimate that the prototype will reduce processor energy consumption by 91 percent for the code that c-cores target, and result in an overall savings of 7.4 X.
This the PPT of GreenDroid
• Thanks For Downloading the PPT for Documentation of Greendroid
Go to Techrulz.com.
Here you will find the Documentation Greendroid.
Click on the link for Documentation
http://www.techrulz.com/2015/02/greendroid-documentation-ppt-doc-free-download.html
