gluex collaboration oct '06 c. cuevas 1 topics: projects and progress 250msps flash adc energy...

GlueX Collaboration Oct '06 C. Cuevas

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Topics: Projects and Progress

250Msps Flash ADCEnergy Sum Module

The Bigger PictureDAQ/Electronics Work PlansOverall Electronic ‘System’

Concerns & Issues

GlueX Collaboration MeetingJefferson Lab

14-16 October 2006

ELECTRONICSR. Chris Cuevas

Jefferson LabPhysics Division

Group Leader -- Fast Electronics


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Flash ADC Development

• At the IU Electronics meeting in April 2006 the detailed requirements were reported as a “work in progress”:

• We have completed all of the design requirements for the prototype and created several documents:

1. 250Msps Flash ADC Module Specifications

2. Flash ADC FPGA requirements (V4LX25)

a) Data Processing and Trigger Window Latency

b) Energy Sum (8 channels per FPGA)

c) Hit Bit Output

d) Trigger Processing – Buffering up to 4 consecutive triggers without data loss

3. Flash ADC Interface and communication with FPGAs

4. Flash ADC Data format for readout

5. Flash ADC Internal Data format – On board FPGA to FPGA

6. Flash ADC Hit Bit Processing, ADC summing & MGT transmission (V4FX20)

7. Flash ADC JTAG and FPGA Eprom configuration and control


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Flash ADC Status - Prototype• Block Diagram

This diagram is not intended for extreme details, and has not been updated recently. The diagram shows the important decisions for FPGA selection and other hardware features.

• SchematicThe Schematic is a tremendous amount of effort and is 47 pages!! Clearly the work of several engineers and designers.

• Printed Circuit Board The latest layout is shown on a slide that follows. Power regulators and other power components will be finalized soon and full time work for routing will begin soon.

• ComponentsXC4VFX20 parts ordered and received. These parts have all 8 MGT units operational at 3.125Gbps. 10 bit Maxim ADC parts ordered and received. XCLX25 parts have been received. All other parts are stock items and we will purchase enough for two prototype units.


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Flash ADC Development Milestones

• This module is a very challenging design and the progress is remarkable, given that the design team members are committed to other projects also.

October 2006 -- Design Complete [ Schematic reviewed]

November-December 2006 – Final layout/Routing/Review/Order

January-March 2007 – INTENSE TESTING! This will include software development work for Coda ‘Drivers’ and Test Station.

Summer 2007 – Production modules,, “How many would you like to order?”


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Energy SUM Module Development

• The prototype module is assembled and initial testing is complete. The design engineer left the lab in August, so firmware development has not progressed.

• The energy sum prototype module will allow us to continue the research necessary to gain expertise with the new VXS, { VME with serial extensions} technology.

• We have purchased the necessary test instruments for measuring the MultiGigabit Transceivers, and have evaluated several VXS crates from different manufacturers.


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Quick VXS Review

Why VXS?

• VXS provides an infrastructure for multi-GBps switched serial technologies to compete and grow on top of VME

• Expected to extend the life of VME for decades

– Part of the VME Renaissance

• Pro’s

– Very high bandwidth

– Low latency

– Increased scalability (as compared to a bus architecture)

– Less contention (as compared to a bus architecture)

– Experiment with switched serial under the safety of the parallel bus

– Migrate from parallel bus to serial switched at one’s own pace

– Provides a platform for high availability systems – hot swap


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Quick VXS Review

VXS Backplane

VXS “Switch” Card(Jlab Energy Sum)

VXS “Payload”(Jlab fADC )


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More VXS Fun

21 Slot VXS cratefromWiener Plein & Baus

Note Switch Slots areLocated in the 1st and Last slots. VME64xSlot is included that Does not have the P0 Or MGT connector


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More VXS Fun

21 Slot VXS cratefromWiener Plein & Baus

The absolute latest In high speed serialAnalysis with digitalOscilloscope technologyWas delivered in Sept!

Tektronix 8Ghz BW Digital Serial Analyzer


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VXS Test Plan

CH1

CH16

FPGA

FPGA

FPGA

CH8

CH9

VME

VME

P0VXS

Jefferson LabFLASH ADC

PENTEK 6822 ADC

CH1

CH2

VME

VME

P0VXS

FPGA

FPGA

Jefferson LabVXS “Switch Slot”Crate SUM

“GateFlow”

High Speed Serial VITA 41 Backplane

FPGA

16 Channel Board SUM Data

DACCrate SUMTo Main Trigger


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VXS Test Plan


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VXS Testing

FIFO12 16

“0000”

12 16

“0000”

ADD

FIFO

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FIFO

TEST CODE FOR PENTEK BOARDProduced by: Doug Curry

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16

16

AURORA64

64CHIPSCOPE

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12

12

U1

U2

U1_U2_SUM

LoopbackModule in Switch Slot

ADC1(U1)

ADC2(U2)


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VXS Testing

Figure 3: VXS Loopback Waveform results (Xilinx ChipScope Pro)Test Conditions:Input ADC1: BLUE Negative exponential pulseInput ADC2: RED Negative exponential pulse; Inverted and attenuated (14db)1Mhz Input Frequency for both inputsOutput ADC1_Aurora: GREEN Data transmitted round trip for ADC1Output ADC1_ADC2_SUM: MAGENTA ADC1 + ADC2 result transmitted round tripConclusion:The backplane functions correctly for the given payload assignment. Four high speed serial ‘lanes’ are used at 2Gbps for an aggregate transfer rate of 8Gbps. The Aurora protocol appears to have a latency of approximately 400ns roundtrip, but the proper summing function occurs without error and is extremely stable. Further testing with the Pentek module is planned to achieve the maximum serial transfer rating of the Xilinx VirtexII Pro FPGA. The Jlab switch slot design will allow the testing of two Jlab flash ADC prototype

modules and the Pentek module.


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The Bigger Picture

• DAQ/Electronics Work Plans

• Hall D Electronics System Integration & Engineering

• Concerns & Issues


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• GlueX- Doc - 614

DAQ/Electronics Work Plans

*Note: Two Xilinx developmentModules received for CNU toPrototype and test crate summingInformation to Master Trigger


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Hall D Electronics System Integration & Engineering

• Engineering effort for the Electrical/ElectronicsSystems of Hall D is significant. This ‘system’ includes(but is not limited to):

1. Civil Construction – AC power distribution & grounding2. Control/Monitor systems for power supplies and instrument racks3. Beamline instrumentation4. Detector Electronics Instrumentation

a. Taggerb. Collimatorc. Start Counterd. Central Drift Chamber – Preamplifierse. BCAL – SiPMTf. FDC – Preamplifiersg. TOFh. Cerenkovi. FCAL

5. HV system(s)6. Readout electronics CABLING! (Including Low Voltage)


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Hall D Electronics System Integration & Engineering


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Concerns & Issues

• Electronics Coordinator – Paul Smith has accepted a new position at IUWill the collaboration provide a new coordinator?

• The work required for the new Readout/Daq/Trigger ElectronicsWill need additional manpower to meet proposed schedules.

• Collaborating groups have committed to building Detector systems and other important electronic projects such as the Preamplifiers,Tagger instrumentation, and 64-Channel ADC for the wire chambers. This goes back to the 1st bullet,,

• Technician position has been posted, and another Engineer position hasbeen requested,,, These positions are crucial to meet the Jlab ElectronicsPlan goals.


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Roll the credits,,,

• Design efforts are remarkable and I thought I would be appropriate toacknowledge: Fernando Barbosa Electronics GroupHai Dong Electronics GroupJeff Wilson Electronics GroupMark Taylor Electronics GroupWilliam Gunning Electronics GroupEd Jastrzembski Daq GroupDavid Abbott Daq GroupDavid Doughty CNU

gluex collaboration oct '06 c. cuevas 1 topics: projects and progress 250msps flash adc energy...

Documents

flash adc jtag

flash adc interface

flash adc data format

maxim adc parts

flash adc internal data

control slide

energy sum module development

energy sum prototype