geostatistical inspired metamodeling and optimization of
TRANSCRIPT
GEOSTATISTICAL INSPIRED METAMODELING AND OPTIMIZATION OF
NANOSCALE ANALOG CIRCUITS
Oghenekarho Okobiah
Dissertation Prepared for the Degree of
DOCTOR OF PHILOSOPHY
APPROVED: Saraju P. Mohanty, Major Professor Elias Kougianos, Co-Major Professor Mahadevan Gomathisankaran, Committee
Member Robert Renka, Committee Member Barrett Bryant, Chair of the Department of
Computer Science and Engineering Costas Tsatsoulis, Dean of the College of
Engineering Mark Wardell, Dean of the Toulouse Graduate
School
UNIVERSITY OF NORTH TEXAS
May 2014
Okobiah, Oghenekarho. Geostatistical Inspired Metamodeling and Optimization of
Nanoscale Analog Circuits. Doctor of Philosophy (Computer Science and Engineering), May
2014, 100 pp., 18 tables, 57 figures, bibliography, 78 titles.
The current trend towards miniaturization of modern consumer electronic devices
significantly affects their design. The demand for efficient all-in-one appliances leads to smaller,
yet more complex and powerful nanoelectronic devices. The increasing complexity in the design
of such nanoscale Analog/Mixed-Signal Systems-on-Chip (AMS-SoCs) presents difficult
challenges to designers. One promising design method used to mitigate the burden of this design
effort is the use of metamodeling (surrogate) modeling techniques. Their use significantly
reduces the time for computer simulation and design space exploration and optimization.
This dissertation addresses several issues of metamodeling based nanoelectronic based
AMS design exploration. A surrogate modeling technique which uses geostatistical based
Kriging prediction methods in creating metamodels is proposed. Kriging prediction techniques
take into account the correlation effects between input parameters for performance point
prediction. We propose the use of Kriging to utilize this property for the accurate modeling of
process variation effects of designs in the deep nanometer region. Different Kriging methods
have been explored for this work such as simple and ordinary Kriging. We also propose another
metamodeling technique Kriging-Bootstrapped Neural Network that combines the accuracy and
process variation awareness of Kriging with artificial neural network models for ultra-fast and
accurate process aware metamodeling design. The proposed methodologies combine Kriging
metamodels with selected algorithms for ultra-fast layout optimization. The selected algorithms
explored are: Gravitational Search Algorithm (GSA), Simulated Annealing Optimization (SAO),
and Ant Colony Optimization (ACO). Experimental results demonstrate that the proposed
Kriging metamodel based methodologies can perform the optimizations with minimal
computational burden compared to traditional (SPICE-based) design flows.
ii
Copyright 2014
by
Oghenekarho Okobiah
ACKNOWLEDGMENTS
I would like to thank my major advisor Prof. Saraju P. Mohanty for the encouragement
and guidance he has given me throughout this process. His constant support and technical feed-
back have made this work possible. I would also like to thank my co-major advisor Prof. Elias
Kougianos who also encouraged and motivated me through the completion of this work. I am
also grateful for his technical guidance. I would also like to thank my committee members: Prof.
Mahadevan Gomathisankaran and Prof. Robert Renka for agreeing to review this work. Special
thanks and appreciation goes to my parents and my siblings whose constant moral support and
encouragement has helped me finish this work. I would also like to acknowledge my lab members;
Oleg, Geng, and Abir who have helped me when I had a problem or two. Our lab called NanoSys-
tem Design Laboratory (NSDL, http://nsdl.cse.unt.edu) has been an excellent work
place for my research for the last few years. I also wish to thank the staff of the Department of
Computer Science and Engineering for being very helpful and caring in times of need. Lastly, I
would like to thank God, who has been my rock through this all.
iii
TABLE OF CONTENTS
Page
ACKNOWLEDGMENTS iii
LIST OF TABLES vii
LIST OF FIGURES viii
CHAPTER 1 INTRODUCTION 1
1.1. Nanoelectronic Mixed-Signal Design: State-of-the-Art 2
1.2. Problems in Existing Mixed Signal Design 4
1.2.1. Power Consumption/Leakage 4
1.2.2. Design Effort 5
1.2.3. Process Variations 6
1.2.4. Yield/Reliability 6
1.3. Possible Solutions for Efficient Design 6
1.4. Organization of this Dissertation 9
CHAPTER 2 REVIEW OF STATE-OF-THE-ART 10
2.1. Different Metamodeling Techniques 10
2.2. Existing Mixed-Signal Design and Analysis Flows 12
2.3. Related Optimization Algorithms 13
2.4. Novel Contributions of this Dissertation 15
CHAPTER 3 GEOSTASTICAL KRIGING METAMODELING 17
3.1. Fundamentals of Geostastical Kriging Techniques 18
3.2. Types of Kriging 20
3.2.1. Ordinary Kriging 20
3.2.2. Simple Kriging 21
iv
3.3. Kriging Metamodel Generation Flow 22
3.4. Summary and Conclusion 25
CHAPTER 4 Case Study Circuits 27
4.1. Sense Amplifier 27
4.2. Thermal Sensor 31
4.3. Phase Locked Loop - PLL 34
4.4. Summary and Conclusion 35
CHAPTER 5 Kriging Metamodel Assisted Nanoelectronic Design Flows 40
5.1. Optimization Algorithms 40
5.1.1. Simulated Annealing Based Optimization (SAO) 40
5.1.2. Ant Colony Optimization (ACO) 42
5.1.3. Gravitational Search Algorithm (GSA) 43
5.2. Metamodel Assisted Design Optimization 48
5.2.1. Design and Netlist Optimization 48
5.2.2. Latin HyperCube Sampling (LHS) 48
5.2.3. Kriging Based MetaModel Generation 50
5.2.4. Design Optimization 50
5.3. Metamodel Assisted Process Variation Analysis 51
5.3.1. Proposed Kriging Bootstrapped Neural Network Metamodel 52
5.4. Metamodel Assisted Process Variation Aware Optimization 57
5.5. Summary and Conclusion 59
CHAPTER 6 Experimental Results 62
6.1. Experimental Setup 62
6.2. Validation of Metamodel Assisted Design Optimization 63
6.2.1. 45nm Sense Amplifier Design 64
6.2.1.1 Metamodel Generation and Accuracy 64
6.2.1.2 Optimization Results 68
v
6.2.2. 45nm Thermal Sensor 71
6.2.2.1 Metamodel Generation and Accuracy 72
6.2.2.2 Optimization Results 74
6.2.3. 180nm Phase Locked Loop 77
6.2.3.1 Metamodel Generation and Accuracy 77
6.2.3.2 Optimization Results 77
6.3. Validation of Metamodel Assisted Process Variation Analysis 78
6.3.1. Statistical Variation Analysis 80
6.3.2. Metamodel Generation and Accuracy 81
6.4. Results Analysis 87
6.4.1. Comparative Perspective with Related Research 87
6.4.2. Qualitative Comparison 88
6.5. Summary and Conclusion 88
CHAPTER 7 Conclusions and Future Research 90
7.1. Summary 90
7.2. Conclusion 91
7.3. Future Research 92
BIBLIOGRAPHY 93
vi
LIST OF TABLES
Page
Table 4.1. Characterization of sense amplifier FoM. 28
Table 4.2. Thermal sensor output comparison. 33
Table 6.1. Statistical analysis of the simple and ordinary Kriging predicted curve for
sample sizes of 20 and 100. 67
Table 6.2. Statistical analysis of the Kriging predicted values with metamodels created
from 100, 200 and 500 sample sizes. 72
Table 6.3. Optimized design values. 73
Table 6.4. Statistical analysis for accuracy of Kriging generated metamodel. 74
Table 6.5. Final design parameters. 76
Table 6.6. Thermal sensor output comparison. 76
Table 6.7. Statistical analysis for accuracy of Kriging generated metamodel for PLL
power consumption. 77
Table 6.8. Final optimization results for the PLL. 78
Table 6.9. Optimized parameter variables. 79
Table 6.10. Statistical analysis for accuracy of Kriging generated metamodel for PLL
power consumption. 80
Table 6.11. Statistical accuracy of Kriging generated points. 82
Table 6.12. Statistical analysis for accuracy of neural network metamodel for PLL FoMs. 82
Table 6.13. Monte carlo time analysis comparison for metamodels. 85
Table 6.14. Statistical analysis for accuracy of Kriging generated metamodel for PLL
power consumption. 86
Table 6.15. Comparative analysis of metamodel and optimization. 87
Table 6.16. Relative comparison of Kriging metamodeling techniques and gravitational
search algorithm. 89
vii
LIST OF FIGURES
Page
Figure 1.1. Nanoelectronic devices: Smart phone and watch. 2
Figure 1.2. Nanoelectronic system components. 3
Figure 1.3. Design challenges for nanoelectronic systems. 5
Figure 1.4. Fast design methods. 7
Figure 2.1. Classification of metamodeling techniques. 11
Figure 2.2. A taxonomy of existing design flow methods. 12
Figure 2.3. A classification of optimization algorithms. 14
Figure 2.4. Accuracy vs. speed of metamodeling design. 16
Figure 3.1. Geostastical Kriging and oxide thickness comparison. 17
Figure 3.2. Geostatistical Kriging metamodel generation process. 22
Figure 3.3. Proposed geostatistical Kriging metamodel generation flow. 23
Figure 4.1. A taxonomy of sense amplifier designs. 27
Figure 4.2. Sense amplifier circuit with sizes for 45nm CMOS technology. 29
Figure 4.3. Physical design of the sense amplifier circuit with 45nm technology. 30
Figure 4.4. Waveform of sense amplifier functional simulation. 31
Figure 4.5. Thermal sensor system configuration. 32
Figure 4.6. Ring oscillator schematic. 32
Figure 4.7. 10 bit binary counter. 36
Figure 4.8. 10-bit register. 37
Figure 4.9. Physical design of 45nm thermal sensor. 37
Figure 4.10. Ring oscillator frequency response versus temperature for both schematic and
physical designs. 38
Figure 4.11. High level system diagram for the PLL. 38
Figure 4.12. Physical layout design for the 180nm PLL. 39
viii
Figure 5.1. GSA: Search agents are attracted towards locations with possible quality
solutions. 45
Figure 5.2. The proposed Kriging assisted ultra-fast design optimization flow. 49
Figure 5.3. Proposed Kriging based ANN metamodel generation flow. 53
Figure 5.4. Proposed metamodel design flow. 54
Figure 5.5. Statistical variation analysis. 57
Figure 5.6. Proposed high level design flow. 58
Figure 5.7. Proposed Kriging bootstrapped ANN metamodel generation flow. 60
Figure 5.8. Proposed process variation design optimization flow. 61
Figure 6.1. Steps and tool interaction. 63
Figure 6.2. Ordinary Kriging responses using Wn as the design parameter. 65
Figure 6.3. Simple Kriging predicted outputs using Wn as the design parameter. 66
Figure 6.4. Golden surface for circuit I using and Ln and Wn as design input. 68
Figure 6.5. Golden surface for circuit II using and Ln and Wn as design input. 69
Figure 6.6. Golden surface circuit I for Kriging predicted FoM’s using 500 Ln and Wn
sample points. 70
Figure 6.7. Golden surface Circuit II for Kriging predicted FoM’s using 500 Ln and Wn
sample points. 71
Figure 6.8. GSA optimization flow. 75
Figure 6.9. GSA performance on Kriging metamodel for 45nm thermal sensor. 76
Figure 6.10. Optimization steps of the PLL. 78
Figure 6.11. Statistical analysis of the performance output for the 180nm PLL using Kriging
metamodels. 81
Figure 6.12. Comparative results with Kriging and neural network. 83
Figure 6.13. Statistical analysis of FoMs using Kriging bootstrapped trained neural network
based metamodeling. 84
Figure 6.14. Statistical analysis of FoMs using Kriging based metamodeling. 85
Figure 6.15. Statistical analysis of FoMs using neural network based metamodeling. 86
ix
CHAPTER 1
INTRODUCTION
The current trend towards miniaturization of consumer electronic devices significantly af-
fects the design complexity of such appliances. The progress of silicon process technology, as pos-
tulated by Moore’s Law has increased the number of transistor devices manufactured on a single die
or chip exponentially. The evolution of electronic devices from the first electronic general-purpose
computer in 1946 to modern desktop and laptop personal computers to now mobile computing
devices has been made possible by the progressive scaling of technology. The adoption of mo-
bile computing devices such as cell phones and tablets by consumers for obligatory daily tasks, in
turn drives manufacturers to deliver devices that can meet performance. Hence high performing
devices with increased functional complexity must be designed and be portable enough for mobile
use. Because of the all-in-one nature of these electronic devices, the circuit designs are typically
mixed signal circuits consisting of analog, digital, and mixed-signal components on a single chip.
The advancement of silicon technology enables such tasks to be met, but it also introduces new
problems such as process variation, current leakage, yield and reliability [53]. The fundamen-
tal reason is that as devices reach deep into the nanometer dimensions, the silicon structures of
the transistor devices become more stochastic in operation [77]. The integration of the different
components presents a difficult challenge for circuit designers as they take into consideration the
different design specifications that must be achieved, especially because a considerable amount of
computer simulations must be performed for exhaustive design exploration which is not afforded
by the reduced time-to-market. Research for solutions to ease the burden on the design process
while sustaining performance motivates this work.
This chapter presents a basic discussion of the relevant features of nanoelectronic mixed-
signal system design, and elaborates on the existing problems and challenges. Possible solutions
and motivations for this work are also discussed and the organization of this dissertation is high-
lighted.
1
1.1. Nanoelectronic Mixed-Signal Design: State-of-the-Art
The progress advancement of silicon technology has led the drive for the development
of many consumer and industry electronic systems, examples of which include mobile phones,
tablets, wearable devices (smart watches, Google glass, exercise bracelets), smart appliances, smart
thermostats, drone systems and many more. The current technology trend is the integration of
multi-systems into one device. For example, smart mobile phones not only function as a telephone,
but function as GPS systems, media playing and storage systems, and personal computers [43]. As
an example of a portable electronic application, figure 1.1 shows the current Samsung Galaxy Note
3 mobile phone with the Samsung Galaxy Gear smart watch [14]. This is a complex mixed-signal
system consisting of diverse components including digital processors, analog baseband circuitry,
and radio frequency communication chips.
FIGURE 1.1. Nanoelectronic devices: Smart phone and watch.
The integration of these different sub-components is the basis of analog mixed-signal sys-
tem design. Analog/mixed-signal systems-on-chip (AMS-SoCs)are systems which consist of ana-
log, digital, and mixed-signal components integrated on the same die for cost and performance
trade-offs. Figure 1.2 shows a breakdown of the components of a typical nano-CMOS AMS-SoC
system which includes digital, analog and mixed-signal devices [49]. The integration of the dif-
2
ferent components must be done efficiently and presents significant problems especially from the
analog components. Each of these components is built from different nanoelectronic technologies,
such as classical MOSFET, high-κ MOSFET, and triple-gate MOSFET. They are built from differ-
ent technology nodes based on the specification requirements of various design and semiconductor
houses.
FIGURE 1.2. Nanoelectronic system components.
State-of-the-art AMS-SoCs are of gigascale complexity consisting of transistors in deep
nanoscale dimensions. The current Intel Haswell 4th generation processor chip uses a 22nm Tri-
Gate 3D transistor technology with a 1.4 billion transistor count on 177 mm2 area. The Nvidia
GK110 graphic processing unit (GPU) consists of 7.1 billion transistors on a 28nm technology
[49]. Digital CMOS technology growth is much faster than any other technology and it is mat-
ter of time before graphene nanoribbon based FETs, tunnel FETs, or even memristors become
commercial [46]. We may see integrated circuits operating at 50 GHz speeds or even higher.
3
1.2. Problems in Existing Mixed Signal Design
The design of Analog Mixed-Signal Systems-onChip (AMS-SoCs) presents difficult chal-
lenges given the number of design specifications that must be met. The demand for smaller,
portable, and yet more powerful and efficient electronic devices continues to drive the aggres-
sive scaling of semiconductor technology design. For example, recent trends show increasing
computing power of mobile devices such as mobile phones and tablet computers. The reduced
feature sizes and increased capabilities leads to more complex designs as more subcircuit systems
are packed into a single chip. The continued progressive scaling and increasing complexity of
nanoscale technology increases the number of design factors and process parameters that affect
the performance of AMS circuits. Furthermore, designers now need to deal with issues of sub-
threshold leakage and power density. A more prominent issue which arises in designs using 65nm
technology and beyond is the issue of process variation. The effects of process variation have be-
comes especially pronounced in the deep nanometer regions. With more complex designs, there
is an increase in the number of design and process parameters that must be considered to mitigate
the issues of subthreshold leakage and process variation. SPICE computer simulations which are
used to accurately simulate the circuit design, are very computationally intensive and consume a
significant amount of time making the design process expensive. For example the complete silicon
aware simulation of a circuit system like a Phase Locked Loop (PLL) on a CAD tool could take
several days. These problems can be classified under design effort, power consumption, process
variation and design for yield and reliability. The most important challenges of nanoelectronic
circuits and systems are depicted in Figure 1.3. This dissertation deals with them with an objective
to make electronics robust, power efficient, cheaper and affordable.
1.2.1. Power Consumption/Leakage
As mobile devices continue to become more powerful and ubiquitous, the issue of power
consumption plays a major role in the design process. The battery life and power consumption
of such devices becomes a key performance metric for design [54, 52, 51]. Power consumption
in circuit design can be classified under dynamic and static power consumption. Dynamic power
occurs when transistors are actively switching, while static power consumption occurs when the
4
Nanoelectronic DesignSpace
DesignEffort
Power/Leakage
Yield/Reliability
ProcessVariation
FIGURE 1.3. Design challenges for nanoelectronic systems.
transistors are in an idle state. The most significant component of static power consumption con-
sists of leakage power due to gate capacitive currents. The continued scaling of technology has
led to a decrease in dynamic power consumption; however, static power consumption continues to
increase with technology scaling.
1.2.2. Design Effort
The design effort comprises the overall burden the designers face in the design cycle. Sim-
ulation of circuit design models with CAD tools is an accurate method of modeling in detail circuit
designs with the ability to accurately estimate performance measures. Performance measures such
as delay, cost and area are also considered when exploring the design space [48]. However, with
the progressive scaling of designs deep into the nanometer region, and the increase in the level of
details in design, the number of design points and process parameters required for accurate sim-
ulation increases dramatically; exhaustive design space exploration through computer simulations
5
has become more daunting and even impractical.
1.2.3. Process Variations
The advanced progress of design technology has led to the integration of circuit compo-
nents in the deep nanometer range. While the benefits allow for more compact and densely inte-
grated components, designs in the deep nanometer technology have a pronounced negative effect
due to process variation which only becomes worse as technology scales [47, 50]. Time delay and
power consumption are common performance measures that can be affected by process variation.
The performance measures statistically vary around the expected mean values with potentially sig-
nificant deviations. A strongly pronounced effect of process variation increases the spread of the
performance measure beyond acceptable values thus reducing the yield of the designs. Process
variations are typically grouped under random, systematic, intra-die and inter-die variations.
1.2.4. Yield/Reliability
Another challenge faced by designers is the design yield and reliability. Again, as tech-
nology shrinks in size, the designs have to be manufacturable with sufficient yield and reliability.
Due to physical limitations, dimensions in deep nanometer range become less tolerant to errors
and extra steps must be taken during the design process to ensure manufacturability.
These factors make design optimization very difficult and time consuming. These effects
also increase the already enormous time for an exhaustive simulation search of the design space
and make design optimization a very time consuming task. To increase the speed of design space
exploration, designers resort to other alternatives such as interpolating functions, fast algorithms
and metamodeling. Current techniques used to reduce simulation time include the use of meta-
modeling functions [7, 38, 5, 18, 24] and performance estimation through Monte Carlo simulation
analysis. Metamodeling has been a recently researched and applied solution to reduce the time
burden of computer simulation models while keeping the accuracy to an acceptable level.
1.3. Possible Solutions for Efficient Design
Fast design effort to reduce design cycle time for integrated circuits has always been an
active area of research. The objective has been to make design exploration fast as well as error
6
free design to reduce the nonrecurrent cost of the integrated circuits. Figure 1.4 shows a summary
of design methods to reduce the design burden of designers. Two techniques, macromodeling and
metamodeling are been shown which essentially change the representation of the circuit during the
design effort to achieve the above.
Design Solutions
Metamodeling Macromodeling
Monte Carlo
Estimates
FIGURE 1.4. Fast design methods.
Metamodeling functions are mathematical approximations of performance objectives, out-
puts, performance metrics, or figures-of-merit (FoMs) of simulated design models with respect to
design parameters [28, 7]. In essence, a metamodel of a circuit is an abstraction of the circuit de-
sign model itself, hence the “meta” term is used. The goal of using metamodeling techniques is to
replicate the simulation results of computer-aided design (CAD) or electronic design automation
(EDA) tools by abstracting the time intensity of computer simulations while accurately capturing
the effects of design details. The metamodel provides an efficient and sufficiently accurate method
for design space exploration. Response-surface modeling, linear and low-order polynomial re-
gression functions, artificial neural networks (ANNs) and Kriging based metamodels are common
forms of metamodeling techniques used [7, 60, 68, 18, 24, 78, 37].
Macromodeling on the other hand uses a simplified circuit that describes the behavior of
the circuit being designed for performance analysis [6]. This approach reduces simulation time
since the simplified circuits are not as complex and detailed. The drawback of macromodeling is
that they are simplified descriptions of the circuit and are not generally design parameter sensitive,
7
hence macromodeling based designs cannot be used for design optimization [6, 26].
Another possible solution for alleviating the design process has been the use of performance
estimation through Monte Carlo (MC) simulations. Interpolating functions, which include linear
and low-order polynomial regression techniques, are one of the most popular methods used by
designers. The accuracy and efficiency of a metamodel depends on the technique used in creating
it [24]. For instance, metamodels based on low-order polynomial regression functions deliver
accurate circuit descriptions for local spaces, however, they are not efficient when used for global
optimizations [5, 67]. Also, due to the oscillatory characteristic of polynomial fits, designs with
rapidly changing data points, as is the case with nano-CMOS designs, are not well fitted [65]. They
are not also very efficient in modeling the effects of process variation which has significant impact
on circuit designs.
When predicting the objective function, regression models assume the effects of process
variation are purely random and approximate the error equally across the design space. However
in nanoCMOS designs where the effects of process variation are very grave, this is not the case.
The effects of process variation are not purely random but they are also strongly correlated among
parameters across the local and global space. The technology scale into deep nanometer regions
significantly increases the correlation effects between parameters making it a significant issue in
design accuracy. Hence, there is a need for design methods which accurately capture and model
these effects in the design process. Kriging based metamodels, which are based on geostatistically
applications, take into account by their weighting system the correlation effects between the de-
sign parameters. Metamodeling techniques which account for the correlation effects of process
variation provide a robust metamodel which is process variation and yield aware giving designers
a greater control over the design parameters.
The work presented in this dissertation explores geostatistical Kriging based metamodel-
ing techniques for design metamodeling and optimization for analog circuit design. Kriging based
techniques generate accurate metamodels with the error due to correlation of design points taken
into consideration. Kriging techniques were originally introduced in the early 1950’s in geostatis-
tical analysis by Daniel Krige (hence the term “Kriging”), but their application has been extended
8
to many other fields [68, 31, 74] but only recently in VLSI [72, 73]. Kriging based techniques
generate interpolating functions for each estimated point using the correlation effect between de-
sign points in the local space. Each point is estimated with a unique set of weights. This differs
from conventional regression techniques because for each predicted point, a new set of weights
is calculated based on the correlations and variance of the design points in the local space. One
major improvement Kriging based techniques have compared to conventional regression is that the
estimated response of design points is the same as the actual circuit response.
With available design metamodels, designers also face the challenge of effectively explor-
ing the design space. In high dimensional parameter designs, as is the case with nanoCMOS
circuits, exhaustive search space optimization techniques are unrealistic as the search space varies
exponentially with problem size [63]. Different optimization algorithms utilized for circuit design
optimization include genetic algorithms, swarm algorithms (including particle swarm optimiza-
tion, ant colony optimization and recently Gravitational Search Algorithm), simulated annealing,
tabu search and geometric programming [8, 4, 24, 33, 66, 11, 75]. A novel design flow method-
ology which combines the Kriging generated metamodels with an optimization algorithm is also
presented as part of this work. The proposed design flow methodology is applicable to the de-
sign of nanoscale analog/mixed-signal circuits. This methodology improves process aware design
optimization reducing computational expense while providing an optimized result.
1.4. Organization of this Dissertation
The rest of this dissertation is organized as follows. Chapter 2 reviews the state-of-the-art
nanoelectronic analog/mixed-signal (AMS) circuit and system design. It also includes the meta-
modeling techniques and related optimization algorithms and novel contributions of this disserta-
tion. Chapter 3 discusses the fundamental theory and implementation of Kriging metamodeling
techniques. The descriptions of the case study nano-CMOS based circuits used for this disser-
tation are presented in 4. In Chapter 5 the design flow methodologies are presented along with
discussions of the optimization algorithms used in this research. The results and verifications of
the implementation are presented in Chapter 6. Conclusions of the research undertaken in this
dissertation and possible scope for future work are presented in Chapter 7.
9
CHAPTER 2
REVIEW OF STATE-OF-THE-ART
In this chapter, a review of current fast design methodologies is presented. The design tech-
niques discussed are primarily based on metamodeling. From the discussion presented in Chapter
1, metamodeling based techniques present some advantages over macromodeling and Monte Carlo
estimates. Metamodeling based techniques can be reused for the same circuit design with different
performance objectives. Since the metamodels are inherently mathematical models of the circuit
behavior, they are tool independent and can be used across design platforms. Fast design tech-
niques also include design methods that reduce the burden of design analysis for performance
estimation. In section 2.1, a selection of metamodeling techniques is discussed. A survey of gen-
eral design and analysis flow methods is also presented and a discussion of related optimization
algorithms commonly applied to analog/mixed signal circuits is highlighted. The last section in
this chapter outlines the novel contributions of this dissertation research work.
2.1. Different Metamodeling Techniques
The research and application of metamodeling as a design methodology has been well
documented. As designs in all engineering disciplines continue to become complex, the need to
devise more accurate metamodels for these designs continues to motivate researchers. In [44], a
analysis of various metamodeling techniques is presented detailing the origin and applicability of
metamodeling to the design and optimization of analog circuits.
The most popular metamodeling technique has been the low order , piecewise polynomial
regression [74, 24, 18, 7]. The work in [24] presents an analysis of different metamodels generated
with a range of sampling techniques to determine which combination produces more accurate
results, specifically for AMS circuits. While low order polynomial regression techniques are well
suited for generating response surfaces, they are only accurate for local design spaces modeling and
have poor fitting for global design spaces [65, 5, 37, 4]. Regression techniques average the errors
in calculating weights over the design space. This creates an oscillating effect for fast changing
data especially where the correlation error between design points varies significantly.
10
Metamodeling
Polynomial
Polynomial Basis
Functions
Non-Polynomial
Kriging
Machine Learning
Support Vector Machines
Genetic Programming
Artificial Neural Networks
Piecewise polynomial
MARS SimpleKriging
OrdinaryKriging
UniversalKriging
FIGURE 2.1. Classification of metamodeling techniques.
Artificial neural networks (ANN) have also been explored for metamodel generation [78,
37, 64, 38]. Neural networks use a learning framework to estimate the weights for creating the
metamodels. [78, 64] test the accuracy of some ANN based metamodels with well known simula-
tion problems. Research in ANNs for optimal network structures is ongoing and finds particularly
active applications in metamodeling for point targets. Metamodels based on ANNs are also com-
mon and are used in [37] for the metamodeling of discrete stochastic systems. Techniques to
improve the selection of ANN structures are presented in [37]. The use of Kriging for circuit de-
sign has been researched in [72, 73]. In [7, 5], studies on Kriging metamodeling for stochastic
simulations have been presented. Recently in [58, 60] a study of different Kriging, simple and
ordinary, is presented. Fig. 2.1 shows a taxonomy of these approaches.
11
In a comparison of selected metamodeling techniques, including 2nd order polynomial
techniques, Kriging, genetic programming (GP), Multivariate Adaptive Regression Splines (MARS),
Artificial Neural Network (ANN), and Support Vector Machine (SVM), Kriging techniques per-
form admirably but not as well as GP. In similar comparisons reported in [71, 41], a survey of
several metamodeling techniques including Response Surface Methodology (RSM), ANN, Poly-
nomial Regression (PR), SVM and Kriging has been presented. In [34], a comparison of PR, Radial
Basis Functions (RBF), MARS and Kriging techniques on a variety of test cases is presented. From
tests run, Kriging and RBF techniques on average have the most accurate metamodels. Kriging
techniques are however more suited to highly non-linear response surfaces which is the case in
nanoelectronic circuits [71].
2.2. Existing Mixed-Signal Design and Analysis Flows
The use of metamodeling for design presents an approach to mitigating the design effort
required for mixed signal systems. As was highlighted earlier, metamodeling presents an appealing
feature that allows ease of design space exploration for performance analysis. There is however
on going research on different techniques for efficient methods for fast design and exploration of
mixed-signal systems. Figure 2.2 shows a taxonomy of existing mixed-signal design and analysis
flows.
Design Flow
Analysis
Actual Netlist
OptimizationMetamodeling
BasedAlgorithm
Based
FIGURE 2.2. A taxonomy of existing design flow methods.
The standard design flow analysis which uses the actual netlist for optimization of the de-
12
sign follows the traditional design process where the netlist is extracted from the physical designs
and logical designs. It requires multiple iterations on the back-end to achieve parasitic closure
between the front-end system logical design and back-end physical layout [23]. This method,
while accurate, produces long design cycle times. Metamodel based techniques are an improve-
ment of the actual netlist optimization that eliminate the long multiple iteration cycles between
the layout and logical designs by automatic, ultra-fast exploration over the metamodels instead.
This improvement requires at most two manual layout steps. The metamodeling design flow easily
reduces the design cycle time while improving circuity yield and allows for multi-objective perfor-
mance analysis. Another design flow includes the use of optimization algorithms with specialized
techniques that aid performance estimations. Such design flow methods are usually specialized and
are not easily reproduced like metamodels. In [22], a methodology which combines response sur-
face modeling techniques with the Cornish-Fisher Expansion (CFE) is proposed to achieve closure
on performance variations through the mapping of process parameters to a quadratic model and
performing analysis with CFE. In [76], a methodology which incorporates statistical techniques
into the design process aids the estimation of temperature effects on the circuit. In [45], a design
which uses a reference transistor independent of ambient temperature is proposed. The effects of
noise and process variation are modeled into the temperature reading increasing accuracy.
2.3. Related Optimization Algorithms
Design optimization remains a prominent issue especially for analog and mixed-signal cir-
cuits for which optimal solutions are required in an efficient manner. Recent research trends steer
towards improving optimization time and efficiency, and optimizing for multi-objective functions
[25, 10, 36]. Conventional optimization algorithms include genetic algorithms, swarm intelligence
algorithms, simulated annealing, tabu search, gradient based algorithms, and linear and geomet-
ric programming [8, 4, 40, 10, 24, 57]. A broad classification of these algorithms into traditional
heuristics and intelligent population based algorithms is shown in Figure 2.3.
In [8], a comparison of simulated annealing, genetic algorithms and gradient based algo-
rithms is presented. Geometric programming is presented in [4]. This solves convex problems
deduced from circuit design equations expressed in polynomial forms. The approximations made
13
Optimization
Algorithms
Traditional
Heuristics
Intelligent
Population Based
Simulated Annealing
Tabu Search
Swarm Intelligence
Ant Colony
Artifical Bee Colony
Gravitational Search
FIGURE 2.3. A classification of optimization algorithms.
in deducing the circuit equations reduce the accuracy, even though they suits global optimizations.
In [40], orthogonal optimization techniques based on swarm intelligence are presented. In [15] an
optimization tool is presented. It uses a fast circuit simulator and optimization package. It uses
an adjoint Lagrangian method to reduce the computation time for the gradient to a single analysis.
In [42], a proposed GPU fast simulation optimization is presented. ACO, originally proposed for
discrete combinatorial problems, is also being actively explored for application in continuous prob-
lems. In [40], a swarm algorithm technique using orthogonal optimization techniques is presented.
Fast optimization algorithms based on artificial bee colonies is presented in [25]. In [10], a tech-
nique using linear programming which improves optimization time by 10% is proposed. Evolu-
tionary algorithms which operate heuristically are particularly suited for computational functions,
and achieve near-optimal solutions. Hence, there is continued research on algorithms. The gravi-
tational search algorithm (GSA) was recently proposed with a thorough performance comparison
14
with the particle swarm optimization (PSO) [63].
For optimization of analog circuit designs, evolutionary algorithms which operate heuris-
tically have generally produced very good results and hence have become very popular. Most
commonly used are genetic algorithms (GA)[8] and variations from the family of swarm algo-
rithms (including particle swarm optimization, artificial bee colonies, ant colonies and the recently
introduced Gravitational Search algorithm). Most heuristic based algorithms have no scientific or
empirical theoretical basis and as such do not guarantee singular results. They are however very
fast and efficient when applied on complex analog circuits producing near-optimal results.
2.4. Novel Contributions of this Dissertation
Minimization of power consumption in AMS circuits is very important. The challenge
for designers in the minimization of the power consumption is a trade-off with the performance
objectives of the circuit. The overlying problem the work in this dissertation seeks to solve is
reducing the design effort by reducing the required design simulation time, while maintaining or
improving design accuracy. Figure 2.4 depicts this concept of various metamodels.
The use of geostatistical Kriging methods is introduced in a design flow methodology for
AMS design optimization. Kriging techniques provide accurate response predictions and are effec-
tive for processes with correlation effects; thus they can account for correlation effects. Different
implementations of Kriging techniques, including simple and ordinary Kriging, are used for the
ultra fast generation of layout-aware accurate metamodels [60, 57]. A Kriging bootstrapped-neural
network based metamodel, which combines the accuracy and process variation characteristics of
Kriging along with ultra-fast artificial neural networks is also proposed. This methodology in-
corporates process variation analysis at two levels of design and optimization to ensure a robust
process aware design. The design metamodels are then optimized with a population based opti-
mization algorithm such as the gravitational search algorithm (GSA) or Ant Colony Optimization.
The GSA algorithm, developed in [63], is presented for optimization of AMS circuits [57]. ACO
based algorithms are also presented for optimization of AMS circuits. The efficiency of the overall
proposed methodologies is illustrated using a 45nm CMOS based sense amplifier, a 45nm CMOS
based thermal sensor and a 180nm CMOS phase locked loop (PLL).
15
FIGURE 2.4. Accuracy vs. speed of metamodeling design.
The novel contributions of this dissertation to the state-of-the-art in analog/mixed-signal
(AMS) circuit and system design are the following:
(1) A layout-accurate method for geostatistical Kriging metamodel generation of AMS blocks.
Simple and ordinary Kriging variants are presented.
(2) A novel ultra-fast but accurate layout design optimization flow for AMS components
that incorporates layout and process-aware metamodels into different levels of the design
process and fast optimization algorithms.
(3) A layout optimization techninque for AMS-SoCs blocks is presented with novel Ant
Colony (ACO), Simulated Annealing (SA), Gravitational Search Algorithm (GSA) al-
gorithms.
(4) For illustrative case studies, a 45 nm sense amplifier, a 45 nm thermal sensor and a 180nm
phase locked loop (PLL) are optimized for specific performance objectives.
16
CHAPTER 3
GEOSTASTICAL KRIGING METAMODELING
Kriging prediction techniques are part of the family of geostatistical methods which are
used for surface estimation from limited sample data locations. This form of prediction technique
was formally proposed by Georges Matheron in the early 1950’s and named after Daniel Krige
(hence the term “Kriging”), a pioneer in geostatistical mining. Kriging techniques which were
originally applied for gold mining - predicting possible gold locations based on previously mined
locations - have now been applied to many other fields relevant to spatial data including VLSI
design. Kriging techniques which predict spatial locations based on observed data can be related
to the VLSI design field in predicting the physical characteristics of a layout design. Figure 3.1
shows a geostatistical surface prediction alongside an oxide thickness distribution [3, 2]. The use
of Kriging metamodeling for accurate and efficient representation of nanoelectronic circuits is
motivated by this observation.
(a) Geostatistical Kriging [3]. (b) Oxide thickness distribution [2].
FIGURE 3.1. Geostastical Kriging and oxide thickness comparison.
From Figure 3.1, the oxide thickness distribution can be modeled as a spatial variation
problem and hence Kriging techniques could be used in predicting the oxide thickness at various
17
locations of the layout. Using this technique the different design variables could also be modeled
using Kriging techniques. This feature is explored to generate the Kriging based metamodels which
are used for design exploration. The rest of this chapter discusses the basics and fundamentals
of geostastical Kriging, the different types of Kriging explored, and the metamodel generation
process.
3.1. Fundamentals of Geostastical Kriging Techniques
The fundamental basis of Kriging is that observed data can be modeled as a random process
with spatial autocorrelation. The spatial autocorrelation between the observed points is explicitly
modeled as weighted averages of nearby points using semivariograms (a geostatistics term). The
weights are unique to each predicted point and are a function of the distance between the point
to be predicted and observed points. The weights are chosen so that the prediction variance is
minimized [16, 68]. Hence geostatistical Kriging functions are a set of linear regression routines
which minimize estimation variance from a predefined covariance model. The general expression
of a Kriging model has the following form:
(1) y(x0) =L∑j=1
λjBj(x) + z(x),
where y(x0), is the predicted response at a design point (x0), {Bj(x), j = 1, · · · , L} is a specific
set of basis functions over the domain DN , and λj are fitting coefficients (also known as weights)
to be explicitly determined and z(x) is the random error. The Kriging prediction approach differs
from common least squares based approaches by modeling z(x) to be a random process and not
independent, unique to each weight and not distributed identically. This process has mean µ, vari-
ance σ2, and correlation function r(s, t) = Corr(z(s), z(t)) (called the variogram in geophysics)
which are assumed known.
The variogram is used to derive the Kriging weights, λj . The spatial autocorrelation of
the design points are characterized by the covariance function [9]. Geostatistical (Kriging) models
comprise of several components: examining the data (distribution, trends, directional components,
outliers), calculating the empirical semivariogram or covariance values, fitting a model to the em-
18
pirical values, generating the matrices of Kriging equations, and solving them to obtain a predicted
value and the error (uncertainty) associated with it for each location in the output surface.
Estimation of the correlation between sampled points and a predicted point is done with
the semivariogram model. The semivariogram is calculated using the covariance and the corre-
lation between the different sample variables. The semivariogram is then used with the points to
be predicted. The empirical semivariogram is used to study the spatial trend of the design vari-
ables. However, in the actual point Kriging prediction, lag distances which are not available in
the empirical semivariogram are required; hence the empirical semivariograms are replaced with
semivariogram models. Another reason why the models are used is to ensure that models are non-
negative definite in order for the Kriging equations to be solved. The most common models used
are the following:
• Spherical
• Linear
• Gaussian
• Exponential
• Nugget
The use of one of the above Kriging models can be explored. In this dissertation the spherical
model is used as it is common.
Based on the nature of the observed data points, the empirical model could be fit to either
spherical, linear, Gaussian or exponential theoretical models. The smoothness of the predicted
points is affected by the theoretical model used. A steeper model reduces the smoothness because
it places more weight on closer neighbors. The most common model used is the spherical and is
expressed as follows:
(2) γ(h) = C0 + C(3h
2a− 1
2(h
a)3) for 0 < h ≤ a,
where C0, C and a are shape parameters. The weights are chosen so that the Kriging variance is
minimized for accurate representation.
19
3.2. Types of Kriging
One advantage of Kriging based functions is that the estimated response points are exactly
the same as the observed data. Kriging accounts for the effects of data clustering with the use of
the empirical semivariogram models [9].
There are different variations of the Kriging prediction technique. The estimation of the
weighting system is often the distinguishing factor for implementation. These types of Kriging
implementation include the following:
• Ordinary
• Simple
• Universal
• Indicator
• CoKriging
• Probability
This dissertation explores two forms of Kriging - ordinary and simple - which are briefly discussed
in the rest of this section.
3.2.1. Ordinary Kriging
Ordinary Kriging assumes a mean that is constant in the local domain of a predicted point
whereas simple Kriging assumes a constant and known mean over the global domain. For ordinary
Kriging techniques, the weights are chosen to minimize the Kriging variance under the unbiased-
ness constraint that E(Z(x) − Z(x)) = 0. Hence the weights are chosen so that the following
expression is satisfied:
(3)n∑j=1
λj = 1,
20
whereas this condition is not required for simple Kriging. The weights then for ordinary Kriging
technique are given by the following expression:
(4)
λ1...
λn
µ
= Γ−1
γ(e1, e0)
...
γ(en, e0)
1
,
where µ is a lagrange multiplier used to ensure equation (3) holds. Γ is the covariance matrix of
the observed points and for ordinary Kriging is given as:
(5) Γ =
γ(e1, e1) · · · γ(e1, en) 1
... . . . ... 1
γ(en, e1) · · · γ(en, en) 1
1 1 1 0
,
where
γ(e1, e2) = E(|Z(e1)− Z(e2)|2).
3.2.2. Simple Kriging
The weighting scheme for simple Kriging is given by the following equations: Assuming
we have have n sampled points, of variable x, to predict a new point y(x0) the weights λ are
estimated by the following:
(6)
λ1...
λn
= Γ−1
γ(x1, x0)
...
γ(xn, x0)
,
where Γ is the covariance matrix of the observed points and is given by the following:
(7) Γ =
γ(x1, x1) · · · γ(x1, xn)
... . . . ...
γ(xn, x1) · · · γ(xn, xn)
,
21
where the following expression is used:
(8) γ(x1, x2) = E(|z(x1)− z(x2)|2
).
3.3. Kriging Metamodel Generation Flow
Figure 3.2 outlines the steps entailed in the generation of the geostatistical Kriging meta-
model. The figure shows the interaction between the steps and the tools used. The flow between
the CAD simulator and the sampling procedure for the Kriging model estimator is highlighted.
FIGURE 3.2. Geostatistical Kriging metamodel generation process.
The formal metamodel generation flow is shown in Figure 3.3. The generation flow can be
broken into 3 phases. The first step in the design is to create the circuit schematic of the design to
meet design specifications. In this phase, the physical design is also produced and verified for key
performance metrics. Design Rule Check (DRC) as well as Layout vs Schematic (LVS) verifica-
tion is also performed to ensure that the circuit schematic and physical layout design match. The
last step in this phase involves the parasitic extraction of the netlist. A full blown parasitic (Resis-
tance, Capacitance and self and mutual Inductance i.e., RCLK) is extracted to improve simulation
accuracy to silicon levels.
The extracted parasitic netlist is then prepared for design sampling by parameterizing the
design and process variables used for exploring the design space. Design parameters considered
for this work include transistor gate length L and width W . At the same time the threshold voltage
22
START
Circuit Schematic
Physical Design
DRC/LVS Netlist Extraction
and Parameterization
No
Yes
Parameterized Design
Variables, L, W, Vdd, Tox
Design
SpecificationFunctional
Verification
Yes
No
Specifications
met?
Specifications
met?
Perform LHS
Sampling
Generate Kriging
MetamodelsKriging Generated
Surface
N Sample
Data Points
Test for Accuracy
YesNo Specifications
met?
DONE
DONE
FIGURE 3.3. Proposed geostatistical Kriging metamodel generation flow.
(Vth), oxide thickness (Tox), supply voltage (VDD) and doping concentrations are considered as
process parameters.
The next phase in the Kriging metamodel generation is the design sampling. Latin Hyper-
23
cube Sampling (LHS) is used to generate the sample points to be used for the Kriging metamodel
generation. LHS was proposed to cover all input dimensions simultaneously and thus improving
on the variance of Monte Carlo distributions. The variance of n LHS sample points of a function
f(x) is given by the following:
(9) V ar(yLHS) =1
nV ar(f(x))− k
n+ o
(1
n
),
where k is a positive constant shown to be smaller than the variance of random sampling techniques
[21]. In [24], a comparison of sampling techniques show that the LHS technique generates more
accurate models over random sampling points which supports the proof in [21].
LHS generates n random sample points based on a range of specified inputs. The LHS
technique divides the input range into n intervals of equal length, from which it randomly selects
points in each interval such that the interval appears once in each row and column of a design ma-
trix. Data points may be selected uniformly, randomly, from midpoints or in any distribution form
in each interval. When the distribution used to sample points from each interval is the midpoint,
the technique is called Middle Latin Hypercube Sampling (MLHS). The design variables L and
W are used as the sampling corners while the process parameters are varied to model the effects
of process variation. The generated sample points are fed into the Kriging metamodel generator
along with the design points to be estimated.
The last phase involves the actual generation of the metamodels. The sample design points
generated by LHS are used with the Kriging based algorithm to generate the metamodel surface.
The Kriging function generator used in this work is based on the mGstat MATLAB tool [1]. A
Kriging function is generated for each performance design objective (Figures-of-Merit, FoM).
Each FoM can be expressed based on the general form of the Kriging function. For example,
the predicted precharge time Ypr for the sense amplifier presented later at an unknown design point
W ∗n is expressed as follows:
(10) Ypr (W ∗n) =
N∑i=1
λ (W ∗n)i Ypr (Wni) ,
where Ypr(Wni) are the observed precharge values for the given N Wni (i = 1, 2, . . . , N ) sample
24
points. The weights λ(W ∗n) are unique for each predicted point W ∗
n and are calculated from Eqn.
(4). The accuracy of the Kriging models is tested using the statistical measures of Mean Square
Error (MSE), Root Mean Square Error (RMSE)and the correlation coefficient R2. The MSE and
RMSE are defined by equations 11 and 12:
(11) MSE =1
N
N∑i=1
(Yi − Yi
)2,
(12) RMSE =
√√√√ 1
N
N∑i=1
(Yi − Yi
)2,
where the summation runs over the N points used to generate the metamodels.
A summary of the Kriging metamodel generation is shown in Algorithm 1. This can help
the readers to follow the metamodeling technique and reproduce the results for their use in circuit
and system design.
3.4. Summary and Conclusion
The geostatistical Kriging metamodel discussed greatly improves the accuracy and process
variation awareness for the design process. The generated Kriging functions are used for ultra fast
design space exploration. A concern in Kriging techniques is the time consumed in calculating the
Kriging weights. Since each predicted point is weighted uniquely and calculated by solving matrix
equations, the speed of design exploration will be limited especially in high dimensional designs.
The accuracy of the Kriging estimations still make it a very appealing technique to use especially
as the effects of process variation become more pronounced.
25
Algorithm 1 Kriging Metamodel Generation1: Obtain the parasitic-aware parameterized netlist of the circuit design after performing the base-
line physical design, design rule check (DRC), layout-vs-schematic (LVS) verification, and
parasitic (RLCK) extraction.
2: Obtain the target specifications of the circuit design and select the performance objectives or
figure-of-merits (FoMs).
3: Parameterize the parasitic-aware netlist for the design parameters.
4: Initialize the number of sample set points (n).
5: Generate n sample set points using Latin Hypercube Sampling (LHS).
6: Sample the design space using n sample points P = [P1, . . . , Pn] for M design variables using
LHS.
7: Derive variogram model for each FoM based on the observed sample points.
8: for Each design points to be predicted. do
9: Generate the variograms for Kriging model .
10: Generate prediction weights for the Kriging model (simple or ordinary).
11: Generate Kriging models for design points.
12: end for
13: Perform accuracy analysis of the Kriging metamodels using the Root Mean Square Error
(RMSE) and the correlation coefficient R2.
26
CHAPTER 4
CASE STUDY CIRCUITS
In implementing the proposed design flows, the design of three analog circuits is used as
case study. A sense amplifier, a thermal sensor and a phase locked loop (PLL) are used to illustrate
the effectiveness of the design flows. In this chapter, the description of each circuit and the design
goals are discussed.
4.1. Sense Amplifier
The sense amplifier is used in conventional DRAMs and is crucial to the correct operation
of the DRAM system. The sense amplifier amplifies the minimal voltage difference appearing on
bitlines into a full swing of VDD for a high or low reading.
Sense Amplifiers
Voltage Based Current Based
Cross Coupled Full Latch Current Mirror Clamped
Bitline
FIGURE 4.1. A taxonomy of sense amplifier designs.
Sense amplifier designs can be classified under voltage and current mode topologies [13,
56]. Voltage mode sense amplifiers amplify a voltage differential while current mode amplify cur-
rent differential. In larger memory circuits where there is a lower input capacitance, current mode
sense amplifiers are more appealing because they can operate faster with lower voltage swings.
Figure 4.1 shows some examples of sense amplifiers and their classification. The sense amplifier is
crucial to the correct operation of the DRAM system. Its performance is significantly affected by
27
effects of process variation which has to be taken into account during the design process, making
it an ideal example circuit for this study.
The circuit schematic of the sense amplifier is shown in Figure 4.2. Figure 2(a) is a full
latch voltage based sense amplifier and Figure 2(b) is a clamped bitline sense amplifier. The full
latch sense amplifier consists of cross coupled inverters and 3 NMOS transistors used to precharge
the bitlines. The clamped bitline is a variation of the full latch amplifier, but uses transistors
MN3 and MN4 to provide a low impedance between the bitlines through VCL. The corresponding
physical layout design is also shown in Figure 3(a) and 3(b) for the full latch and clamped bitline
respectively. Both designs have been implemented using 45nm technology with baseline transistor
widths of NMOS and PMOS transistors at 120nm and 240nm respectively.
The circuit is characterized for FoMs which include the precharge and equalization time
(TPC) — the time used to equally precharge the bitlines for sense operations, sense delay (TSD) —
the time it takes for a sufficient voltage sharing to appear on the bitlines, power consumption(PSA)
— average power consumed including static and dynamic power and sense margin (VSM ) — the
minimum amount of voltage that must appear on the bitlines for correct amplification [56, 61].
TABLE 4.1. Characterization of sense amplifier FoM.
Design Precharge time Sense delay Power Sense Margin Area
TPC (ns) TSD(ns) PSA (µW) VSM (mV) µm2
SchematicFull Latch 18.02 7.46 1.16 29.33 -
Clamped Bitline 10.31 1.79 1.84 26.91 -
LayoutFull Latch 18.20 7.45 1.17 29.25 4.294
Clamped Bitline 18.40 1.91 1.88 28.03 6.045
The functional simulation of the full latch sense amplifier is shown in Fig. 4.4. It shows
the various operating states of the sense amplifier, namely the write, hold and read stages. Ln and
Wn are used as design parameters (the parametric analysis shows the nMOS transistors dominate
the FoM). The design objective could be single or multi-objective; in this case a single objective
with design constraint is presented. For this design, the optimization objective is the precharge
28
MP2MP1
MN1 MN2
SE MP3
SE
PRE
VDD/2
VDD
BLBL
Vbl Vbl
MN4 MN5
Cbl Cbl
MN3
(a) Conventional (full latch) sense amplifier.
Pre2Pre1
BLBL
VoVo
SESE
SAP
VCL
MN6
MN7 MN8
MP2MP1
MN1MN9 MN2 MN10
MN4MN3
MN5
RefRef
eqVDD
(b) Clamped bitline sense amplifier.
FIGURE 4.2. Sense amplifier circuit with sizes for 45nm CMOS technology.
29
(a) Conventional sense amplifier.
(b) Clamped bitline sense amplifier.
FIGURE 4.3. Physical design of the sense amplifier circuit with 45nm technology.
30
time TPC , while power consumption is used as a design constraint.
0 50 100 150 200 2500
0.2
0.4
0.6
0.8
1
time(ns)
Vol
t(V
)
Sensing Waveform
BLBLBAR
0 50 100 150 200 2500
0.5
1
1.5
time(ns)
Vol
t(V
)
Signal Control
WLPRESE
Sense "0"
VDD/2Sense "1"
FIGURE 4.4. Waveform of sense amplifier functional simulation.
4.2. Thermal Sensor
Thermal sensors are commonly used as stand-alone sensors as well as integrated into big-
ger chips for power consumption management and over-heating prevention. The design of thermal
sensors has increasingly become crucial due to the critical need of efficient thermal management
methods [17]. Most thermal sensor designs are oscillator based, with the ring oscillator as a signif-
icant component. The system level diagram of the thermal sensor is shown in 4.5 and is made up
of three 3 major components: The ring oscillator (RO), the 10-bit counter and the 10-bit register.
The RO, shown in 4.6, consists of a cascade of an odd number inverters connected in a loop. The
RO used here has 15 stages.
The oscillation frequency of a ring oscillator is calculated using the following expression:
(13) fosc =1
n(tpLH + tpHL),
where n is the number of stages used in the oscillator and tpLH and tpHL are the low-to-high and
high-to-low propagation delays, respectively. In an ideal condition, the propagation delays can be
expressed as follows [45]:
31
Out
Ring
OscillatorBinary Counter
Register
Inputctrl fout clk
reset cout
inclkSys_clk
FIGURE 4.5. Thermal sensor system configuration.
NAND Inv1 Inv2 Inv14. . .
ctrlFout
FIGURE 4.6. Ring oscillator schematic.
(14) tpLH =−2CLVtp
κp(Vdd + Vtp)2+
CLκp(Vdd + Vtp)
ln1.5Vdd + 2Vtp
0.5Vdd
(15) tpHL =2CLVtn
κn(Vdd − Vtn)2+
CLκn(Vdd − Vtn)
ln1.5Vdd − 2Vtn
0.5Vdd
(16) tpLH =2C
κn(WL
)n
(Vdd − V t)
[Vt
Vdd − V t+
1
2ln
(3Vdd − 4Vt
Vdd
)],
where CL is the capacitive load. κn and κp are the transconductance values which are calculated
from the following expression: κn/p = µnCox(WL
)n/p.
From equations 13 - 15, the threshold voltage Vt and mobility are the factors most sensitive
to temperature fluctuations. The threshold voltage Vt and mobility are expressed in equations 17
and 18 respectively [12] in the following manner:
(17) Vt(T ) = Vt(T0) + αVt(T − T0), αVt = −0.5− 3.0mV/◦K
32
(18) µ(T ) = µ0
(T
T0
)αµ, αµ = −1.2− 2.0
An increase in temperature leads to an increase in the propagation delay which results in a decrease
of the oscillating frequency.
The 10-bit binary counter is shown in Fig. 4.7 which consists of JK flip-flops while the 10-
bit register shown in Fig. 4.8 is used to store the value from the counter and is also implemented
with JK flip-flops.
The technology library used for the implementation of this thermal sensor design was a
45nm technology library provided by Cadence Design Systems, Inc., with nominal parameter di-
mensions on the Cadence Virtuoso Platform. The thermal sensor design is characterized to sense
temperatures between 0°C and 100°C. The Sys clk signal is used to enable the thermal sensor.
When the Sys clk turns to logic zero, the ring oscillator is disabled, the counter is also reset and the
register also stops saving the count, storing the last count value it had before the Sys clk was set to
logic “0”. The binary counter is used to count the frequency difference between the ring oscillator
output and the system clock. The count is stored in the 10-bit register and calibrated to measure
the temperature change. The physical design of the thermal sensor is shown in Figure 4.9.
The performance and accuracy of the physical design of the thermal sensor are degraded
when compared to the schematic design. This is expected due to parasitic effects from the layout.
Table 4.2 shows a comparison between the schematic and physical design. The power consumption
is increased by 29 % from 293 µW to 379.4 µW. This circuit exhibits a linear dependence of
oscillating frequency on junction temperature, as shown in Fig. 4.10.
TABLE 4.2. Thermal sensor output comparison.
Design Average Power, (PTS) Sensitivity, (TTS) Area (µm2)
Schematic 293.1 µW 16.88 MHz/°C -
Layout 379.4 µW 9.42 MHz/°C 1221.37
% Change 29.44% 44.2%
33
As frequency decreases, the temperature increases. The frequency range of the schematic
design is from 0°C= 5.924 GHz to 100°C= 4.236 GHz. Assuming a 6 GHz max clock rate for
the ring oscillator, and a 10 bit counter (1024 max count) the effective resolution is calculated by
dividing the temperature range by the number count 100°C/1024 bit which gives a 0.097°C/bit
resolution. The range of frequency output is also severely degraded as also seen in Fig. 4.10.
The range drops to 3.867 GHz to 2.986 GHz. The resolution can also be specified in terms of
GHz/°Cto reflect the degrading effect of parasitics from the physical design. There is a 47.8%
change in frequency/temperature resolution between the schematic design and the physical design.
The area of the physical design is 1221.37 µm2.
4.3. Phase Locked Loop - PLL
The phase locked loop (PLL), which is a closed feedback loop circuit system, is an ideal
circuit for this study. It is widely used in many analog mixed signal systems including processors,
Field-Programmable Gate Arrays (FPGAs) and in telecommunication applications. The major
components of the PLL are the phase detector, charge pump, voltage controlled oscillator (VCO)
and frequency divider. A system diagram is shown in Figure. 4.11.
The phase detector is the most critical element as it detects the phase difference of the
signals from the reference clock and closed loop. A difference in phase causes the charge pump to
supply charge proportional to the error detected. The charge pump controls the amount of charge
on the filters of the capacitors based on the signals from the phase detector. The signal is filtered
and used to control the VCO which produces the output phase to lock in with the reference clock.
The divider is used to make the output signal a multiple of the reference clock if desired. The
PLL used here is based on the design presented in [26]. The physical layout design of the baseline
180nm design is shown in Fig. 4.12.
The PLL was characterized for power consumption, frequency output and locking time.
The design objective was the minimization of power consumption using the locking time as opti-
mization cost and 21 design parameters as variables.
34
4.4. Summary and Conclusion
The circuits presented here represent a cross section of different applications and different
design sizes of mixed-signal designs. The sense amplifier is the smallest circuit with 6-9 transistors,
while the thermal sensor and PLL circuit designs have hundreds of transistors. This selection of
circuits illustrate the robustness of the proposed methodologies to be applied to different types of
mixed signal designs.
35
JKFl
ipFl
op0
J Kclk
QJK
Flip
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1J Kclk
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k
Q
b0b1
b2
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n
clk
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op2
Buffe
rBu
ffer
AN
D
Buffe
r
AN
D. .
. . . .
J Kclk
Qb9
JKFl
ipFl
op9
FIGURE 4.7. 10 bit binary counter.
36
JKFlipFlop0J
Kclk
QQ0
Q0
JKFlipFlop1J
Kclk
QQ1
Q1
JKFlipFlop9J
Kclk
QQ9
Q9
clk
. . .. . .
FIGURE 4.8. 10-bit register.
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FIGURE 4.9. Physical design of 45nm thermal sensor.
37
0 20 40 60 80 1002.5
3
3.5
4
4.5
5
5.5
6x10
9
Temperature (°C)
SchematicLayout
Fre
quen
cy (
Hz)
FIGURE 4.10. Ring oscillator frequency response versus temperature for both
schematic and physical designs.
Output
Phase
Detector
Charge Pump/
Loop Filter
LC-
VCO
Divider
Input
Signal
FIGURE 4.11. High level system diagram for the PLL.
38
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1
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FIGURE 4.12. Physical layout design for the 180nm PLL.
39
CHAPTER 5
KRIGING METAMODEL ASSISTED NANOELECTRONIC DESIGN FLOWS
This chapter presents the novel metamodel design and optimization flows proposed. The
metamodeling design technique is based on the geostatistical Kriging prediction technique. The
generated Kriging based metamodel function has already been discussed in Chapter 3.3. In this
chapter, the overall design flow methodology with performance optimization components is pro-
posed. The novel design flow is a modification and improvement of the actual netlist optimization
discussed in Chapter 2.2. A Kriging bootstrapped artificial neural network flow is also proposed to
introduce a process variation awareness at different levels of the design process.
The overall design flow methodologies include optimization algorithms for the fast opti-
mization of the metamodel based designs. The first section of this chapter discusses the optimiza-
tion algorithms used and then the different design flow methodogies are presented.
5.1. Optimization Algorithms
In this work, we explore intelligent population based algorithms which are heuristic in
nature and are particularly well suited for optimization problems of this context. We explore simu-
lated annealing, ant colony optimization, and gravitational search algorithm (GSA). The following
subsections summarizes the details of each of the algorithms used in the design flow methodolo-
gies.
5.1.1. Simulated Annealing Based Optimization (SAO)
Simulated annealing optimization is based on the Monte Carlo algorithm and was originally
used to simulate the annealing process used in metallurgy. This gives the simulated annealing
algorithm random characteristics. Successive runs of the algorithm will produce different results.
The optimization steps are presented in Algorithm 2.
The algorithm takes random walks through the design space starting from the middle point
of each design parameter, looking for points with low energies. In each step, the probability of
taking a step is determined by the Boltzmann distribution, p =
(e
∆TPCT
)when ∆TPC is high, and
40
Algorithm 2 Simulated-Annealing Based Optimization for Analog Circuits1: Initialize iteration counter: counter ← 0.
2: Initialize temperature Θ.
3: Initialize Cooling Rate.
4: Start with an initial solution. eg CBSAi.
5: Calculate the FoMs for CBSAi using the Kriging metamodels.
6: Consider the objective of interest TPCi .
7: result← ∆TPC ← TPCi .
8: while (∆TPC ! = 0 ) do
9: counter ← max Iteration.
10: while (counter > 0) do
11: Generate random transition from solution CBSAi to CBSAj .
12: Calculate the FoMs e.g. CBSAj using the Kriging models.
13: if (TPCj < result) then
14: result← TPCj .
15: CBSAi ← CBSAj .
16: else
17: ∆TPC ← TPCi − TPCj .
18: if ( ∆TPC < 0, random(0,1) < e∆TPCT ) then
19: TPCi ← TPCj .
20: CBSAi ← CBSAj .
21: end if
22: end if
23: counter ← counter − 1.
24: end while
25: Θ← Θ× Cooling Rate.
26: end while
27: return result and CBSAi.
41
p = 1 when ∆TPC is low. Therefore a step will occur if a new value is better than the previous
one. If the new value is worse, the transition can still occur, and its likelihood is proportional to
the temperature T and inversely proportional to ∆TPCi.
The temperature T is initially set to a high value, and a random walk is carried out at
that temperature. Then the temperature is lowered according to a cooling schedule, for example:
T = T ∗ Cooling Rate where Cooling rate is slightly lower than 1. The slight probability of
taking a step even if the new solution is worse is what allows simulated annealing to frequently
get out of local minima. The algorithm stops when it reaches an acceptable solution or reaches the
maximum number of iterations. The objective chosen for optimization is the precharge time TPC .
From the metamodel plot shown in Fig. 6.2, the average power PSA is already at its minimum,
while the precharge time shows greater potential for optimization compared to the sense delay.
5.1.2. Ant Colony Optimization (ACO)
Ant Colony Optimization (ACO) algorithms inspired by the foraging behavior of ant species
are metaheuristic random searching algorithms. The majority of ACO algorithms have been ap-
plied to discrete combinatorial optimization problems such as routing, scheduling, and timetabling
[20, 19]. A classic example in demonstrating the ACO algorithm is the Traveling Salesman Prob-
lem (TSP), where a shortest route that allows the salesman to visit each city only once is required.
The basic stages of ACO based algorithms are metaheuristic which means they can be easily modi-
fied for applications on a wide range of optimization problems [19]. Recently, there has been more
research to investigate and extend the application of the ACO algorithms to continuous function
problems [66, 33, 11, 75]. The pheromones are updated using equation (19):
(19) τi = (1− ρ) . τi + ρ . ∆τi,
where ρ is the rate of evaporation. m is the number of ants used in the algorithm. The pheromone
is updated only for the best solutions. The criteria and number for best solutions can be decided
for each optimization problem.
The basic characteristics of ACO algorithms include the incremental construction of solu-
tions and the use of pheromone updates to guide point explorations. The basic stages for the ACO
42
metaheuristic are the following:
(1) Initialize variables and set conditions
(2) Construct ant nodes
(3) Perform local search (optional)
(4) Update pheromones
After the initialization step, the algorithm iterates between steps 2-4 until the condition for
termination is met.
There are several variations of the ant colony optimization, which include the Ant System
(AS), Max-Min Ant System (MMAS), the Ant Colony System (ACS). The three stages are com-
mon to all three. The MMAS and the ACS provide an improvement over the AS by having only
the best solutions update pheromones.
ACO algorithms for continuous problems differ from discrete optimization in the selection
of ant nodes. In [66, 19, 33, 11, 32, 70] several modifications to ACO for continuous function
optimization have been presented. One major way of adapting the ACO for continuous functions
is by dividing the solution space into different intervals and having each ant or node search an
interval for an optimal solution. The nodes can also directly search the continuous function. The
proposed algorithm in this paper is most closely related to the approach proposed in [33], where
the design space is sampled for search nodes. Where the proposed algorithm in this paper differs
from [33] is that each decision variable is a given node and not a set of nodes. In this case a
solution by a node is also assumed a “path” traversed by an ant, keeping in line with the original
ACO framework. With the discretization of the continuous problem space, the ACO algorithm can
be easily used to generate optimal solutions.
The distinct steps which are used for the setup of the ant colony heuristic are presented in
an algorithm fashion in Algorithm 3.
5.1.3. Gravitational Search Algorithm (GSA)
Although many optimization algorithms exist and are being actively applied in design tech-
niques, research to improve performance or deduce new algorithms continues. The gravitational
43
Algorithm 3 Ant Colony Optimization (ACO) Based Heuristic Algorithm Setup1: Initialize parameters
2: Set termination conditions
3: Generate random node ants
4: Perform pheromone update
5: while (Termination condition not met ) do
6: Generate node ants with pheromone probability
7: Update pheromone
8: end while
9: return result
search algorithm (GSA) was recently introduced in 2009 by [63], as a new heuristic optimization
algorithm based on the Newtonian laws of gravity. The proposed GSA algorithms model the search
agents as mass objects varying in design points by the location of the masses and the performance
object is modeled as the mass of the object. Heavier masses correspond to better performing agents
(i.e design points with superior performance objectives.) As agent masses become heavier, they at-
tract other agents towards them by gravity force, hence pulling search agents towards an area with
a likely optimal solution. Agents which attract other masses become heavier and move slower,
concentrating in a search area with a likely optimal solution while lighter masses are able to move
faster exploring other search locations. The movement and attraction of agents are developed using
Newtonian laws of gravity and motion. The selection of the rate of attraction is an important step
in order to fully utilize the exploration and exploitation features of this algorithm. The exploration
feature is the capability of actively stratifying the design space while exploitation is the efficiency
of locating optimal solution in a likely optimal area. If the masses attract each other too quickly,
the agents will not fully explore the search space.
A high-level overview of the GSA algorithm is shown in Fig. 5.1. The search agents, for
example a set of design parameters, are denoted by their locations and masses asMw, Mx, My, and
Mz in the design space. The location of each agent at any particular time is shown and the quality
of solution is denoted by the mass size of the agent. Mz, currently has the best quality while Mw
44
has the worst. The underlying principle of the algorithm is shown using the forces acting on search
agent My as an example.
My
Mx
Mw
Mz
Fwy
Fxy
Fyz
Fxz
ay
My
Best solution
so far
New My
Design Space
FIGURE 5.1. GSA: Search agents are attracted towards locations with possible
quality solutions.
Assuming a system where N denotes the number of masses (search agents/nodes), the
location (design point) of the ith mass can be expressed as follows:
(20) Xi = (x1i , x2i , . . . , x
di , . . . , x
ni ) for i = 1, 2, . . . , N,
where xdi , presents the position of the ith agent in the dth dimension, and n is the number of
dimensions.
The major premise of the algorithm is the extension of the Newtonian laws of gravitation
and motion. The GSA system which is based on system of masses interacting with each other relies
on the idea that better solutions accorded with heavier mass will eventually attract search agents
with worse solutions which have smaller masses, increasing the search agents in an area with a
likely optimal solution. The movement of the search agents is also based on the laws of motion,
which directs the velocity of an object based on the acceleration due to the force of attraction from
surround objects. In calculating the force of attraction in GSA, a random value has been added to
provide a stochastic feel to the algorithm and to reduce the likelihood of optimization being stuck
45
in local minima. The attractive force on a mass object ‘i’ from a mass object ‘j’ is given by the
following expression:
(21) F dij(t) = G(t)
Mpi(t)×Maj(t)
Rij(t) + ε(xdj (t)− xdi (t)),
whereMaj andMpi are the active and passive gravitational mass of objects ‘j’ and ‘i’, respectively,
G(t) is a gravitational constant at time t, and Rij is the Euclidean distance between both objects.
The mass of each agent is updated with the following equation:
(22) mi(t) =fiti(t)− worst(t)best(t)− worst(t)
,
(23) Mi(t) =mi(t)∑Nj=1mj(t)
.
In the above expressions, fiti(t) represents the best solution found in each iteration. Thus,
the total force acting on an object is given by the following expression:
(24) F di (t) =
N∑j=1.j 6=i
randjFdij(t),
where randj is a random number between 0 and 1. The use of the random number adds a stochastic
feel to the algorithm.
The velocity and the new agent location update are given by equations (25) and (26).
(25) vdi (t+ 1) = randi × vdi (t) + adi (t),
where randi again is a random number between 0 and 1 and adi (t) is the total force given in
equation (21) divided by the mass of the object given in equation (23).
(26) xdi (t+ 1) = xdi (t) + vdi (t+ 1),
Hence, mass locations which find optimal solutions gradually attract masses with poor
performance effectively increasing the chances of exploitation but also ensuring exploration of the
design space. A convergence of the masses by the heaviest mass presents an optimal solution of
the search space. One appealing feature of the GSA is that it is memoryless, it does not need
46
to remember previous best solutions but still guarantees near-optimal solution by virtue of mass
acquisition.
A summary of the GSA algorithm is shown in the pseudocode displayed in Algorithm 4.
This algorithm can be programmed using any language and platform of the designer’s choice.
Algorithm 4 Gravitational Search Algorithm1: Initialize iteration counter: counter ← 0.
2: Initialize max iteration Maxiter.
3: Initialize number of search agents η gravity constant G, and velocity ν.
4: Generate η random search nodes (design parameter sets).
5: Consider the objective of interest PTSi .
6: counter ← max Iteration.
7: while (counter < Maxiter) do
8: Evaluate objective of interest for each search node.
9: Update best and worst solution per function objective.
10: Update G.
11: Calculate M and a for each search node.
12: Update ν for each search node.
13: Update search nodes by applying velocity on M.
14: counter ← counter + 1.
15: end while
16: return bestsolution
In the pseudocode shown in 4, steps 1 - 3 set up the optimization flow, by setting up the
maximum number of iterations and the number of mass agents to use for optimization. Step 4 sets
up the location of each of the search nodes with generic masses. Steps 7-14 consist of the main
section which analyses each search node per iteration and update the mass, velocity and location,
reiteratively until an optimal solution is found or the termination criteria are met.
47
5.2. Metamodel Assisted Design Optimization
Computationally intensive simulations are very expensive. To reduce this cost, metamodels
are generated to aid the design process and its optimization. A new methodology, geostatistical
Kriging Assisted Ultra-Fast Optimization design flow is proposed. The proposed Kriging based
methodology uses the Kriging generated metamodeling function combined with an optimization
algorithm. The methodology is incorporated in the design flow shown in Fig. 5.2. The design
flow is a combination of the Kriging metamodel generation flow and can be broken into 4 steps as
described in the rest of this Section.
5.2.1. Design and Netlist Optimization
The first step in the design flow is to create a model of the circuit design that meets the
design specifications. The circuit schematic is drawn and simulated using a CAD tool. After
the design is verified for key performance characteristics, the physical layout is created using
Design Rule Checks (DRC) as a guide. Once the DRC is completed, a layout vs. schematic (LVS)
verification is also oerformed to ensure that the physical design matches the circuit schematic.
A parasitic netlist, including resistance, capacitance and self and mutual inductance (RCLK) is
then extracted from the physical design and used for further simulations to give a more accurate
description of the design. The design and process parameters are identified in the netlist which
is then parameterized and used for sample point generations in the next step. In this flow, the
design parameters chosen are the transistor gate length L and width W . For process parameters,
threshold voltage (Vth), oxide thickness (Tox), supply voltage (VDD), and doping concentration are
considered.
5.2.2. Latin HyperCube Sampling (LHS)
Latin Hypercube Sampling (LHS) techniques are one of the commonly used methods for
generating sample data points for Kriging based metamodels. LHS generates n random sample
points based on a range of specified inputs. The LHS technique divides the input range into n
intervals of equal length, from which it randomly selects points from each interval such that the
interval appears once in each row and column of a design matrix. Data points may be selected
48
START
Circuit Schematic
Physical Design
DRC/LVS Netlist Extraction
No
Yes
Netlist with Parasitics
Design
SpecificationFunctional
Verification
Yes
No
Specifications
met?
Specifications
met?
Perform LHS
Sampling
Kriging Metamodel
GenerationKriging Metamodel
Function
Sample
Data Points
ANN Training
Yes
No Specifications
met?
DONE
Optimized design
ParametersPerform Optimization of Kriging
Function using Optimization Algorithm
STOPRobust Final
Design
Identify Design and Process
parameters (Design -L, W)
(Process Vth, Tox, Vdd, doping conc)
Parameterized Design
Variables, L, W, Vdd, Tox
A
B
C
D
FIGURE 5.2. The proposed Kriging assisted ultra-fast design optimization flow.
49
uniformly, randomly, from midpoints or in any distribution form in each interval. When the dis-
tribution used to sample points from each interval is the midpoint, the technique is called Middle
Latin HyperCube Sampling (MLHS). The design points L and W are used as the sampling corners
while the process parameters are varied to model the effects of process variation.
5.2.3. Kriging Based MetaModel Generation
The sample design points generated by LHS are used with the Kriging based algorithm to
generate the metamodel surface. The Kriging technique generates predicted output response points
of design inputs based on observations from the sampled data. The generated metamodel is a func-
tion of the design parameters L and W , and process parameters. Two Kriging methods, ordinary
Kriging and simple Kriging, are used to generate metamodels for each of the FoMs (precharge
time TPC , sense delay TSD, and sense margin VSM ), of the clamped bitline sense amplifier. A total
of 8 metamodels are generated and are compared to an accurate model generated by exhaustive
simulation. The empirical variogram is estimated from the created variogram. It is then fitted with
the theoretical spherical model, which was the best fit for the sampled data points. Each FoM
can be expressed based on the general form of the Kriging function. For example, the predicted
precharge time Ypr at an unknown design point W ∗n is expressed as:
(27) Ypr (W ∗n) =
N∑i=1
λ (W ∗n)i Ypr (Wni) ,
where Ypr(Wni) are the observed precharge values for the given N Wni (i = 1, 2, . . . , N ) sample
points. The weights λ(W ∗n) are unique for each predicted pointW ∗
n and are calculated from Kriging
weight equations. Using similar equations, the values for the other FoMs of the sense amplifier are
predicted.
5.2.4. Design Optimization
The generated Kriging metamodel is subject to an optimization algorithm, which could be
any of the algorithms discussed in section 5.1. The design flow can be summarized by using the
ACO example as show in Algorithm 5.
50
Algorithm 5 Ant Colony Based Algorithm1: Start
2: Create baseline design.
3: Identify FoMs (verify functionality).
4: Create physical layout.
5: Perform DRC/LVS/RLCK.
6: Identify design parameters and parameterize netlist
7: Metamodel Generation
8: Perform LHS to generate design points for metamodel.
9: Generate Kriging metamodels using mGStat tool
10: Optimization
11: while (Optimization objective not met ) do
12: Perform ACO based algorithm.
13: end while
14: return Optimized Design
The detail of implementation is in steps 6 and 7. For each iteration, new sets of ant solutions
(feasible design points) are generated. The solutions are updated with an evaporating pheromone.
The best solution is however updated with more pheromone increasing the probability of the path
(node) being traversed by more search ants. The iterations are continued until the termination
condition is met, in this case, a maximum number of iterations. The speed of convergence of ACO
algorithms is controlled by the rate of pheromone update. A series of runs show that for this circuit,
an average of 100 iterations converge the algorithm to an optimal solution.
5.3. Metamodel Assisted Process Variation Analysis
In this section, another novel design flow methodology is presented. The previous Kriging
based design flow methodology presents a limitation in the speed of the design space exploration.
The disadvantage lies in the unique weighting system of Kriging techniques, which require each
weight to be calculated using matrix equations. Hence for high dimensional designs, the speed
with which the design space can be explored may be limited. To mitigate this, we propose a
51
novel Kriging Bootstrapped Neural Network Metamodeling design technique. This methodology
introduces a process variation awareness at different levels of the design process.
5.3.1. Proposed Kriging Bootstrapped Neural Network Metamodel
The metamodel assisted process variation analysis flow is discussed in this section.
Our proposed Kriging bootstrapped Artificial Neural Network metamodeling technique is
shown in Fig. 5.3. Metamodeling techniques based on Kriging prediction have been explored in
[60, 7]. In estimating performance points, Kriging prediction techniques take into account the cor-
relation effects between design parameters. This characteristic is very appealing and can be used
to model the correlation effects between design parameters due to process variation for design pro-
cesses deep in the nanometer range. The drawback to Kriging based techniques is that the weights
used for each point prediction are unique and have to be calculated for each performance point
to be estimated using linear algebra calculations (mostly matrix inversion). This can lead to po-
tential time consuming metamodel generation for high dimensional designs and very large design
spaces. Artificial Neural Network (ANN) training, which has also been presented for NanoCMOS
metamodeling in [27], has been shown to be robust and accurate for high dimensional models [69].
While ANNs also produce highly accurate models, they do not effectively model process variation
effects with correlations present.
Hence, the proposed metamodeling technique aims to combine Kriging and ANN to gen-
erate accurate models which account for the effects of correlated process variation in a fast and
efficient manner. Figure. 5.3 highlights the already presented methods for ANN and Kriging meta-
model generation. For each method sample data points are generated using a Latin Hypercube
Sampling (LHS) design and then are either fed into an ANN trainer or a Kriging function genera-
tor. In the proposed metamodel generation method, the sample data points are fed into a Kriging
generator that produces an intermediate set of sample data points (bootstrapped) which are then
fed into the ANN trainer. This method feeds the ANN trainer Kriging generated sample data points
which are process and correlation aware. We demonstrate that using the Kriging generated sample
data points will result in a more robust metamodel which is process variation aware and also less
time intensive.
52
Sam
ple
NS
amp
le 3
Sam
ple
2D
ata
1
f f
Kri
gin
g F
un
ctio
n
Gen
erat
or
AN
N
Met
amo
del
Kri
gin
g
Met
amo
del
f fK
rig
ing
/AN
N
Met
amo
del
AN
N T
rain
ing
Kri
gin
g t
rain
ed A
NN
Sam
ple
NS
amp
le 3
Sam
ple
2S
amp
le 1
Dat
a n
-1D
ata
3D
ata
2D
ata
1D
ata
n-1
Dat
a 3
Dat
a 2
Dat
a 1
...
Bo
ots
trap
ped
Kri
gin
g
Gen
erat
ed D
ata
FIGURE 5.3. Proposed Kriging based ANN metamodel generation flow.
53
START
Circuit Schematic
Physical Design
DRC/LVS Netlist Extraction
and Parameterization
No
Yes
Parameterized Design
Variables, L, W, Vdd, Tox
Design
SpecificationFunctional
Verification
Yes
No
Specifications
met?
Specifications
met?
Perform LHS
Sampling
N Kriging point estimationN Kriging bootstrapped
Data Points
N Sample
Data Points
ANN Training
Test for Accuracy
YesNo Specifications
met?DONE
DONE
Kriging Trained
ANN Metamodel
To Statistical
Variation Analysis
FIGURE 5.4. Proposed metamodel design flow.
The methodology for the generation of the proposed metamodel-based design flow is shown
in Fig. 5.4. The first step involves creating a SPICE netlist of the design. The functional simula-
tion of the circuit schematic is performed to ensure the SPICE model meets design specifications.
The physical layout design is also constructed using Design Rule Check (DRC) and Layout vs.
Schematic (LVS) verification to ensure a match to the circuit schematic. The physical layout de-
54
sign is used to generate a silicon-aware accurate model (netlist). The performance of the physical
design is often degraded due to the parasitic effects. A fully extracted parasitic netlist, including re-
sistance (R), capacitance (C) and self (L) and mutual inductance (K) is used to ensure silicon-level
accuracy.
The generation of the metamodel is based on the extracted parasitic RCLK netlist. In
order to generate data sample points, the extracted parasitic netlist is parameterized for the design
and process variables and then simulated to eliminate the strenuous task of physically varying the
design parameters on the physical layout design. The Latin Hypercube Sampling technique is used
in the proposed method to vary the design and process parameters. LHS methods generate N
random sample points from a given design space. They divide the design space into equal intervals
and then randomly select design points from an interval in such a way that each interval appears
once in a row-column matrix of the design space. Several techniques may be used to select the
data points including uniformly, midpoints or randomly. We use Random LHS which has been
reported to generate more accurate models [23]. The LHS parameter points are used as inputs
to the parameterized netlist to generate corresponding performance outputs (data point) for each
sample point.
The next step in the metamodeling process is the Kriging bootstrapping of the data points.
The generated sample points are fed into a Kriging metamodel generator. We generate N Kriging
bootstrapped data points by using N − 1 points and the Kriging method to estimate the Nth point.
N iterations of this process will generate N Kriging bootstrapped data points which are then used
for the ANN training.
The ANN training process is used to create metamodels for each performance objective
(Figure-of-Merit or FoM) characterized for the design. In this work, 4 metamodels were created
for the Phase Locked Loop circuit described in section 4.3.
The final step of the metamodel design flow is the verification and test of accuracy of the
generated metamodel. The statistical metric used to verify the accuracy is the Root of Mean Square
55
Error (RMSE). The expression of the RMSE is the following:
(28) RMSE =
√√√√ 1
N
N∑i=1
(Yi − Yi
)2,
where N is the number of sampled points, Yi is the “true” circuit response (SPICE simulation
results) and Yi is the metamodel predicted response. The RMSE measures the difference between
the metamodel and the SPICE model where a smaller value indicates a more accurate model.
In this section we perform a process variation aware statistical analysis of the generated
Kriging trained Neural Network metamodel. Monte Carlo simulation experiments are a common
method for the analysis of process variation on analog circuits in order to estimate the yield and
efficiency of the design. Monte Carlo analysis enables an efficient investigation of the design space
by randomly generating a distribution test case of design variables. The set of test cases form a
given probability distribution with a mean of the nominal value of the variable. This is particularly
efficient in high dimensional designs where a test case simulation time increases exponentially.
For example, in our PLL case study circuit which has 21 design and process parameters, even a
high and low test case will require 221 simulations.
The selection of design and process parameters significantly affects the accuracy of the
analysis. A sensitivity test is usually performed to select parameters which are most sensitive to
performance measure. Reported research [39, 35, 55] shows that the length (Ln, Lp), width (Wn,
Wp) and oxide thickness (Tox) have a significant effect on the performance shift. Ln, Lp, Wn,
Wp for the various sub-circuit components of the PLL have been used as design parameters. The
nominal values are selected from the baseline design in Chapter 4.3 and a Gaussian distribution
with 10 % standard deviation is used to generate the sample set for the metamodel simulation.
Figure. 5.5 summarizes the statistical analysis process. N = 1000 Monte Carlo simulations are
performed for each FoM.
The performance results of the Monte Carlo analysis are compared with an analysis from
the spice simulation of the PLL design in the next section.
56
Gaussian Data Point
Distribution
L,W, Vdd, tox
freq
uen
cy
Peformance Shift
Distribution
freq
uen
cy
From Metamodel
Design Flow
jitter
Kriging Trained ANN frequency
Kriging Trained ANN Lock_time
Kriging Trained ANN
Metamodel Power
jitterfrequencyLock_time
Powerfreq
uen
cy
FIGURE 5.5. Statistical variation analysis.
5.4. Metamodel Assisted Process Variation Aware Optimization
We propose a novel design flow that integrates a Kriging bootstrapped metamodeling pro-
cess with the differential search algorithm for the design optimization of nanoCMOS circuits. The
overall flow of the design process shown in Fig. 5.6 highlights the major phases of the design flow.
The first phase labeled A constitutes the baseline logical and physical design and functional veri-
fication of the circuit. In this phase, the baseline design is drawn both as a circuit schematic and
the implementation of the physical design. The baseline is simulated for functional verification
of the performance objectives. The functional verification also serves to characterize the circuit
design objectives which are defined in section 4.3. The next phase involves the creation of the
process variation aware metamodel of the circuit design. The first step in this phase is identifica-
tion and parameterization of the design and process variables used to create the metamodel from
the extracted parasitic netlist. The parasitic netlist is used to improve the silicon accuracy of the
design. Incorporating the process parameters early on in the design phase ensures a process vari-
ation aware metamodel. An LHS sampling of the circuit from the parasitic netlist is then used by
Kriging techniques to bootstrap the sample data points infusing process variation characteristics.
We detail this process in section 5.3.1. The Kriging bootstrapped points are then used for Artificial
Network Training (ANN) of the circuit metamodel. The final phase is the process aware design
optimization phase of the circuit. The Differential Search (DS) algorithm is used together with
the created metamodel and design objectives as an input to optimize the design. The final design
parameters are then used to update the physical design for an optimal design of the circuit.
57
Kri
gin
g C
orr
elat
ion
Fu
nct
ion
Ou
tpu
t
Inp
ut
Hid
den
La
yer
(Gau
ssia
n D
ata
Po
ints
)
µ,σ
(L,W
, Vd
d, t
ox)
frequency
(Pef
orm
ance
Sh
ift
Dis
trib
uti
on
)
frequency Lo
ck_t
ime
µ,σ
(Po
wer
)
frequency
(Bas
elin
e L
ayo
ut)
(Dat
a S
amp
les)
Sta
tist
ical
An
aly
sis
Fo
M
op
tim
izat
ion
(Kri
gin
g S
urf
ace)
Mo
nte
Car
lo A
nal
ysi
s
LH
S S
amp
lin
g
fro
m S
pic
e N
etli
st
(AN
N T
rain
ing
)
(Gra
vit
atio
nal
Sea
rch
Alg
ori
thm
)
My M
x
Mw
Mz
Fw
y
Fxy
Fyz
Fxz
ay
My
Bes
t so
luti
on
so f
ar
New
My
Des
ign
Sp
ace
Fyw
Op
tim
ized
des
ign
var
iab
les
FIGURE 5.6. Proposed high level design flow.
58
The Kriging bootstrapped metamodeling process is shown in Fig. 5.7. The metamodeling
technique incorporates Kriging based techniques to infuse process variation characteristics to the
sampled data. Kriging in itself has been successfully used for metamodel generation with high
accuracy [7, 60]. The property of Kriging which makes it very appealing and lends to its high
accuracy especially for designs deep in the nanometer range is the ability to take into account the
correlation between the input parameters in performance point prediction. This can be effectively
utilized to model the correlation between the process parameters which also serves as input in the
sample data point bootstrapping. The design flow is presented in detail in Fig. 5.8.
5.5. Summary and Conclusion
Three novel design flow methodologies have been proposed in this chapter. The first design
flow incorporates Kriging techniques with optimization algorithms for the design flow process. The
second design flow improves the limitations which might appear for the Kriging based techniques
by bootstrapping Kriging sample points with Artificial Neural network models. The bootstrapped
points introduce process variation aware characteristics without subsequent weighting calculations
and combine this with ANN models. The last design flow methodology models process aware
design optimization. The experimental results of these methodologies are presented in chapter 6.
59
Sam
ple
NS
ample
3S
ample
2D
ata
1
f fA
NN
Met
amodel
Kri
gin
g
Met
amodel
f fK
rigin
g/A
NN
Met
amodel
AN
N T
rain
ing
AN
N T
rain
ing
Sam
ple
NS
ample
3S
ample
2S
ample
1
Dat
a n
-1D
ata
3D
ata
2D
ata
1D
ata
n-1
Dat
a 3
Dat
a 2
Dat
a 1
...
Kri
gin
g D
ata
y(x
0)
= ∑λ
jBj(x)
+ z
(x)
y(x
0)
= ∑λ
jBj(x)
+ z
(x)
Kri
gin
g F
unct
ion
Gen
erat
or
FIGURE 5.7. Proposed Kriging bootstrapped ANN metamodel generation flow.
60
START
Logical/Physical
Design
DRC/LVS Netlist Extraction
and Parameterization
Parameterized Design
Variables, L, W, Vdd, Tox
Design
SpecificationFunctional
Verification
Yes
No
Specifications
met?
Perform LHS
Sampling
N Kriging point estimationN Kriging bootstrapped
Data Points
N Sample
Data Points
ANN Training
DONE
Kriging bootstrapped
ANN Metamodel
Perform Design
Optimization using DSA
Yes
No Specifications
met?
DONE
Performance
Distribution Optimized [µpwr, σpwr]
freq
uen
cy
Lock_timePowerfr
equ
ency
L,W, Vdd,
tox
freq
uen
cy
A
B
C
FIGURE 5.8. Proposed process variation design optimization flow.
61
CHAPTER 6
EXPERIMENTAL RESULTS
In this chapter, the experimental results from the implementation of the proposed method-
ologies discussed in Chapter 5 are presented. The first part of this chapter gives a description of
the experimental setup and tools used. The efficiency of the proposed methodologies is illustrated
through the design of three different mixed signal circuits discussed in Chapter 4. The design
objectives, design and process parameters for each circuit are also described in the experimen-
tal setup. The proposed methodologies are tested across the circuits to show their robustness in
general mixed signal design. The results of the experiments will discuss the verification of the
metamodeling design techniques and analyze the improvement in design optimization. A com-
parative discussion of the results is also presented to compare the results of this work to existing
techniques. A summary discussion of the significance of results from the implementation of the
proposed techniques and the impact and contribution to the design of mixed-signal systems is
presented.
6.1. Experimental Setup
This section describes the experimental setup for the validation of the proposed method-
ologies. The experimental circuits used are the baseline designs of the three mixed-signal circuits
discussed in Chapter 4. The sense amplifier was implemented in two different topologies; as a
(1)conventional full latch and (2) Clamped Bitline. Both topologies were implemented on a 45nm
technology. The sense amplifiers were also designed for similar performance measures (Figures-
of-Merit (FoM))which are power consumption PSA, precharge time TPC , sense delay TSD, and
sense margin VSM . The baseline design performance measures are shown in Table 4.1. The ther-
mal sensor was also implemented using the same 45nm technology. The thermal sensor was de-
signed for power consumption using thermal sensitivity and area as constraints. The baseline
design performance measures are shown in Table 4.2. The PLL was implemented using 180nm
technology and was designed for performance measures of power consumption using the locking
time as design constraint.
62
All of the logical schematic and physical layout designs were performed using the Cadence
virtuoso platform. The full blown parasitic (RLCK) netlist is extracted and parameterized with
respect to the corresponding design variables. The parameterized netlist is used as the circuit
description for design sampling. An ocean script is created with the parameterized netlist that can
automate the design sampling procedure using MATLAB. The Spectre analog simulator was used
to perform the simulations. The algorithm used to generate the Kriging metamodels was written
using MATLAB with the help of the toolboxes mGstat [1] and SUMO [30].
A diagram showing the different tool interactions is shown in Fig. 6.1. Any design engineer
can use this as a guideline for tool usage to reproduce our results when needed to be used in their
circuit design.
CAD(Cadence on Virtuoso Platform)
OCEAN Script
MATLAB
MATLAB toolboxmGstat:Geostatistical MATLABSUMO:SUrrogate MOdeling
Steps and Tool Interaction
FIGURE 6.1. Steps and tool interaction.
6.2. Validation of Metamodel Assisted Design Optimization
In this section, experimental results that validate the metamodel assisted design method-
ology are presented. The methodology is illustrated with the sense amplifier design for both the
conventional and clamped bitline topologies, the thermal sensor and the phase locked loop (PLL).
63
The results are presented for each circuit design in two phases for each of the circuit designs. First,
following the design flow methodology, the geostatistical Kriging metamodel is generated and the
accuracy is analyzed. A sufficiently accurate metamodel is then used along with an optimization
algorithm for the design optimization phase.
6.2.1. 45nm Sense Amplifier Design
The results of the metamodeling design of the conventional and clamped bitline topologies
are shown here with FoMs of power consumption PSA, precharge time TPC , sense delay TSD,
and sense margin VSM . For both designs transistor length and width have been used as design
parameters.
6.2.1.1. Metamodel Generation and Accuracy
The first phase of validation is the accuracy analysis of the generated metamodel. To test
the accuracy of Kriging methods, the geostatistical simple and ordinary Kriging techniques were
generated using transistor width as a design parameter.
Design sample sizes of 20 and 100 sets were used to create the Kriging based metamodels.
A total of 16 metamodels were created, 4 metamodels for each FoM created from sampling sizes
of 20 and 100 using ordinary and simple Kriging. An exhaustive baseline simulation was also
done to compare the accuracy of the Kriging predicted models. A total of 1000 design points were
simulated to densely capture the design space compared to the 20 and 100 LHS points used to
generate the Kriging predicted curves. The predicted curves for the ordinary and simple Kriging
based metamodels are shown in Figure 6.2 and 6.3 respectively with Wn as the design input.
The plots also show the exhaustive design points simulations. From the plots it is seen that the
predicted Kriging metamodels for both the ordinary and simple Kriging techniques closely match
the exhaustive simulation.
A statistical analysis on both responses shows that the accuracy of the Kriging method
is very high. A summary of the statistical analysis is shown in Table 6.1 for both ordinary and
simple Kriging metamodels compared to the exhaustive design surface. The metrics used for
comparison are the Mean Square Error (MSE), the Root Mean Square Error (RMSE) and the
64
120 140 160 180 200 220 240
7.5
8
8.5
9
9.5
10
Wn (nM)
Tim
e (n
s)Ordinary Kriging Predicted Precharge Time
(a) Ordinary Kriging for precharge time
120 140 160 180 200 220 240
1.7
1.75
1.8
1.85
Wn (nM)
Tim
e (n
s)
Ordinary Kriging Predicted Delay Time
(b) Ordinary Kriging for sense delay
120 140 160 180 200 220 240
1.9
1.95
2
2.05
2.1
2.15
2.2
2.25
Wn (nM)
Wat
t(µs
)
Ordinary Kriging Predicted Average Power
(c) Ordinary Kriging for average power
120 140 160 180 200 220 240
27
27.2
27.4
27.6
27.8
28
28.2
28.4
Wn (nM)
Vo
lt(m
V)
Ordinary Kriging Predicted Margin Time
(d) Ordinary Kriging for sense margin
FIGURE 6.2. Ordinary Kriging responses using Wn as the design parameter.
correlation coefficient R2:
The results in Table 6.1 show the metamodels to be accurate with very low RMSE values.
The R2 values for the precharge time are abnormally low and could be due to experimental errors.
The experiments were repeated to increase the number of design parameters from transis-
tor width to include transistor length. For this round, only ordinary Kriging technique was imple-
mented however with increased sampling sizes to increase accuracy. In creating the metamodel,
three sets of ordinary Kriging metamodels were generated with the mGstat toolbox [1] using 100,
200 and 500 sampling points. Again all sampling techniques were done with LHS. For each design
65
120 140 160 180 200 220 240
7.5
8
8.5
9
9.5
10
Wn (nM)
Tim
e (n
s)Simple Kriging Predicted Precharge Time
simple krigingexhaustive
(a) Simple Kriging prediction for Precharge time
120 140 160 180 200 220 2401.65
1.7
1.75
1.8
1.85
Wn (nM)
Tim
e (n
s)
Simple Kriging Predicted Sense Delay Time
simple krigingexhaustive
(b) Simple Kriging prediction for Sense Delay
120 140 160 180 200 220 240
1.9
1.95
2
2.05
2.1
2.15
2.2
2.25
Wn (nM)
Wat
t(µs
)
Simple Kriging Predicted Average Power
simple kriging
exhaustive
(c) Simple Kriging prediction for Average Power
120 140 160 180 200 220 240
27
27.2
27.4
27.6
27.8
28
28.2
28.4
Wn (nM)
Vo
lt(m
V)
Simple Kriging Predicted Sense Margin
simple kriging
exhaustive
(d) Simple Kriging prediction for Sense Margin
FIGURE 6.3. Simple Kriging predicted outputs using Wn as the design parameter.
sample set, a metamodel was generated for each FoM. For comparison purposes, an exhaustive de-
sign response surface which we call the “golden surface” was also generated to compare to the
Kriging predicted surfaces.
A total of 10,000 simulations were run to created the golden surface. Figures 6.4 and 6.5
shows the golden surface for the conventional (Circuit I) and clamped bitline (Circuit II) sense
amplifiers. The corresponding ordinary Kriging predicted surfaces are shown in Figures 6.6 and
6.7 for Circuit I and Circuit II respectively. The figures shown are from the metamodel created
with 500 design sample points.
66
TABLE 6.1. Statistical analysis of the simple and ordinary Kriging predicted curve
for sample sizes of 20 and 100.
FoMs Ordinary Kriging Simple Kriging
Samples 20 100 20 100
Precharge
MSE 6.02× 10−21 3.85× 10−19 5.32× 10−21 3.63× 10−19
RMSE 7.76× 10−11 6.20× 10−10 7.29× 10−11 6.02× 10−10
R2 0.9931 0.5560 0.9939 0.5810
STD 6.95× 10−11 6.09× 10−10 6.60× 10−11 5.91× 10−10
Sense Delay
MSE 1.12× 10−23 8.27× 10−24 7.49× 10−24 4.02× 10−24
RMSE 1.02× 10−10 2.88× 10−12 2.73× 10−12 2.00× 10−12
R2 0.9984 0.9985 0.9987 0.9993
STD 8.62× 10−11 2.64× 10−12 2.29× 10−12 1.79× 10−12
Power
MSE 3.64× 10−15 4.35× 10−15 3.56× 10−15 4.69× 10−15
RMSE 6.24× 10−11 6.60× 10−08 5.96× 10−08 6.85× 10−08
R2 0.9957 0.8145 0.8486 0.8003
STD 5.75× 10−11 6.40× 10−08 5.69× 10−08 6.66× 10−08
Sense Margin
MSE 2.79× 10−09 6.31× 10−09 2.56× 10−09 4.32× 10−09
RMSE 5.28× 10−05 7.94× 10−05 5.06× 10−05 6.57× 10−05
R2 0.9987 0.9753 0.9900 0.9831
STD 2.58× 10−05 7.73× 10−05 4.79× 10−05 6.41× 10−05
It can be seen from the figures, that like Kriging predicted curves, the Kriging generated
surface closely matches the exhaustive golden surface for the corresponding circuits. To verify the
accuracy however, a statistical analysis using MSE, RMSE, R2 and standard deviation statistical
measures shows that the metamodels created are quite accurate with very low RMSE values an
average R2 values in the range of 0.98–0.99. The statistical analysis is shown in Table 6.2. The R2
values for power consumption PSA FoM are a little lower than the other FoMs. As expected, the
metamodels generated from 500 LHS sampling points are generally more accurate than the ones
67
6080
100120
150200
250300
350
0.5
1
1.5
x 10−8
Ln (nM)
Golden Surface for Precharge Time
Wn (nM)
Tim
e
(a) Golden surface for Precharge time
6080
100120
150200
250300
350
2
3
4
5
6
7
x 10−9
Ln (nM)
Golden Surface for Sense Delay
Wn (nM)
Tim
e
(b) Golden surface for Sense Delay
60
80
100
120
150200250300350
1.165
1.17
1.175
1.18
1.185
1.19
1.195
x 10−6
Ln (nM)
Golden Surface for Average Power
Wn (nM)
Po
wer
(c) Golden surface for Average Power
6080
100120
150200
250300
350
0.03
0.032
0.034
0.036
0.038
0.04
Ln (nM)
Golden Surface for Sense Margin
Wn (nM)
Vo
lt
(d) Golden surface for Sense Margin
FIGURE 6.4. Golden surface for circuit I using and Ln and Wn as design input.
generated from the 200 sampling points, and likewise for the metamodels from the 200 and 100
sampling points.
The time taken for the metamodel generation is 3.69 mins, significantly less than 72 hours
required for an exhaustive simulation.
6.2.1.2. Optimization Results
After the Kriging generated metamodels have been analyzed for accuracy, the next step in
the design flow methodology is the fast and efficient design optimization using any of the discussed
optimization algorithms. This implementation was performed using the verified ordinary Kriging
68
6080
100120
150200
250300
350
5
6
7
8
9
10
x 10−9
Wn (nM)
Golden Surface for Precharge Time
Ln (nM)
Tim
e
(a) Golden Surface for Precharge time
60
80
100
120
150200250300350
1.4
1.5
1.6
1.7
1.8
1.9
x 10−9
Ln (nM)
Golden Surface for Sense Delay
Wn (nM)
Tim
e
(b) Golden Surface for Sense Delay
6080
100120
150200
250300
350
1.9
2
2.1
2.2
2.3
2.4
2.5
x 10−6
Ln (nM)
Golden Surface for Average Power
Wn (nM)
Pow
er
(c) Golden Surface for Average Power
60
80
100
120
150
200
250
300
350
0.028
0.03
0.032
Ln (nM)
Golden Surface for Sense Margin
Wn (nM)
Vo
lt
(d) Golden Surface for Sense Margin
FIGURE 6.5. Golden surface for circuit II using and Ln and Wn as design input.
metamodels with the ACO based algorithm described in Chapter 5. The optimization scheme is
summarized in Algorithm 6, and the Kriging metamodel generated with the 500 data sample points
is used. The design optimization goal is to minimize the precharge time TPC , without violating
the power constraint. The parameters are initialized for random design points of Ln and Wn. The
algorithm goes through each iteration remembering the best solution. It updates the pheromones
by evaporation but remembers the best solution, thereby increasing the probability of more search
ants in that direction.
The values for the optimized design are shown in Table 6.3. TPC has been reduced by 65.
69
6080100120
150 200 250 300 350
4
6
8
10
12
14
16
Ln (nM)
Ordinary Kriging Predicted Precharge Time
Wn (nM)
Tim
e (n
s)
(a) Golden Surface for Precharge time
6080
100120
150200
250300
350
2
3
4
5
6
x 10−9
Ln (nM)
Ordinary Kriging Predicted Sense Delay Time
Wn (nM)
Tim
e (n
s)
(b) Golden Surface for Sense Delay
60
80
100
120
150200
250300
350
1.165
1.17
1.175
1.18
1.185
1.19
x 10−6
Ln (nM)
Ordinary Kriging Predicted Average Power
Wn (nM)
Wat
t(µs
)
(c) Golden Surface for Average Power
6080
100120
150200
250300
350
0.032
0.034
0.036
0.038
0.04
Ln (nM)
Ordinary Kriging Predicted Sense Margin
Wn (nM)
Vo
lt(m
V)
(d) Golden Surface for Sense Margin
FIGURE 6.6. Golden surface circuit I for Kriging predicted FoM’s using 500 Ln
and Wn sample points.
77 % while PSA, was increased by 0.85 %. The final design parameters for Ln and Wn are 65
nm and 300 nm respectively. The final design also increases the area cost for the physical layout
by 23.10 %. The total average time taken for design optimization using the sense amplifier as the
case study circuit is 3.9 minutes. The bulk of the time is consumed in the metamodel generation as
the ACO algorithm converges in an average time of 1.36 seconds. The process from design space
exploration to optimization is reduced by a factor of approximately 103×.
70
6080
100120
150200
250300
350
5
6
7
8
9
10
x 10−9
Wn (nM)
Ordinary Kriging Predicted Precharge Time
Ln (nM)
Tim
e (n
s)
(a) Golden Surface for Precharge time
60
80
100
120
150200
250300
350
1.4
1.5
1.6
1.7
1.8
1.9
x 10−9
Wn (nM)
Ordinary Kriging Predicted Sense Delay Time
Ln (nM)
Tim
e (n
s)
(b) Golden Surface for Sense Delay
6080
100120
150200
250300
350
2
2.1
2.2
2.3
2.4
2.5
x 10−6
Ln (nM)
Ordinary Kriging Predicted Average Power
Wn (nM)
Wat
t(µs
)
(c) Golden Surface for Average Power
5060
7080
90100
110
150200
250300
350
0.028
0.03
0.032
Ln (nM)
Ordinary Kriging Predicted Sense Margin
Wn (nM)
Vo
lt(m
V)
(d) Golden Surface for Sense Margin
FIGURE 6.7. Golden surface Circuit II for Kriging predicted FoM’s using 500 Ln
and Wn sample points.
6.2.2. 45nm Thermal Sensor
In this section, the results of the metamodel generation and the optimization of the thermal
sensor design are presented. For this design illustration, six design parameters were chosen based
on the 3 components of the thermal sensor. The widths of the NMOS and PMOS transistors in the
RO are parameterized to WNosc and WPosc respectively. Similarly, the widths of the transistors
for the 10-bit counter and 10-bit registers are parameterized to WNctr, WPctr, WNreg and WPreg
for a total of 6 design parameters.
71
TABLE 6.2. Statistical analysis of the Kriging predicted values with metamodels
created from 100, 200 and 500 sample sizes.
FoMs Ordinary Kriging
Samples 100 200 500
Precharge
MSE 2.20× 10−19 5.23× 10−20 1.84× 10−20
RMSE 4.69× 10−10 2.29× 10−10 1.36× 10−10
R2 0.9650 0.9917 0.9971
STD 4.32× 10−10 2.03× 10−10 1.27× 10−10
Sense Delay
MSE 4.22× 10−20 1.16× 10−20 4.75× 10−21
RMSE 2.05× 10−10 1.08× 10−10 6.89× 10−11
R2 0.9529 0.9871 0.9947
STD 1.89× 10−10 9.39× 10−11 6.26× 10−11
Power
MSE 1.84× 10−17 1.08× 10−17 1.02× 10−11
RMSE 3.44× 10−09 3.29× 10−09 3.20× 10−09
R2 0.8384 0.8525 0.8606
STD 1.19× 10−09 9.47× 10−10 6.06× 10−10
Sense Margin
MSE 1.12× 10−07 3.41× 10−08 9.47× 10−09
RMSE 3.35× 10−04 1.85× 10−04 9.73× 10−05
R2 0.9804 0.9940 0.9983
STD 2.98× 10−04 1.62× 10−04 9.05× 10−05
6.2.2.1. Metamodel Generation and Accuracy
A simple Kriging model was generated for the thermal sensor power consumption. In
generating the Kriging metamodels, 100 sample points were generated using the LHS design. The
generated metamodels were based on six design paramaters, thus a metamodel surface could not
be generated. The evaluation of the metamodels was done using the MSE, RMSE andR2 statistical
measures. The table in 6.4 shows the accuracy tests for the metamodels.
From the results in Table 6.4, the Kriging metamodels are sufficiently accurate with very
72
Algorithm 6 Ant Colony Optimization (ACO) Based Heuristic Algorithm for 45 nm Sense Am-
plifier
1: Initialize number of ants (solutionset)
2: Initialize iteration counter: counter← 0
3: Start with initial baseline solution (SAi)
4: Generate metamodel functions for each FoM of (SAi) with Ordinary Kriging.
5: Consider the objective of interest TPCi
6: Generate random ant nodes AL,Wi, where i = 1,2,. . . ,Nant.
7: Assign initial pheromone, τi
8: counter ← max Iteration
9: while (counter > 0) do
10: Generate ant solutions TPCi
11: Rank solutions (SAi) in set from best to worst.
12: Update Pheromone, increase pheromone for best solution and evaporate pheromone for all
others
13: result← TPCi
14: Generate new ant nodes AL,Wi,
15: counter ← counter − 1
16: end while
17: return result
TABLE 6.3. Optimized design values.
Design Precharge time Sense delay Power Sense Margin Area
TPC (ns) TSD (ns) PSA (µW) VSM (mV) µm2
Schematic 18.02 7.46 1.16 29.33 -
Layout 18.20 7.45 1.17 29.25 4.294
Optimized 6.23 2.58 1.18 35.56 5.286
Improvement 65.77 % 65.37 % -0.85 % 21.57 % 23.10 %
73
TABLE 6.4. Statistical analysis for accuracy of Kriging generated metamodel.
Metric Value
Mean Square Error (MSE) 4.36× 10−18
Root Mean Square Error(RMSE) 2.09× 10−09
Coefficient of Determination (R2) 0.9934
low MSE and RMSE values of 4.36 × 10−18 and 2.09 × 10−09. The correlation coefficient R2 is
very close to unity. The results validate the efficiency of Kriging metamodeling by producing very
accurate metamodels while greatly reducing the simulation time required. The total time taken for
the metamodel generation was approximately 30 hours, the bulk of this time being the simulation
time required for the sample points. The time however is a factor of 10 lower than approximately
300 hours required for an exhaustive simulation of the design across the entire design space.
6.2.2.2. Optimization Results
In optimizing the thermal sensor, the GSA optimization discussed in 5 is applied to the
generated metamodel with an initial number of 50 search agents and a maximum iteration of 1000
runs. The design objective of the optimization is the minimization of power consumption. A
summary of the GSA optimization flow is shown in 6.8 and the results are shown shown in Fig.
6.9. From the optimization graph, it is seen that the algorithm is able to reach an optimized solution
of 184.7 µW in about 900 iterations. The gravitational search being a heuristic algorithm, its
convergence is usually near optimal. We chose 1000 iterations based on results from previous
experiments. In the implementation of the algorithm, there is also a termination criterion where
the algorithm could also terminate before the maximum iteration.
Table 6.5 shows the final design parameters while the optimized responses of the thermal
sensor are provided in Table 6.6. Compared to the schematic baseline design, there is a 36.9%
reduction in power dissipation with an area penalty of about 45 %.
74
Gen
erat
e in
itia
l se
arch
agen
t(W
n,
Wp
)
Ev
alu
ate
ob
ject
ive
of
inte
rest
(p
ow
er)
Ran
k q
ual
ity
of
solu
tio
n
Up
dat
e m
ass
of
each
loca
tio
n
Up
dat
e g
rav
ity
co
nst
ant
and
cal
cula
te a
ttra
ctio
n
Cal
cula
te v
elo
city
an
d
up
dat
e ag
ent
loca
tio
n
(new
Wn,
Wp
)
Op
tim
izat
ion
or
Ter
min
atio
n c
rite
ria
met
?
Bes
t S
olu
tio
n
Sta
rtE
nd
FIGURE 6.8. GSA optimization flow.
75
0 100 200 300 400 500 600 700 800 900 10001.5
2
2.5
3
3.5
4
4.5
5
5.5x 10−4 Optimization using GSA
Iteration
Bes
t−so
−far
(W
)
FIGURE 6.9. GSA performance on Kriging metamodel for 45nm thermal sensor.
TABLE 6.5. Final design parameters.
Parameter Value
WNosc 215 nM
WPosc 140 nM
WNctr 313 nM
WPctr 121 nM
WNreg 224 nM
WPreg 378 nM
TABLE 6.6. Thermal sensor output comparison.
Design Average Power, (PTS) Sensitivity, (TTS) Area (µm2)
Schematic 293.1 µW 16.88 MHz/°C -
Layout 379.4 µW 9.42 MHz/°C 1221.37
Final 184.7 µW 9.42 MHz/°C 1770.98*
% Change 36.9% 44.2% 45%*
76
6.2.3. 180nm Phase Locked Loop
The results of the experimental test of the design flow methodology incorporating Kriging
techniques and the GSA algorithm applied to the design optimization of the phase locked loop
(PLL) discussed in 5 are presented. For this experiment, 21 parameters were chosen as design
variables. The transistor widths from the different components of the PLL were used as the design
variables. The list of design variables is shown in Table 6.9 with their min-max ranges. The
optimization objective was to minimize the power consumption using the locking time as a design
constraint.
6.2.3.1. Metamodel Generation and Accuracy
An ordinary Kriging metamodel was generated using similar techniques for the thermal
sensor and the sense amplifier. The analytical evaluation of the generated metamodel is shown in
Table 6.7. From the results, the RMSE for the power consumption is 6.46× 10−10 which shows a
very high accuracy. The R2 value is 0.9959 which signifies a very high accuracy also.
TABLE 6.7. Statistical analysis for accuracy of Kriging generated metamodel for
PLL power consumption.
Metric Value
Root Mean Square Error(RMSE) 6.46× 10−10
Coefficient of Determination (R2) 0.9959
6.2.3.2. Optimization Results
With the accuracy of the Kriging metamodel verified, the optimization algorithm is per-
formed to minimize the power consumption using the locking time as a constraint. The GSA
algorithm described in Chapter 5 and used in Section 6.2.1 is applied to the metamodel design.
The maximum iteration is set to 1000 with 50 initial search nodes (masses). The result of the algo-
rithm operation is shown in Fig. 6.10. It is seen from the figure that an optimal power consumption
of 1.67 mW is obtained after 377 iterations. It can also be seen that the algorithm has very fast
convergence rate due to its strong attractive features. On average, the GSA is able to converge to
77
an optimal power consumption in about 400 iterations. Table 6.8 shows the final results from the
optimization algorithm. The power consumption is reduced by approximately 79%. The locking
time is also reduced by 4 %. The range of the design variables and the final optimized values are
given in Table 6.9.
0 100 200 300 400 500 600 700 800 900 10001.65
1.7
1.75
1.8
1.85
1.9
1.95
2
2.05
2.1x 10−3 GSA Optimization for PLL
Iterations
Pow
er C
onsu
mpt
ion
FIGURE 6.10. Optimization steps of the PLL.
TABLE 6.8. Final optimization results for the PLL.
Metric Power (mW) Locking Time (ns) Area (µm2)
Baseline Design 8.27 2.74 525 × 326
Optimal Optimal 1.67 2.63 525 × 326
Reduction 79 % 4 % 0 %
6.3. Validation of Metamodel Assisted Process Variation Analysis
The experimental setup to illustrate the process variation aware methodology is similar
to the previous methodology. The 180 nm PLL circuit is also used to illustrate the efficiency of
the methodology. The proposed Kriging bootstrapped neural network aims to limit speed lost to
reiterative Kriging weight calculations. A statistical variation analysis was first performed on the
design to enable a better evaluation of the proposed methodology. A Monte Carlo analysis of
78
TABLE 6.9. Optimized parameter variables.
PLL Circuit Component Parameter Min(m) Max (m) Optimal (m)
Phase Detector
WpPD1 400n 2µ 1.53µ
WpPD1 400n 2µ 0.95µ
WpPD1 400n 2µ 1.00µ
WnPD1 400n 2µ 1.16µ
WnPD1 400n 2µ 0.52µ
WnPD1 400n 2µ 1.58µ
Charge Pump
WnCP1 400n 2µ 1.12µ
WpCP1 400n 2µ 1.32µ
WnCP2 2µ 4µ 2.07µ
WpCP2 4µ 4µ 4.72µ
LC-VCOWnLC 3µ 20µ 12.22µ
WpLC 6µ 40µ 14.83µ
Divider
WpDIV 1 400n 2µ 1.06µ
WpDIV 2 400n 2µ 1.11µ
WpDIV 3 400n 2µ 0.75µ
WpDIV 4 400n 2µ 1.78µ
WnDIV 1 400n 2µ 1.35µ
WnDIV 1 400n 2µ 1.86µ
WnDIV 1 400n 2µ 1.65µ
WnDIV 1 400n 2µ 1.96µ
WnDIV 1 400n 2µ 0.43µ
1000 simulation runs were performed for comparison to the statistical model analysis of this work.
The Monte Carlo simulations were configured for process and mismatch variations. The physical
design and Monte Carlo simulations were performed using the CADENCE Virtuoso environment.
The performance outputs characterized are the Power Consumption (PPLL), and the Locking time
79
(LckPLL). The results from the statistical analysis are presented along with the results of the
implementation of the methodology.
6.3.1. Statistical Variation Analysis
The results of the proposed statistical model characterized by the PDF Histogram plot is
shown in Figure 6.11. The plots show the PDF for both the power consumption of the PLL and
the locking time. The x-axis for Figure 11(a) shows the power and the y-axis shows the frequency
of outputs. Similarly Figure 11(b) shows the locking time and frequency of outputs respectively.
The distribution of both plots is Gaussian as expected from the nature of random process variation
modeled.
Table 6.10 shows the tabulated statistical analysis for the mean (µ) and standard deviation
(σ) of the power consumption and locking time of the PLL in comparison to the values from the
actual netlist. The mean value of the predicted power output is 0.871 mW compared to 0.877 from
the actual netlist Monte Carlo analysis with a 0.7 % error. The predicted locking time is 3.23 µs
compared to 3.24 µs again with a 0.31 % error. The accuracy of these results validates the proposed
statistical model which can be used for analysis while reducing the amount of time required for the
conventional Monte Carlo analysis. This is a significant improvement of time costs for analysis.
The simulation time for the Monte Carlo analysis on the actual netlist is about 5 days while the
Kriging metamodel generation and analysis takes only a few hours.
TABLE 6.10. Statistical analysis for accuracy of Kriging generated metamodel for
PLL power consumption.
Mean (µ) Standard Deviation (σ)
Circuit Kriging Error Circuit Kriging Error
PPLL 0.877 mW 0.871 mW 0.7 % 0.073 mW 0.072 mW 1.4 %
LckPLL 3.24 µs 3.23 µs 0.31 % 1.07 µs 0.33 µs 69.16 %
80
6 7 8 9 10x 10
−4
0
50
100
150
Power(W)
Fre
quen
cy
MonteCarlo Analysis of Power consumption
(a) Power
2 2.5 3 3.5 4x 10
−6
0
50
100
150
Time(s)
Fre
quen
cy
MonteCarlo Analysis of Locking Time
(b) Locking Time
FIGURE 6.11. Statistical analysis of the performance output for the 180nm PLL
using Kriging metamodels.
6.3.2. Metamodel Generation and Accuracy
Table 6.11 shows the accuracy of the proposed Kriging Bootstrapped Trained Neural Meta-
models. The Root Mean Square Errors (RMSE) for each of the FoMs is shown. A lower value
81
of RMSE indicates a higher accuracy. The low RMSE values thus demonstrate that the created
metamodels are sufficiently accurate and can be used for design exploration.
TABLE 6.11. Statistical accuracy of Kriging generated points.
FoM’s RMSE
Power (PPLL) 2.51 x 10 −6
Frequency (FPLL) 5.68 x 10 −13
Locking Time(LckPLL) 5.01 x 10 −12
Jitter (LckPLL) 1.69 x 10 −19
The Monte Carlo results for the various metamodels are shown in Table 6.12. A Monte
Carlo analysis on the SPICE model is used as baseline to compare the results. The results are also
compared with the bare Kriging and Artificial Neural Network (ANN) metamodels.
Table 6.10 shows the mean (µ) and standard deviation (σ) for the FoMs in each of the
metamodels. From the results, the Kriging metamodels are shown to be most accurate on both the
TABLE 6.12. Statistical analysis for accuracy of neural network metamodel for
PLL FoMs.
Circuit Kriging-ANN Kriging ANN
Value Value error Value error Value error
(%) (%) (%)
PPLLMean 2.4 mW 2.4 mW 3.2 2.5 mW 0.8 2.5 mW 0.8
STD 0.4 mW 0.3 mW 19.0 0.5 mW 21.4 0.7 mW 64.3
FPLLMean 2.6 GHz 2.5 GHz 5.6 2.6 GHz 0.1 2.7 GHz 5.4
STD 10.9 MHz 41.9 MHz 282.9 3.7 MHz 66.0 51.9 MHz 373.9
LckPLLMean 5.5 µs 5.1µs 7.2 5.5 µs 0.07 5.2 µs 5.6
STD 0.7 µs 0.4 µs 38.9 0.6 ns 10.2 1.0 µs 40.3
JPLLMean 16.8 ns 14.7ns 10.2 16.8ns 0.1 17.9 ns 6.6
STD 1.3 ps 4.5 ps 240.9 0.7ps 48.5 19.1 ps 1352.2
82
(a) Mean
(b) STD
FIGURE 6.12. Comparative results with Kriging and neural network.
83
1.5 2 2.5 3 3.5 4x 10
−3
0
50
100
150
200
Power(w)
Fre
quen
cyMonteCarlo Analysis of Power consumption
(a) Power
2.4 2.45 2.5 2.55 2.6 2.65 2.7x 10
9
0
5
10
15
20
Frequency(Hz)
Freq
uenc
y
MonteCarlo Analysis of Frequency
(b) Frequency
3 3.5 4 4.5 5 5.5 6 6.5 7x 10
−6
0
20
40
60
80
100
120
Time(s)
Fre
quen
cy
MonteCarlo Analysis of Locking Time
(c) Locking Time
1.4 1.5 1.6 1.7 1.8 1.9 2x 10
−10
0
50
100
150
200
Time(s)
Fre
quen
cy
MonteCarlo Analysis of Jitter
(d) Jitter
FIGURE 6.13. Statistical analysis of FoMs using Kriging bootstrapped trained neu-
ral network based metamodeling.
mean (µ) and (σ) values for all FoMs. The Kriging bootstrapped neural network metamodel on the
other hand is shown to be more accurate on the (σ) values than the plain neural network metamodel
but less accurate on the (µ) values. This difference is expected because while bootstrapping infuses
the autocorrelation property of Kriging based techniques, some error is also introduced as well.
Fig. 6.12 shows the errors for the (µ) and (σ) as a bar chart. The histograms of the Monte
Carlo analysis for the Kriging bootstrapped, Kriging and neural network metamodels are shown in
Figures 6.13–6.15.
The value of the Kriging bootstrapped metamodeling technique is due to the reduced time
cost for design exploration. While Kriging models may be more accurate, the time cost for design
exploration for a large design space still becomes too expensive due to the repetitive solution of
large-dimension systems of equations for each sample point. One obvious goal for metamodel use
84
2.3 2.4 2.5 2.6 2.7 2.8x 10
−3
0
20
40
60
80
Power(w)
Fre
quen
cyMonteCarlo Analysis of Power consumption
(a) Power
2.645 2.65 2.655 2.66 2.665 2.67x 10
9
0
20
40
60
80
100
120
Frequency(Hz)
Freq
uenc
y
MonteCarlo Analysis of Frequency
(b) Frequency
4.8 4.9 5 5.1 5.2 5.3 5.4 5.5x 10
−6
0
20
40
60
80
Time(s)
Fre
quen
cy
MonteCarlo Analysis of Locking Time
(c) Locking Time
1.66 1.67 1.68 1.69 1.7 1.71 1.72x 10
−10
0
20
40
60
80
Time(s)
Fre
quen
cy
MonteCarlo Analysis of Jitter
(d) Jitter
FIGURE 6.14. Statistical analysis of FoMs using Kriging based metamodeling.
is the improved time cost. Table 6.13 shows the time cost for the Monte Carlo Analysis on each
metamodel.
TABLE 6.13. Monte carlo time analysis comparison for metamodels.
Model Kriging-ANN Kriging ANN
Time 19 s 468 s 19 s
Speedup 24.63× 1 24.63×
The Table shows a speedup of approximately 25 times in time cost for the Monte Carlo Sim-
ulation of 1000 runs for the Kriging bootstrapped model over traditional Kriging. The significant
improvement in time cost is large enough to mitigate the minimal error incurred in the metamodel.
The overall use of metamodels significantly reduces the simulation time over SPICE models. It
may be noted that the Monte Carlo simulation time on the SPICE models is approximately 5 days,
85
3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6x 10
−3
0
50
100
150
200
250
Power(w)
Fre
quen
cyMonteCarlo Analysis of Power consumption
(a) Power
2.65 2.7 2.75 2.8 2.85 2.9 2.95x 10
9
0
20
40
60
80
Frequency(Hz)
Freq
uenc
y
MonteCarlo Analysis of Frequency
(b) Frequency
0 1 2 3 4 5x 10
−6
0
10
20
30
40
50
Time(s)
Fre
quen
cy
MonteCarlo Analysis of Locking Time
(c) Locking Time
0.5 1 1.5 2 2.5 3 3.5x 10
−10
0
50
100
150
200
250
Time(s)
Fre
quen
cy
MonteCarlo Analysis of Jitter
(d) Jitter
FIGURE 6.15. Statistical analysis of FoMs using neural network based metamodeling.
which highlights the huge time gain with the use of metamodels.
To show improvement of Kriging techniques over similar behavioral modeling used for
analysis, results from selected works are compared to this work. The results of the comparison are
shown in Table 6.14.
TABLE 6.14. Statistical analysis for accuracy of Kriging generated metamodel for
PLL power consumption.
Technique Power Locking Time
Mean Error Mean Error
[39] Quasi-SA - - 3.45 2.2 %
[27] ANN 0.90 mW 0.14 % 3.22 µs 0.7 %
[This work] Kriging 0.87 mW 0.7 % 3.23 µs 0.33 %
86
The results in Table 6.14 are not quite comprehensive but serve to show a perspective of
the capacity of Kriging techniques.
6.4. Results Analysis
The experimental results have been illustrated with three different analog designs to illus-
trate the robustness of the methodology. While the results show that geostatistical Kriging meta-
models are very accurate and lead to efficient design exploration we present some discussion to
compare the results with perspective to other design methods proposed in the literature. However,
the technology node, operating voltage, topology, and design objectives are quite different and
hence fair direct comparison is not possible. We present some perspective comparisons to similar
designs presented in literature.
6.4.1. Comparative Perspective with Related Research
A perspective comparison of the performance of existing techniques is shown in Table 6.15.
The RO design in [25] implements Tabu Search (TSA) and Simulated Annealing (SAA), and the
performance results are compared with the thermal sensor in this paper. The RO has 6 transistors
and 2 design parameters with the TSA and SSA running for 12 and 15 iterations, while the thermal
sensor has 896 transistors and 6 parameter designs and optimizing in about 900 iterations. The
computational time in Table 6.15 has been normalized to compare with the thermal sensor design.
The proposed method had an improved simulation and optimization of 17.46 s compared to 31.04
s and 241.25s for the SAA and TSA respectively.
TABLE 6.15. Comparative analysis of metamodel and optimization.
Metric On Netlist With Metamodel
TSA SSA GSATSA SSA GSA
Polynomial Polynomial Simple
Kriging
Time 140.4 s 175.8 s 1.08 x 106 s 7.18 ms 0.77 ms 17.46 s
Normalized 4.72 x 10 6 s 4.73 x 10 6 s 1.08 x 106 s 241.25 s 31.04 s 17.46 s
87
For a comparative perspective, we used the thermal sensor design and compare to other
thermal sensor designs with similar approach [62, 17, 12]. The proposed thermal sensor design
has an improved sensitivity of 0.097°Cwhich is higher than the other selected designs. The overall
power consumption is 184.7 µW which is higher than the design presented in [62]. The design in
[62], however has an operating voltage of 0.3 V compared to an operating voltage of 1 V for our
design. Our design also has a smaller area overhead cost of 0.001 mm2 compared to the related
designs. The 45nm technology is similar to the thermal sensor presented in [17] which also had a
low area of 0.04 mm2.
6.4.2. Qualitative Comparison
Table 6.16 shows a brief comparison on metamodeling based designs and optimization
techniques. The comparisons are only qualitative and illustrate the perspective of the proposed de-
sign methodology. In [72, 73, 58, 60], Kriging metamodeling techniques have been used for analog
design modeling while in [29], ANN and polynomial are used. In [72, 73], only metamodels have
been presented without an optimization algorithm. Both [58, 29] used optimization algorithms on
the metamodels for design optimization. The accuracy of the metamodels are shown in column
4 of Table 6.16. The metric for analysis used is RMSE except in the case of [73] where MSE
is used. In [59], Kriging techniques are used to explore the accuracy of metamodeling for high
dimensional designs, especially designs with a characteristically high non-linear response. The
proposed method results in a higher accuracy than the compared methods. The selected methods
however have been performed on different circuits and different Figures-of-Merit, hence a direct
comparison only just shows perspective.
6.5. Summary and Conclusion
Experimental results from the implementation of the proposed metamodel design optimiza-
tion flows were presented and discussed. The use of 3 different analog circuits serves to establish
the robustness of the proposed methods. The proposed methodology was implemented in various
forms testing the applications of different Kriging techniques. Ordinary and simple Kriging tech-
niques were explored in generating the metamodels along with sample size selection. From our
88
TABLE 6.16. Relative comparison of Kriging metamodeling techniques and grav-
itational search algorithm.
Work Test Metamodeling Accuracy Optimization
Circuit Technique Technique
You [72] Integrated Op-Amp Kriging 0.5658 -
Yu [73]Ring Oscillator Kriging 0.5325% (MSE) -
LC-VCO 0.5563% (MSE) -
Okobiah [58] Sense Amplifier Kriging 3.2× 10−9 ACO
Garitselov [29] PLLPolynomial 0.5658
ABCANN 51.24
Okobiah [59] PLL Kriging 6.46× 10−10 GSA
experience and the results of the experiments, we believe a sample size of 100 is sufficient to create
accurate metamodels for analog design optimizations.
The accuracy of the generated Kriging metamodels was also very high and more impor-
tantly the use of metamodeling achieves an average design speed up 25 ×. The results also show
a significant increase in the process variation awareness of the analog designs using the proposed
methodology.
The proposed methodology was implemented using simulated annealing, ant colony and
gravitational search algorithms. These algorithms heuristic in nature with fast convergence rates
where chosen because of their optimal characteristics.
89
CHAPTER 7
CONCLUSIONS AND FUTURE RESEARCH
The work in this dissertation contributes to the solution of problems relating to the design
of Analog Mixed/Signal System-on-a-Chip (AMS-SoC) due to the aggressive scaling of CMOS
technology. The effects of scaling include increased static power consumption due to increased
leakage, the uncontrollable effects of random process variation and the unfeasible overall design
effort. The overarching problem tackled is reducing design effort (increasing accuracy and reduc-
ing computation time) in the face of the problems resulting from the scaling of technology in the
design of AMS-SoC systems. Solutions to these problems have been proposed and demonstrated
through the previous chapters of this dissertation. A summary of the solutions proposed to these
problems is given in this chapter. A brief discussion on the impact and significance of the solutions
is also presented and directions for future research are outlined.
7.1. Summary
In this dissertation, a novel design flow methodology has been proposed to reduce the over-
bearing burden faced by designers. The proposed methodology uses geostatistical Kriging meta-
modeling techniques for fast and accurate design space exploration. Kriging based techniques
generate metamodels that accurately capture the global design space along with the effects of pro-
cess variation. They achieve this unique feature by taking into account the spatial autocorrelation
of the input design and process parameters. The process parameters (such as threshold voltage,
oxide thickness and random doping) which generally exhibit larger variations especially in deep
nanometer dimensions are also strongly correlated and thus the use of Kriging based techniques
in metamodeling design increases the prediction accuracy. Comparisons with exhaustive simula-
tions show that Kriging predicted metamodels are very accurate with very low RMSE and highR2.
The accurate Kriging based metamodels have been combined with optimization algorithms which
efficiently explore the design space for optimal design parameters. The optimization algorithms
explored were simulated annealing, ant colony optimization, and gravitational search algorithm
(GSA)
90
The design flow methodology was presented in three phases:
(1) As an overall design flow methodology incorporating Kriging techniques with an opti-
mization algorithm for fast and accurate AMS-SoC system design.
(2) As a process variation analysis flow, capturing and analyzing the effects of process vari-
ation early in the design flow using the proposed Kriging bootstrapped artificial neural
network technique.
(3) As a process variation aware optimization flow process where the effects of process vari-
ation are captured at two levels of design and performance optimization.
The proposed methodologies were implemented with the design of 3 Analog/Mixed-Signal
circuits: 45nm sense amplifier, 45nm thermal sensor and a 180nm Phase Locked Loop (PLL). In
the design of the sense amplifier, the proposed methodology was demonstrated as effective pro-
ducing an optimized design with a 65.77 % improved Precharge Time (TPC). The implementation
of the methodology on the design of the thermal sensor showed a 36.9 % improved power con-
sumption. This was achieved while reducing design space exploration by about 90% compared to
exhaustive simulation methods. Finally, the proposed solution was tested with the design of the
180nm PLL for Private Mobile Radio (PMR) applications. The design simulation and optimization
took approximately 13.5 hours compared to several days of simulation which conventional CAD
techniques take. The statistical variation analysis of the power consumption and the locking time
of the PLL shows a mean error of 0.7 % and 0.33 % respectively when compared to conventional
Monte Carlo methods. This shows a minimized statistical error while significantly reducing the
simulation time by about 25 times.
7.2. Conclusion
The work in this dissertation has shown the advantage of geostatistical Kriging techniques
in metamodeling design of AMS-SoCs systems. The hypothesis is that the Kriging techniques of
spatial autocorrelation can be efficiently applied to model the spatial correlation of the variation of
the design and process parameters in deep nanometer technology. The illustrative design process
of three AMS circuits has been used to show the efficiency of the proposed methodology. In
91
the design of the thermal sensor and PLL, 6 and 21 design parameters respectively were used.
However, 100 sample points were used for the creation of the metamodels. The accuracy of both
design was consistently high, which supports the scalability of the proposed methodology.
7.3. Future Research
A limitation of Kriging techniques however is the time required to recalculate the weight-
ing average since each predicted point is unique. The bootstrapped Kriging technique proposed
attempts to mitigate some of this by using bootstrapped Kriging points on neural network mod-
els, which shows promising results. The design flow methodology proposed and illustrated in this
work has been shown for the single performance optimization. For future research, the proposed
methodology could be extended to multi-objective optimization algorithms. It would also be inter-
esting to include techniques to improve the nominal accuracy of the designs.
92
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