george mason university ece 645 lecture 7 fpga embedded resources
TRANSCRIPT
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George Mason University
ECE 645Lecture 7
FPGA Embedded Resources
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Resources
• FPGA Embedded Resources web pageavailable from the course web page
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Recommended reading• XAPP463 Using Block RAM in Spartan-3 Generation FPGAs
Google search: XAPP463
• XAPP464 Using Look-Up Tables as Distributed RAM in Spartan-3 Generation FPGAs
Google search: XAPP464
• XST User Guide, Section: Coding Techniques
Google search: XST User Guide (PDF) http://www.xilinx.com/itp/xilinx4/data/docs/xst/hdlcode.html (HTML)
• ISE In-Depth Tutorial, Section: Creating a CORE Generator Module
Google search: ISE In-Depth Tutorial
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ECE 448 – FPGA and ASIC Design with VHDL
Use of Embedded FPGA Resourcesin SHA-3 Candidates
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Technology Low-cost High-performance
120/150 nm Virtex 2, 2 Pro
90 nm Spartan 3 Virtex 4
65 nm Virtex 5
45 nm Spartan 6
40 nm Virtex 6
Xilinx FPGA Devices
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Altera FPGA Devices
Technology Low-cost Mid-range High-performanc
e130 nm Cyclone Stratix
90 nm Cyclone II Stratix II
65 nm Cyclone III Arria I Stratix III
40 nm Cyclone IV Arria II Stratix IV
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ECE 448 – FPGA and ASIC Design with VHDL
FPGA Embedded Resources
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ECE 448 – FPGA and ASIC Design with VHDL
Embedded Multipliers
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10ECE 448 – FPGA and ASIC Design with VHDL
RAM blocks
Multipliers
Logic blocks
Multipliers in Spartan 3
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
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Number of Multipliers per Spartan 3 Device
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Combinational and Registered Multiplier
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Dedicated Multiplier Block
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Interface of a Dedicated Multiplier
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Unsigned vs. Signed Multiplication
1111
1111x
11100001
15
15x
225
1111
1111x
00000001
-1
-1x
1
Unsigned Signed
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Cyclone II
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Embedded Multiplier Block Overview
Each Cyclone II has one to three columns of embedded multipliers.
Each embedded multiplier can be configured to support
One 18 x 18 multiplierTwo 9 x 9 multipliers
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Number of Embedded Multipliers
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Multiplier Block Architecture
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Two Multiplier Types
Two 9x9 multiplierTwo 9x9 multiplier 18x18 multiplier18x18 multiplier
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Multiplier Stage
• Signals signa and signb are used to identify the signed and unsigned inputs.
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3 Ways to Use Dedicated Hardware
• Three (3) ways to use dedicated
(embedded) hardware– Inference – Instantiation– CoreGen in Xilinx
MegaWizard Plug-In Manager in Altera
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library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
entity mult18x18 is generic ( word_size : natural := 18); port (
a : in std_logic_vector(word_size-1 downto 0); b : in std_logic_vector(word_size-1 downto 0); c : out std_logic_vector(2*word_size-1 downto 0));end entity mult18x18;
architecture infer of mult18x18 isbegin c <= std_logic_vector(unsigned(a) * unsigned(b));end architecture infer;
Inferred Multiplier
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Forcing a particular implementation in VHDL
Synthesis tool: Xilinx XST
Attribute MULT_STYLE: string;
Attribute MULT_STYLE of c: signal is block;
Allowed values of the attribute:
block – dedicated multiplier
lut - LUT-based multiplier
pipe_block – pipelined dedicated multiplier
pipe_lut – pipelined LUT-based multiplier
auto – automatic choice by the synthesis tool
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Instantiation for Spartan 3 FPGAs
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CORE Generator
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ECE 448 – FPGA and ASIC Design with VHDL
DSP Units
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Xilinx XtremeDSP
• Starting with Virtex 4 family, Xilinx introduced DSP48 block for high-speed DSP on FPGAs
• Essentially a multiply-accumulate core with many other features
• Now also in Spartan-3A, Spartan 6, Virtex 5, and Virtex 6
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DSP48 Slice: Virtex 4
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Simplified Form of DSP48
Adder Out = (Z ± (X + Y + CIN))
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Choosing Inputs to DSP Adder
P = Adder Out = (Z ± (X + Y + CIN))
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DSP48E Slice : Virtex5
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New in Virtex 5 Compared to Virtex 4
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Stratix III DSP Unit
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ECE 448 – FPGA and ASIC Design with VHDL
Embedded Memories
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Memory Types
Memory
RAM ROM
Single port Dual port
With asynchronous
read
With synchronous
read
Memory
Memory
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Memory Types in Xilinx
Memory
Distributed (MLUT-based)
Block RAM-based(BRAM-based)
Inferred Instantiated
Memory
Manually Using Core Generator
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Memory Types in Altera
Memory
Distributed (ALUT-based,
Stratix III onwards)
Memory block-based
InferredInstantiated
Memory
Manually Using MegaWizard Plug-In Manager
Small size(512)
Large size(144K, 512K)
Medium size(4K, 9K, 20K)
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Inference vs. Instantiation
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FPGA Distributed
Memory
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COUT
D Q
CK
S
REC
D Q
CK
REC
O
G4G3G2G1
Look-UpTable
Carry&
ControlLogic
O
YB
Y
F4F3F2F1
XB
X
Look-UpTable
F5IN
BYSR
S
Carry&
ControlLogic
CINCLKCE SLICE
CLB Slice
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16-bit SR
16 x 1 RAM
4-input LUT
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Xilinx Multipurpose LUT
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RAM16X1S
O
DWE
WCLKA0A1A2A3
RAM32X1S
O
DWEWCLKA0A1A2A3A4
RAM16X2S
O1
D0
WEWCLKA0A1A2A3
D1
O0
=
=LUT
LUT or
LUT
RAM16X1D
SPO
D
WE
WCLK
A0
A1
A2
A3
DPRA0 DPO
DPRA1
DPRA2
DPRA3
or
Distributed RAM
• CLB LUT configurable as Distributed RAM• An LUT equals 16x1 RAM• Cascade LUTs to increase RAM size
• Synchronous write• Asynchronous read
• Can create a synchronous read by using extra flip-flops
• Naturally, distributed RAM read is asynchronous
• Two LUTs can make• 32 x 1 single-port RAM• 16 x 2 single-port RAM• 16 x 1 dual-port RAM
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FPGA Block RAM
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Block RAM
Spartan-3Dual-PortBlock RAM
Po
rt A
Po
rt B
Block RAM
• Most efficient memory implementation• Dedicated blocks of memory
• Ideal for most memory requirements• 4 to 104 memory blocks
• 18 kbits = 18,432 bits per block (16 k without parity bits)
• Use multiple blocks for larger memories• Builds both single and true dual-port RAMs• Synchronous write and read (different from distributed RAM)
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RAM blocks
Multipliers
Logic blocks
RAM Blocks and Multipliers in Xilinx FPGAs
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
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Block RAM can have various configurations (port aspect ratios)
0
16,383
1
4,095
40
8,191
20
2047
8+10
1023
16+20
16k x 1
8k x 2 4k x 4
2k x (8+1)
1024 x (16+2)
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Block RAM Port Aspect Ratios
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Single-Port Block RAM
DI[w-p-1:0]
DO[w-p-1:0]
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Dual-Port Block RAM
DIA[wA-pA-1:0]
DOA[wA-pA-1:0]
DOA[wB-pB-1:0]
DIB[wB-pB-1:0]
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RAMB4_S18_S9
Port A Out18-Bit Width
Port B In2k-Bit Depth
Port A In1K-Bit Depth
Port B Out9-Bit Width
DOA[17:0]
DOB[8:0]
WEA
ENA
RSTA
ADDRA[9:0]
CLKA
DIA[17:0]
WEB
ENB
RSTB
ADDRB[10:0]
CLKB
DIB[8:0]
Dual-Port Bus Flexibility
• Each port can be configured with a different data bus width • Provides easy data width conversion without any additional logic
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0, ADDR[12:0]
1, ADDR[12:0]
RAMB4_S1_S1
Port B Out1-Bit Width
DOA[0]
DOB[0]
WEA
ENA
RSTA
ADDRA[12:0]
CLKA
DIA[0]
WEB
ENB
RSTB
ADDRB[12:0]
CLKB
DIB[0]
Port B In8K-Bit Depth
Port A Out1-Bit Width
Port A In8K-Bit Depth
Two Independent Single-Port RAMs
• To access the lower RAM• Tie the MSB address bit to Logic Low
• To access the upper RAM• Tie the MSB address bit to Logic High
• Added advantage of True Dual-Port• No wasted RAM Bits
• Can split a Dual-Port 16K RAM into two Single-Port 8K RAM
• Simultaneous independent access to each RAM
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The embedded memory structure consists of columns of M4K memory blocks that can be configured as RAM, first-in first-out (FIFO) buffers, and ROM
Cyclone II Memory Blocks
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The M4K memory blocks support the following modes:
Single-port RAM (RAM:1-Port) Simple dual-port RAM (RAM: 2-Port) True dual-port RAM (RAM:2-Port) Tri-port RAM (RAM:3-Port) Single-port ROM (ROM:1-Port) Dual-port ROM (ROM:2-Port)
Memory Modes
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Single-Port ROM
• The address lines of the ROM are registered
• The outputs can be registered or unregistered
• A .mif file is used to initialize the ROM contents
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Stratix II TriMatrix Memory
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Stratix II TriMatrix Memory
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Stratix III & Stratix IV TriMatrix Memory
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Stratix II & III Shift-Register Memory Configuration
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ECE 448 – FPGA and ASIC Design with VHDL
Test Circuit Example
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ATHENa Example includingembedded FPGAresources
test_circuit:
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Generic Multiplier (1)
entity mult isgeneric
( vendor : integer := XILINX -- vendor : XILINX=0, ALTERA=1 multiplier_type : integer:= MUL_DEDICATED; -- multiplier_type : MUL_LOGIC_BASED=0, MUL_DSP_BASED=1
WIDTH : integer := 8 -- width : width (fixed width for input and output) );port (
a : in std_logic_vector (WIDTH-1 downto 0);b : in std_logic_vector (WIDTH-1 downto 0);s : out std_logic_vector (WIDTH-1 downto 0)
);end mult;
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Generic Multiplier (2)architecture mult of mult isbegin
xil_dsp_mult_gen : if (multiplier_type = MUL_DEDICATED and vendor = XILINX) generatemult_xil: entity work.mult(xilinx_dsp) generic map ( WIDTH => WIDTH )
port map (a => a, b => b, s => s );end genxil_logic_mult_gen : if (multiplier_type=MUL_LOGIC_BASED and vendor = XILINX) generatemult_xil: entity work.mult(xilinx_logic) generic map ( WIDTH => WIDTH )
port map (a => a, b => b, s => s );end generate;
alt_dsp_mult_gen : if (multiplier_type=MUL_DEDICATED and vendor = ALTERA) generatemult_alt: entity work.mult(altera_dsp) generic map ( WIDTH => WIDTH )
port map (a => a, b => b, s => s );end generate;alt_logic_mult_gen : if (multiplier_type=MUL_LOGIC_BASED and vendor = ALTERA) generatemult_alt: entity work.mult(altera_logic) generic map ( WIDTH => WIDTH )
port map (a => a, b => b, s => s );end generate;
end mult;
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Generic Multiplier (3)architecture xilinx_logic of mult is
signal temp1 : std_logic_vector(2*WIDTH -1 downto 0);attribute mult_style : string ;attribute mult_style of temp1: signal is "lut”;begin
temp1 <= STD_LOGIC_VECTOR(unsigned(a) * unsigned(b));s <= temp1(WIDTH-1 downto 0);
end xilinx_logic;
architecture xilinx_dsp of mult issignal temp2 : std_logic_vector(2*WIDTH -1 downto 0);attribute mult_style : string ;attribute mult_style of temp2: signal is "block”;begin
temp2 <= STD_LOGIC_VECTOR(unsigned(a) * unsigned(b));s <= temp2(WIDTH-1 downto 0);
end xilinx_dsp;
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Generic Multiplier (4)architecture altera_logic of mult is
signal temp : std_logic_vector(2*WIDTH -1 downto 0);attribute multstyle : string ;attribute multstyle of altera_logic : architecture is "logic”;begin
temp <= STD_LOGIC_VECTOR(unsigned(a) * unsigned(b));s <= temp(WIDTH-1 downto 0);
end altera_logic;
architecture altera_dsp of mult issignal temp : std_logic_vector(2*WIDTH -1 downto 0);attribute multstyle : string ;attribute multstyle of altera_dsp : architecture is "dsp";begin
temp <= STD_LOGIC_VECTOR(unsigned(a) * unsigned(b));s <= temp(WIDTH-1 downto 0);
end altera_dsp;
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FPGA Distributed
Memory
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COUT
D Q
CK
S
REC
D Q
CK
REC
O
G4G3G2G1
Look-UpTable
Carry&
ControlLogic
O
YB
Y
F4F3F2F1
XB
X
Look-UpTable
F5IN
BYSR
S
Carry&
ControlLogic
CINCLKCE SLICE
CLB Slice
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16-bit SR
16 x 1 RAM
4-input LUT
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Xilinx Multipurpose LUT
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71
RAM16X1S
O
DWE
WCLKA0A1A2A3
RAM32X1S
O
DWEWCLKA0A1A2A3A4
RAM16X2S
O1
D0
WEWCLKA0A1A2A3
D1
O0
=
=LUT
LUT or
LUT
RAM16X1D
SPO
D
WE
WCLK
A0
A1
A2
A3
DPRA0 DPO
DPRA1
DPRA2
DPRA3
or
Distributed RAM
• CLB LUT configurable as Distributed RAM• An LUT equals 16x1 RAM• Cascade LUTs to increase RAM size
• Synchronous write• Asynchronous read
• Can create a synchronous read by using extra flip-flops
• Naturally, distributed RAM read is asynchronous
• Two LUTs can make• 32 x 1 single-port RAM• 16 x 2 single-port RAM• 16 x 1 dual-port RAM
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72
Generic
Inferred
RAM
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73
Distributed versus Block RAM Inference
Examples:1. Distributed single-port RAM with asynchronous read
2. Distributed dual-port RAM with asynchronous read
3. Distributed single-port RAM with "false" synchronous read
4. Block RAM with synchronous read (no version with asynchronous read!)
More excellent RAM examples from XST Coding Guidelines:http://toolbox.xilinx.com/docsan/xilinx4/data/docs/xst/hdlcode.html(Click on RAMs)
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74
Distributed RAM with asynchronous read
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75
Distributed single-port RAM with asynchronous read
LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all; entity raminfr is generic ( data_bits : integer := 32; -- number of bits per RAM word addr_bits : integer := 3); -- 2^addr_bits = number of words in RAM port (clk : in std_logic; we : in std_logic; a : in std_logic_vector(addr_bits-1 downto 0); di : in std_logic_vector(data_bits-1 downto 0); do : out std_logic_vector(data_bits-1 downto 0)); end raminfr;
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76
Distributed single-port RAM with asynchronous read
architecture behavioral of raminfr is type ram_type is array (2**addr_bits-1 downto 0) of std_logic_vector (data_bits-1 downto 0); signal RAM : ram_type; begin process (clk) begin if (clk'event and clk = '1') then if (we = '1') then RAM(conv_integer(unsigned(a))) <= di; end if; end if; end process; do <= RAM(conv_integer(unsigned(a))); end behavioral;
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77
Report from Synthesis
Resource Usage Report for raminfr Mapping to part: xc3s50pq208-5Cell usage:GND 1 useRAM16X4S 8 usesI/O ports: 69I/O primitives: 68IBUF 36 usesOBUF 32 usesBUFGP 1 use
I/O Register bits: 0Register bits not including I/Os: 0 (0%)
RAM/ROM usage summarySingle Port Rams (RAM16X4S): 8
Global Clock Buffers: 1 of 8 (12%)
Mapping Summary:Total LUTs: 32 (2%)
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78
Report from Implementation
Design Summary:Number of errors: 0Number of warnings: 0Logic Utilization:Logic Distribution: Number of occupied Slices: 16 out of 768 2% Number of Slices containing only related logic: 16 out of 16 100% Number of Slices containing unrelated logic: 0 out of 16 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number of 4 input LUTs: 32 out of 1,536 2% Number used as 16x1 RAMs: 32 Number of bonded IOBs: 69 out of 124 55% Number of GCLKs: 1 out of 8 12%
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79
Distributed dual-port RAM with asynchronous read
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80
Distributed dual-port RAM with asynchronous read
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity raminfr is generic ( data_bits : integer := 32; -- number of bits per RAM word addr_bits : integer := 3); -- 2^addr_bits = number of words in RAM port (clk : in std_logic; we : in std_logic; a : in std_logic_vector(addr_bits-1 downto 0); dpra : in std_logic_vector(addr_bits-1 downto 0); di : in std_logic_vector(data_bits-1 downto 0); spo : out std_logic_vector(data_bits-1 downto 0); dpo : out std_logic_vector(data_bits-1 downto 0)); end raminfr;
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81
Distributed dual-port RAM with asynchronous read
architecture syn of raminfr is type ram_type is array (2**addr_bits-1 downto 0) of
std_logic_vector (data_bits-1 downto 0); signal RAM : ram_type; begin process (clk) begin if (clk'event and clk = '1') then if (we = '1') then RAM(conv_integer(unsigned(a))) <= di; end if; end if; end process; spo <= RAM(conv_integer(unsigned(a))); dpo <= RAM(conv_integer(unsigned(dpra))); end syn;
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82
Report from Synthesis
Resource Usage Report for raminfr Mapping to part: xc3s50pq208-5Cell usage:GND 1 useI/O ports: 104I/O primitives: 103IBUF 39 usesOBUF 64 usesBUFGP 1 useI/O Register bits: 0Register bits not including I/Os: 0 (0%)
RAM/ROM usage summaryDual Port Rams (RAM16X1D): 32
Global Clock Buffers: 1 of 8 (12%)
Mapping Summary:Total LUTs: 64 (4%)
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83
Report from Implementation
Design Summary:Number of errors: 0Number of warnings: 0Logic Utilization:Logic Distribution: Number of occupied Slices: 32 out of 768 4% Number of Slices containing only related logic: 32 out of 32 100% Number of Slices containing unrelated logic: 0 out of 32 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number of 4 input LUTs: 64 out of 1,536 4% Number used for Dual Port RAMs: 64 (Two LUTs used per Dual Port RAM) Number of bonded IOBs: 104 out of 124 83% Number of GCLKs: 1 out of 8 12%
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84
Distributed RAM with "false" synchronous read
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85
Distributed RAM with "false" synchronous read
LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;USE ieee.std_logic_unsigned.all; entity raminfr is generic ( data_bits : integer := 32; -- number of bits per RAM word addr_bits : integer := 3); -- 2^addr_bits = number of words in RAM port (clk : in std_logic; we : in std_logic; a : in std_logic_vector(addr_bits-1 downto 0); di : in std_logic_vector(data_bits-1 downto 0); do : out std_logic_vector(data_bits-1 downto 0)); end raminfr;
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86
Distributed RAM with "false" synchronous read
architecture behavioral of raminfr is type ram_type is array (2**addr_bits-1 downto 0) of std_logic_vector (data_bits-1 downto 0); signal RAM : ram_type; begin process (clk) begin if (clk'event and clk = '1') then if (we = '1') then RAM(conv_integer(unsigned(a))) <= di; end if;
do <= RAM(conv_integer(unsigned(a))); end if; end process; end behavioral;
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87
Report from Synthesis
Resource Usage Report for raminfr Mapping to part: xc3s50pq208-5Cell usage:FD 32 usesGND 1 useRAM16X4S 8 usesI/O ports: 69I/O primitives: 68IBUF 36 usesOBUF 32 usesBUFGP 1 use
I/O Register bits: 0Register bits not including I/Os: 32 (2%)
RAM/ROM usage summarySingle Port Rams (RAM16X4S): 8
Global Clock Buffers: 1 of 8 (12%)
Mapping Summary:Total LUTs: 32 (2%)
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88
Report from Implementation
Design Summary:Number of errors: 0Number of warnings: 0Logic Utilization: Number of Slice Flip Flops: 32 out of 1,536 2%Logic Distribution: Number of occupied Slices: 16 out of 768 2% Number of Slices containing only related logic: 16 out of 16 100% Number of Slices containing unrelated logic: 0 out of 16 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number of 4 input LUTs: 32 out of 1,536 2% Number used as 16x1 RAMs: 32 Number of bonded IOBs: 69 out of 124 55% Number of GCLKs: 1 out of 8 12%
Total equivalent gate count for design: 4,355
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89
Block RAM with synchronous read
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90
Block RAM with synchronous read (write first mode)
LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all; entity raminfr is generic ( data_bits : integer := 32; -- number of bits per RAM word addr_bits : integer := 3); -- 2^addr_bits = number of words in RAM port (clk : in std_logic; we : in std_logic; a : in std_logic_vector(addr_bits-1 downto 0); di : in std_logic_vector(data_bits-1 downto 0); do : out std_logic_vector(data_bits-1 downto 0)); end raminfr;
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91
Block RAM with synchronous read (write first mode) cont'd
architecture behavioral of raminfr is type ram_type is array (2**addr_bits-1 downto 0) of std_logic_vector
(data_bits-1 downto 0); signal RAM : ram_type; signal read_a : std_logic_vector(addr_bits-1 downto 0);
begin process (clk) begin if (clk'event and clk = '1') then if (we = '1') then RAM(conv_integer(unsigned(a))) <= di; end if;
read_a <= a; end if; end process; do <= RAM(conv_integer(unsigned(read_a)));end behavioral;
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92
Block RAM Waveforms – WRITE_FIRST mode
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93
Report from Synthesis
Resource Usage Report for raminfr Mapping to part: xc3s50pq208-5Cell usage:GND 1 useRAMB16_S36 1 useVCC 1 useI/O ports: 69I/O primitives: 68IBUF 36 usesOBUF 32 usesBUFGP 1 use
I/O Register bits: 0Register bits not including I/Os: 0 (0%)
RAM/ROM usage summaryBlock Rams : 1 of 4 (25%)Global Clock Buffers: 1 of 8 (12%)
Mapping Summary:Total LUTs: 0 (0%)
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94
Report from Implementation
Design Summary:Number of errors: 0Number of warnings: 0Logic Utilization:Logic Distribution: Number of Slices containing only related logic: 0 out of 0 0% Number of Slices containing unrelated logic: 0 out of 0 0% *See NOTES below for an explanation of the effects of unrelated logic Number of bonded IOBs: 69 out of 124 55% Number of Block RAMs: 1 out of 4 25% Number of GCLKs: 1 out of 8 12%
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95
Generic
Inferred
ROM
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96
Distributed ROM with asynchronous read
LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;USE ieee.std_logic_unsigned.all; entity rominfr is generic ( data_bits : integer := 10; -- number of bits per ROM word addr_bits : integer := 3); -- 2^addr_bits = number of words in ROM port (a : in std_logic_vector(addr_bits-1 downto 0); do : out std_logic_vector(data_bits-1 downto 0)); end rominfr;
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97
Distributed ROM with asynchronous read
architecture behavioral of rominfr is type rom_type is array (2**addr_bits-1 downto 0) of std_logic_vector (data_bits-1 downto 0); constant ROM : rom_type := ("0000110001", "0100110100", "0100110110", "0110110000", "0000111100", "0111110101", "0100110100", "1111100111"); begin do <= ROM(conv_integer(unsigned(a))); end behavioral;
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98
Using
CORE
Generator
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CORE Generator
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CORE Generator
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101
FPGA
specific memories
(Instantiation)
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102
RAM 16x1 (1)
library IEEE;use IEEE.STD_LOGIC_1164.all;
library UNISIM;use UNISIM.all;
entity RAM_16X1_DISTRIBUTED is port(
CLK : in STD_LOGIC; WE : in STD_LOGIC; ADDR : in STD_LOGIC_VECTOR(3 downto 0); DATA_IN : in STD_LOGIC; DATA_OUT : out STD_LOGIC
);end RAM_16X1_DISTRIBUTED;
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RAM 16x1 (2)architecture RAM_16X1_DISTRIBUTED_STRUCTURAL of
RAM_16X1_DISTRIBUTED is-- part used by the synthesis tool, Synplify Pro, only;-- ignored during simulation
attribute INIT : string; attribute INIT of RAM_16x1s_1: label is "0000”;
component ram16x1sgeneric(
INIT : BIT_VECTOR(15 downto 0) := X"0000");port(
O : out std_ulogic; -- note std_ulogic not std_logicA0 : in std_ulogic;A1 : in std_ulogic;A2 : in std_ulogic;A3 : in std_ulogic;D : in std_ulogic;WCLK : in std_ulogic;WE : in std_ulogic);
end component;
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RAM 16x1 (3)
begin
RAM_16x1s_1: ram16x1s generic map (INIT => X"0000")port map
(O => DATA_OUT, A0 => ADDR(0), A1 => ADDR(1), A2 => ADDR(2), A3 => ADDR(3), D => DATA_IN, WCLK => CLK, WE => WE );
end RAM_16X1_DISTRIBUTED_STRUCTURAL;
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105
RAM 16x8 (1)
library IEEE;use IEEE.STD_LOGIC_1164.all;
library UNISIM;use UNISIM.all;
entity RAM_16X8_DISTRIBUTED is port(
CLK : in STD_LOGIC; WE : in STD_LOGIC; ADDR : in STD_LOGIC_VECTOR(3 downto 0); DATA_IN : in STD_LOGIC_VECTOR(7 downto 0); DATA_OUT : out STD_LOGIC_VECTOR(7 downto 0)
);end RAM_16X8_DISTRIBUTED;
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RAM 16x8 (2)architecture RAM_16X8_DISTRIBUTED_STRUCTURAL of
RAM_16X8_DISTRIBUTED is-- part used by the synthesis tool, Synplify Pro, only; -- ignored during simulation
attribute INIT : string;attribute INIT of RAM_16x1s_1: label is "0000";
component ram16x1sgeneric(
INIT : BIT_VECTOR(15 downto 0) := X"0000");port(
O : out std_ulogic;A0 : in std_ulogic;A1 : in std_ulogic;A2 : in std_ulogic;A3 : in std_ulogic;D : in std_ulogic;WCLK : in std_ulogic;WE : in std_ulogic);
end component;
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RAM 16x8 (3)begin
GENERATE_MEMORY:for I in 0 to 7 generate
RAM_16x1_S_1: ram16x1s generic map (INIT => X"0000")port map (O => DATA_OUT(I),
A0 => ADDR(0), A1 => ADDR(1), A2 => ADDR(2),
A3 => ADDR(3), D => DATA_IN(I), WCLK => CLK, WE => WE );
end generate;
end RAM_16X8_DISTRIBUTED_STRUCTURAL;
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108
ROM 16x1 (1)
library IEEE;use IEEE.STD_LOGIC_1164.all;
library UNISIM;use UNISIM.all;
entity ROM_16X1_DISTRIBUTED is port( ADDR : in STD_LOGIC_VECTOR(3 downto 0);
DATA_OUT : out STD_LOGIC );
end ROM_16X1_DISTRIBUTED;
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109
ROM 16x1 (2)architecture ROM_16X1_DISTRIBUTED_STRUCTURAL of ROM_16X1_DISTRIBUTED
is -- part used by the synthesis tool, Synplify Pro, only; -- ignored during simulation
attribute INIT : string;attribute INIT of rom16x1s_1: label is "F0C1";
component ram16x1sgeneric(
INIT : BIT_VECTOR(15 downto 0) := X"0000");port(
O : out std_ulogic;A0 : in std_ulogic;A1 : in std_ulogic;A2 : in std_ulogic;A3 : in std_ulogic;D : in std_ulogic;WCLK : in std_ulogic;WE : in std_ulogic);
end component;
signal Low : std_ulogic := '0';
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ROM 16x1 (3)
begin
rom16x1s_1: ram16x1s generic map (INIT => X"F0C1")
port map (O=>DATA_OUT,
A0=>ADDR(0), A1=>ADDR(1), A2=>ADDR(2), A3=>ADDR(3), D=>Low, WCLK=>Low, WE=>Low
);
end ROM_16X1_DISTRIBUTED_STRUCTURAL;
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Block RAM library components
Component Data Cells Parity Cells Address Bus Data Bus Parity Bus
Depth Width Depth Width
RAMB16_S1 16384 1 - - (13:0) (0:0) -
RAMB16_S2 8192 2 - - (12:0) (1:0) -
RAMB16_S4 4096 4 - - (11:0) (3:0) -
RAMB16_S9 2048 8 2048 1 (10:0) (7:0) (0:0)
RAMB16_S18 1024 16 1024 2 (9:0) (15:0) (1:0)
RAMB16_S36 512 32 512 4 (8:0) (31:0) (3:0)
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Component declaration for BRAM (1)
-- Component Declaration for RAMB16_S1 -- Should be placed after architecture statement but before begincomponent RAMB16_S1 -- synthesis translate_off generic ( INIT : bit_vector := X"0"; INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; ………………………………… INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; SRVAL : bit_vector := X"0"; WRITE_MODE : string := "WRITE_FIRST"); -- synthesis translate_on port (DO : out STD_LOGIC_VECTOR (0 downto 0) ADDR : in STD_LOGIC_VECTOR (13 downto 0); CLK : in STD_ULOGIC; DI : in STD_LOGIC_VECTOR (0 downto 0); EN : in STD_ULOGIC; SSR : in STD_ULOGIC; WE : in STD_ULOGIC); end component;
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Genaral template of BRAM instantiation (1)
-- Component Attribute Specification for RAMB16_{S1 | S2 | S4} -- Should be placed after architecture declaration but before the begin-- Put attributes, if necessary -- Component Instantiation for RAMB16_{S1 | S2 | S4} -- Should be placed in architecture after the begin keyword RAMB16_{S1 | S2 | S4}_INSTANCE_NAME : RAMB16_S1 -- synthesis translate_off generic map ( INIT => bit_value, INIT_00 => vector_value, INIT_01 => vector_value, …………………………….. INIT_3F => vector_value, SRVAL=> bit_value, WRITE_MODE => user_WRITE_MODE) -- synopsys translate_on port map (DO => user_DO, ADDR => user_ADDR, CLK => user_CLK, DI => user_DI, EN => user_EN, SSR => user_SSR, WE => user_WE);
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INIT_00 : BIT_VECTOR := X"014A0C0F09170A04076802A800260205002A01C5020A0917006A006800060040";INIT_01 : BIT_VECTOR := X"000000000000000008000A1907070A1706070A020026014A0C0F03AA09170026";INIT_02 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";INIT_03 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";……………………………………………………………………………………………………………………………………INIT_3F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000")
0000F0
0000F1
0000F2
0000F3
0000F4
0000FE
0000FF
INIT_3FADDRESS
002610
091711
03AA12
0C0F13
014A14
00001E
00001F
INIT_01ADDRESS
004000
000601
006802
006A03
091704
0C0F0E
014A0F
INIT_00ADDRESS
Addresses are shown in red and
data corresponding to the same
memory location is shown in black
ADDRESSDATA
Initializing Block RAMs 1024x16
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Component declaration for BRAM (2)
VHDL Instantiation Template for RAMB16_S9, S18 and S36 -- Component Declaration for RAMB16_{S9 | S18 | S36} component RAMB16_{S9 | S18 | S36} -- synthesis translate_off generic ( INIT : bit_vector := X"0"; INIT_00 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3E : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3F : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_00 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_07 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000"; SRVAL : bit_vector := X"0"; WRITE_MODE : string := "WRITE_FIRST"; );
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Component declaration for BRAM (2)
-- synthesis translate_on port (DO : out STD_LOGIC_VECTOR (0 downto 0); DOP : out STD_LOGIC_VECTOR (1 downto 0); ADDR : in STD_LOGIC_VECTOR (13 downto 0); CLK : in STD_ULOGIC; DI : in STD_LOGIC_VECTOR (0 downto 0); DIP : in STD_LOGIC_VECTOR (0 downto 0); EN : in STD_ULOGIC; SSR : in STD_ULOGIC; WE : in STD_ULOGIC); end component;
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-- Component Attribute Specification for RAMB16_{S9 | S18 | S36} -- Component Instantiation for RAMB16_{S9 | S18 | S36} -- Should be placed in architecture after the begin keyword RAMB16_{S9 | S18 | S36}_INSTANCE_NAME : RAMB16_S1 -- synthesis translate_off generic map ( INIT => bit_value, INIT_00 => vector_value, . . . . . . . . . . INIT_3F => vector_value, INITP_00 => vector_value, …………… INITP_07 => vector_value SRVAL => bit_value, WRITE_MODE => user_WRITE_MODE) -- synopsys translate_on port map (DO => user_DO, DOP => user_DOP, ADDR => user_ADDR, CLK => user_CLK, DI => user_DI, DIP => user_DIP, EN => user_EN, SSR => user_SSR, WE => user_WE);
Genaral template of BRAM instantiation (2)
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Block RAM Waveforms – WRITE_FIRST mode
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Block RAM Waveforms – READ_FIRST mode
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Block RAM Waveforms – NO_CHANGE mode