Generating Code From DAGs

Directed Ascyclic Graph (DAG)

• A tree structure such that nodes may have more than one parent

• Multiple parents are allowed so that an expression can be used more than once

Redundant Expressions

DAG for (a+b)+(a+b)

b

+

a

+

Updated Variables

The expression i = i + 1with updated variable highlighted

1

+(i)

i

Code to Optimize

g = c * (a + b) + (a + b)

c = a + b

a = (c * d) + (e – f)

Convert Code to Trees

+

=

g

+*

+c

ba

ba

+

=

c

dc

+

=

a

– *

fe

ba

Convert Tree to DAG

+ (G)

*

+c

ba

+ (G)

*

+ (C)c

ba

+ (G)

*

+ (C)c

– *

fed

+(A)

ba

Schedule DAG Nodes• The first operator scheduled will be the last

evaluated• Because a DAG can have more than one root, start

at rightmost root• Nodes are added to DAG from left to right, so

rightmost is the last to be created and added to graph

• Work left-to-right within sub-DAG scheduling each operator in turn

• Within a sub-DAG, schedule an operator if all of its parents have been scheduled

Scheduled Nodes

ba

+ 4 (G)

* 5

+ 6 (C)c

– 3 * 2

fed

+ 1 (A)

Determining Virtual RegistersStart at node with schedule number 1• Assign the node that currently has the lowest

schedule number m and has not already been assigned to a register set to the next sequential virtual register set Vn, where n = 1,2, …

• Recursively assign each left node in the tree under m to virtual register set Vn so long as its lowest schedule number parent belongs to Vn

• Continue until all nodes are assigned virtual regisers

Virtual Registers Assigned

ba

+ 4 (G) V3

* 5 V3

+ 6 (C) V1

c

– 3 V2* 2 V1

fed

+ 1 (A) V1

Virtual Register Span• A virtual register’s span is the nodes it is needed for• Two virtual registers may be mapped into the same

hardware registers if their spans do not overlap• V1 is mapped alone to R1 since its span is from

node 1 to node 6• V2 and V3 are mapped into R2 since their spans do

not overlap

Register Span

V1

V2

V3

1-6

1-3

4-5

Code Generation

• Generate code from highest schedule number to lowest schedule number

• Make sure that register that is saved is real register that virtual register at that node maps to

• Delay stores until code for lowest schedule number parent is about to be output

Code Generation

(1) Load a, r1 (7) Load e, r2

(2) Add b, r1 (8) Sub f, r2

(3) load c, r2 (9) Store c, r1

(4) Mult r1, r2 (10) Mult d, r1

(5) Add r1, r2 (11) Add r2, r1

(6) Store g, r2 (12) Store a, r1

ba

+ 4 (G) r2

* 5 r2

+ 6 (C) r1c

– 3 r2* 2 r1

fed

+ 1 (A) r1

Node Scheduling

cb

d+ 4

+ 3* 2

a

+ 1

cb

+ 4

+ 3* 2

+ 1

da

a * (b + c) + (b + c) + d

(b + c) * a + d + (b + c)

Virtual Registers

cb

d+ 4 V3

+ 3 V2* 2 V1

a

+ 1 V1

cb

+ 4 V1

+ 3 V2V1 * 2

+ 1 V1

da

Register Span

V1

V2

V3

1-2

2-4

3-4

Register Span

V1

V2

1-4

1-3

Real Registers

cb

d+ 4 R3

+ 3 R2* 2 R1

a

+ 1 R1

cb

+ 4 R1

+ 3 R2R1 * 2

+ 1 R1

da

Code ComparisonLoad b, r3 Load b, r1

Add c, r3 Add c, r1

Move r3, r2 Load d, r2

Add d, r2 Add r1, r2

Load a, r1 Mult a, r1

Mult r3, r1 Add r2, r1

Add r2, r1

Aliasing

• When aliasing is included in DAGs, code generation becomes more complicted

• For example, assignment to one array element, say a(i) may effect the value of a seemingly different array element, a(j)

• DAGs must be generated so that aliasing is handled

Problems

1. Stores cannot be delayed. For example, a(i) = j must be stored immediately, because later a(k) could be referenced where i = k

2. An assignment to an alias must kill all previous references to that alias. For example

a(i) = j;a(k) = m; /* this kills the association of j with a(i)

*/

3. The order of writes to, and reads from, aliased data objects must be preserved

DAG for j = a(i)

ia

Ind

(j)

DAG for a(i) = j

ia

Ind (%1)

DAG for a(i) = j

ia

Ind (%1)

j (%1)

DAG for a(k) = m

ka

Ind (%1)

m (%2)

DAG for a(i) = j; k = a(m);

ia

Ind (%1) j(%1 )

ma

Ind (%2)

(k)

ia

Ind (%1)

ma

Ind (%2)

(k)

j(%1 )