Gate-tunable selective operation of single electron/hole transistor modesin a silicon single quantum dot at room temperature

Sejoon Lee,1,a) Youngmin Lee,2 Emil B. Song,3 Kang L. Wang,3 and Toshiro Hiramoto4

1Quantum-functional Semiconductor Research Center, Dongguk University-Seoul, Seoul 100-715,South Korea2Department of Semiconductor Science, Dongguk University-Seoul, Seoul 100-715, South Korea3Department of Electrical Engineering, University of California, Los Angeles, California 90095, USA4Institute of Industrial Science, University of Tokyo, Tokyo 153-8505, Japan

(Received 5 December 2012; accepted 13 February 2013; published online 25 February 2013)

We demonstrate a gate-tunable selective operation of single-electron-transistor (SET) and single-

hole-transistor (SHT) in a unit silicon (Si) quantum dot (QD) system at room temperature. The

small sized Si-QD (�7 nm) with well-defined tunnel barriers, which are formed along the pþ-i-nþ

Si nanowire in both the conduction band and the valence band, permits the alternative use of

quantum states for electrons or holes to be selected by the polarity of the gate bias. The device

shows clear Coulomb blockade and negative differential-conductance oscillations on both

gate-tunable SET and SHT modes as a result of quantum transport in the pþ-i-nþ Si QD system.VC 2013 American Institute of Physics. [http://dx.doi.org/10.1063/1.4793564]

A single electron device, where the electron tunnels one

by one through a quantum dot (QD), has opened up an effec-

tive way to overcome the limits of which current comple-

mentary metal-oxide-semiconductor technology possesses.1

In a semiconductor QD single-charge device, the carrier

transport inevitably depends on the charge polarity of the

majority carrier. For instance, the electron-transport of a

single-electron transistor (SET) only takes place in the con-

duction band at a positive bias regime, and vice versa for a

single-hole transistor (SHT). This results in the unipolar

transport behavior of SET and SHT, which bounds the

ability to operate the device at a broad voltaic-bias range and

possibly restricts the expansion of device functionalities.

Many attempts were made to bypass such intrinsic hurdles.

For instance, a combination of SET and SHT functions has

been demonstrated on a common silicon (Si) QD by connect-

ing four separate contacts for each polarity,2 and bipolar

electronic-transport behaviors have been investigated in a

resonant tunneling device that operates at cryogenic temper-

atures below 4.2 K.3,4 On the other hand, very recently, an

alternatively selectable electron/hole transport has been dem-

onstrated at elevated temperatures by the usage of a graphene

QD.5–8 Because of the ambipolar conduction properties of

graphene,9 the device exhibits Coulomb blockade (CB)

effects at continuous voltaic-bias regimes regardless of the

voltage signs. In the application point of view, however,

many obstacles still remain when trying to utilize graphene

(e.g., a lack of energy band-gap and a difficulty in doping

technique).9,10 Regardless of the extensive efforts made to

replace Si, technical and scientific knowledge accumulated

on Si offers an advantage for rapid innovations.11,12 By

exploiting Si SETs, several concepts have been proposed to

put a step closer into quantum information. Multi-value

arithmetic logics,13 single-electron ratchets,14 single electron

shuttles,15 single-electron counting,16 and stochastic data

processing17 are just a few examples that elucidate the possi-

bilities of achieving quantum computation.

In this Letter, we report on the alternative operation of

SET and SHT in a unit device—a gated pþ-i-nþ Si QD tran-

sistor—at room temperature. The alternative use of quantum

states in either the conduction band or the valence band can

be selected depending on the gate voltage polarities. The

electrical characteristics and the transport mechanisms of the

Si QD device are analyzed and discussed in detail.

The gated pþ-i-nþ QD transistor was fabricated using a

patterned [100] Si NW [Fig. 1(a)]. First, a [100] Si NW

(w� 40 nm and l� 200 nm) was patterned on a semi-

insulating (100) silicon-on-insulator substrate (p� 1015 cm�3)

using electron-beam lithography. Then, by applying sequen-

tial processes of helicon dry-etching, isotropic wet-etching

(NH4OH/H2O2/H2O), and thermal oxidation, the width of the

Si-NW was reduced to be <5 nm. After this step, the volumet-

ric undulation of the isotropic-etching on the nanowire (NW)

results in a self-formed Si QD with double barriers on

each side [Fig. 1(b)]. The diameter of the as-fabricated Si

nanowire-channel is �5 nm [Fig. 1(c)]. Since the subband

modulation from the quantum confinement is much stronger

in the narrow regions (�5 nm) compared to the central region

(�5 nm),2 one can expect that the narrow regions will act as

the tunneling barriers while the central region will show QD

features [Fig. 1(d)]. Finally, the pþ (p� 1020 cm�3) drain and

nþ (n� 1020 cm�3) source were formed by ion implantation

(BF2þ, Pþ), and the gate stacks of polycrystalline-Si/SiO2 were

created with a gate-all-around (GAA) structure. The device

fabrication process in details was described in our previous

report.2

A structure, composed of a pþ-i-nþ junction formed

along a drain-channel-source, should operate as a pþ-i-nþ

diode under a source-drain bias voltage (VDS) where the

drain current (ID) can be tuned by the gate voltage (VG).

This allows the fabricated device to behave as a gate-tunable

ambipolar QD transistor. Figure 2(a) shows the VG depend-

ence of the ID-VDS characteristics. At VG¼ 0 V, a clear

a)Author to whom correspondence should be addressed; Electronic mail:

sejoon@dongguk.edu.

0003-6951/2013/102(8)/083504/4/$30.00 VC 2013 American Institute of Physics102, 083504-1

APPLIED PHYSICS LETTERS 102, 083504 (2013)

rectifying behavior appears at a turn-on voltage (VT) of

�1.0 V, which is consistent with the built-in-potential (Vbi)

of �1.1 V along the pþ-i-nþ junction. When a positive VG

(> 0 V) is applied, the VT slightly increases and then reduces

because the i-Si changes to n-Si [Fig. 2(a)]. Starting from

VG� 1.5 V, a negative differential conductance (NDC) peak

appears. Upon increasing VG> 3.7 V, the device shows cur-

rent oscillations with multiple NDCs [Fig. 2(b)].

In a pþ-i-nþ junction device, the appearance of NDC

originates from either band-to-band tunneling18,19 or reso-

nant tunneling.3,4 In band-to-band tunneling, only the strong

band bending under high reverse bias enables the depletion

width to be thin enough for Esaki-tunneling to take place. In

our device, however, we observe NDC in the positive VDS

bias regime, which strongly suggests the observed NDC to

be responsible for resonant tunneling by modulating the VDS

[inset of Fig. 2(b)]. Similarly, when a negative VG is applied,

a type conversion from i-Si to p-Si occurs and leads to a

reduction in VT [inset of Fig. 2(a)]. After VG exceeds

�2.0 V, the current plateaus (CP) begin to appear.

Considering that the NDC behaviors in ID-VDS charac-

teristics are also tuned by VG, one may expect the device to

operate as a gate-selectable SET/SHT device because the

gate-tunable NDC features indicates that the device consists

of a small QD with the double-barrier tunnel-junction sys-

tem.20–23 To examine the single-electron transport properties,

thus, the ID-VG characteristics of the device are investigated

at various VDS. At VDS<VT [Fig. 3(a)], the current remains

less than a few tens of pA regardless of VG and starts to gradu-

ally increase as VDS increases. When VDS approaches VT

(i.e., VDS¼ 0.9 V), the device exhibits oscillatory behavior

with multiple CPs, which arises from the sudden variations of

channel conductance at specific VG values.

FIG. 2. ID-VDS characteristics at (a) VG¼ 0–3.5 V and (b) VG¼ 3.7–4.3 V

of the gated pþ-i-nþ Si QD transistor. The inset of (a) shows the ID-VDS

curves at various �VG. The inset of (b) illustrates the NDC behavior due to

the existence of quantum levels. The solid and dashed lines represent the on-

and off-resonance states, respectively.

FIG. 3. ID-VG characteristics for the gated pþ-i-nþ Si QD transistor at (a)

VDS¼ 0.5–0.9 V and (b) VDS¼ 1.0–1.2 V. The dashed-line in (a) displays

the G-VG curve at VDS¼ 0.9 V. The inset of (b) represnets the gate-tunable

selctive-operation of SET/SHT modes; i.e., the electron-tranfer at þVG and

the hole-transfer at �VG.

FIG. 1. (a) Schematic of the gated pþ-i-nþ Si QD transistor formed along a

[100] Si NW. (b) SEM image of the undulated [100] Si-NW after isotropic

wet-etching. (c) Cross-sectional TEM image of the Si NW with GAA gate-

stacks. (d) Expected potential profiles in the energy-band scheme of pþ-i-nþ

Si QD transistor along the undulated Si-NW.

083504-2 Lee et al. Appl. Phys. Lett. 102, 083504 (2013)

The above behavior hints that the device starts to oper-

ate in a Coulomb blockade regime when VDS reaches VT.

After aligning the energy bands by VDS�VT, the þVG

will lower the dot potential, allowing the electrons in the

nþ region to overcome the one-electron-addition energy;

hence, they transport through the barriers via the quantum

states of the QD and reach the pþ region [see also Figs.

5(e) and 5(f)]. On the other hand, the �VG will raise the

dot potential, permitting the holes in the pþ region to flow

into the nþ region [see also Fig. 5(h)]. These result in a

gate-tunable selective operation of SET/SHT modes in a

single device. To clarify the above hypothesis, we examine

the ID-VG at VDS� 1.0 V (�VT) [Fig. 3(b)]. The device

clearly displays the Coulomb blockade oscillation (CBO)

peaks in both þVG and �VG regions from a continuous

sweep of VG [Fig. 3(b)], and it confirms the gate-tunability

of selective SET/SHT operation [inset of Fig. 3(b)]. Here,

we note that, as we increase VDS, the CBO peaks shift to

lower |VG| values. This is attributed to the reduction of

Vbi, which results in the decrease of the potential deviation

between the first excited state of the dot and the Fermi

level of the carrier reservoir. Additionally, the less noticea-

ble CBOs in the SET mode are thought to originate from

the low tunneling barriers associated with weaker subband

modulation in the conduction band for the [100] Si-NW

than the valence band [inset of Fig. 3(b)].2

Room temperature operation of a single electron device

requires the one-electron-addition energy (Ea¼ECþDe,where EC is the charging energy and De is the spacing of quan-

tum levels) to be sufficiently greater than the thermal energy

(Ethffi 25.9 meV at 300 K).11 The Ea of a QD SET/SHT is

given by Ea¼r�e�DVG,21–23 where DVG is the width of the

Coulomb gap and r is the gate modulation factor (r¼CG/

Cdot). The Cdot is the total dot capacitance coupling to the

gate, drain, and source (i.e., Cdot¼CGþCDþCS). In order to

estimate the Ea, we extract the DVG (�971 mV in average)

from the ID-VG curve at VDS¼ 1.0 V because at this point the

bands align and, therefore, the contribution of the depletion

capacitance can be presumably excluded [see also Fig. 5].

The gate modulation factor r is related to the VG- and

VDS-dependent broadening of the Coulomb gap, which can

be traced from the Coulomb diagram of the device.21–24 As

shown in Fig. 4, triangular-shaped CB regions appear instead

of the typical rhombus-shaped CB diamonds because the de-

vice only operates in the forward bias (VDS> 0) regime. The

arrows indicate CB regimes with distinguishable slopes,

a¼CG/(CGþCS) and b¼�CG/CD.21–23 Here, we note that

we used the slopes aSHT and bSET at VDS� 1.0 V to deter-

mine the capacitance ratio of the device, where the device

satisfies the band alignment condition and thus the overesti-

mation from series-capacitances from n-nþ (S) and p-pþ (D)

junctions can be ruled out. The estimated capacitance ratio is

CG:CD:CS¼ 1:1.82:2.96; hence, the gate-modulation factor

of r is approximately 0.17 (¼CG/Cdot).

Based on the above, the Ea of the device is �168 meV,

which is 6-times larger than the Eth at RT (¼ 25.9 meV) and

thus renders a clear observation of CBOs at RT.11 According

to the previous report,25 the empirical dot size of a spherical

Si QD is �7 nm when Ea¼�170 meV. In a Si QD with

ddot� 7 nm, the theoretical value of De is �65 meV;26,27

hence, EC is�105 meV. The 2.5-times greater De and 4-times

greater EC than Eth at RT corroborate the clear appearance of

both CBO and NDC at RT in our device. Furthermore, in pre-

vious reports,20–25 De of >60 meV has been experimentally

observed in Si QDs with ddot� 7 nm. As a consequence, the

formation of an ultra-small dot in the GAA matrix leads to

large values of EC and De, and thus manifests a gate-tunable

alternative-operation of SET/SHT at RT.

To help understand the operation scheme, we explain

the transport mechanism of our device. At the equilibrium

state [Fig. 5(a)], a depletion region with 1=2Vbi would be

formed at both-sides on i-Si, when equivalent concentra-

tions of electron/hole in the source/drain (S/D) are

assumed. For convenience, the barrier heights and the

quantum level spacings are assumed to be identical in both

the conduction and valence bands. When a small forward

VDS is applied, Vbi at each side will be lowered

[Fig. 5(b)]; however, the carriers in both pþ and nþ

regions will be blocked by each tunnel barrier. As VDS

increases (0<VDS<VT), a small ID will start to flow

because of thermal generation. Under this condition, a pos-

itive VG will accumulate electrons in the i-Si and lower

the dot potential so that the electrons can move from the S

to D through the QD [Fig. 5(c)]. However, because of the

residual Vbi at the i-pþ junction, the transport is dominated

by diffusion carriers and leads to the recombination current

near the D. Similarly, a negative VG will create hole trans-

port in the valence band [Fig. 5(d)].

At VDSffiVT (¼ Vbi), the band-alignment condition is

achieved [Fig. 5(e)]. Similar to the situations in Figs. 5(c)

and 5(d), the VG will enable the carrier transport via the CB

events [Fig. 5(f)]. In other words, the electrons can transfer

from nþ-Si to the inverted i-Si region (i.e., n-Si near the

pþ-Si) through the quantum states of the dot, which results

in the appearance of CBO. At this stage, the transport would

be mostly governed by the drift carriers due to the absence

of Vbi and a minimized depletion width. By further increas-

ing VDS (VT) [Fig. 5(g)], the NDC will appear when large

quantum-level-spacings exist. These explain the appearance

of CBO and NDC in Figs. 2 and 3. In the negative VG bias

regime [Fig. 5(h)], a similar situation can be constituted in

the valence band; i.e., the hole carriers transfer through the

FIG. 4. Contour plot of ID as functions of VDS and VG of the gated pþ-i-nþ

Si QD transistor. The substhreshold region in VG¼ 0–1.5 V is governed by

the inversion/depletion in the i-Si region.

083504-3 Lee et al. Appl. Phys. Lett. 102, 083504 (2013)

quantum states of the valence band. Therefore, by switching

the polarity of VG, a selective operation of SET and SHT

modes can be accomplished in a single device.

In summary, the gate-tunable selective operation of

SET/SHT in a unit device was demonstrated at room temper-

atures. The small sized (�7 nm) Si QD shows a large one-

electron addition energy (Ea� 168 meV) greater than the

thermal energy at RT (Ethffi 25.9 meV). The device shows

clear current oscillations and negative differential conduct-

ance, arising from the Coulomb blockade effect and resonant

tunneling, in both the electron and hole transport regimes.

We believe that the gate selectivity of SET and SHT in a sin-

gle device could benefit applications on realizing quantum

information.

This research was supported by the National Research

Foundation of Korea (Grant Nos. NRF-2009-0077230 and

NRF-2012-0006943 (FY: 2010-2012)) funded by the Korean

government of Ministry of Education, Science and

Technology (MEST).

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FIG. 5. Mechanism for the gate-tunable selctive-operation of SET/SHT. Band

diagrams at various bias conditions: (a) Equilibrium, (b) VDS<Vbi and

VG¼ 0 V, (c) VDS<Vbi and VG> 0 V, (d) VDS<Vbi and VG< 0 V, (e)

VDSffiVbi and VG¼ 0 V, (e) VDS>Vbi and VG> 0 V, (g) VDSVbi and

VG> 0 V, and (f) VDSffiVbi and VG< 0 V. EC, EV, and EF labeled in each

band diagram represent the conduction band maximum, valence band maxi-

mum, and Fermi level of source/drain, respectively.

083504-4 Lee et al. Appl. Phys. Lett. 102, 083504 (2013)