future trend of microprocessor designvojin/classes/eec280/f2002/yunges… · robert yung ©2002...
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![Page 1: Future Trend of Microprocessor Designvojin/CLASSES/EEC280/F2002/yungES… · Robert Yung ©2002 Intel Corp. Page Page 33 Microprocessor Evolution • 4004 – 1971 – 2300 transistors](https://reader035.vdocuments.site/reader035/viewer/2022071012/5fca1678c14e9710a730fcef/html5/thumbnails/1.jpg)
©2002©2002 Intel Corp.Intel Corp.Page Page 11
Robert YungRobert Yung
Future Trend of Microprocessor Design:Future Trend of Microprocessor Design:Challenges and RealitiesChallenges and Realities
Robert Yung, Ph.D.Robert Yung, Ph.D.Chief technology officer, Enterprise ProcessorsChief technology officer, Enterprise Processors
(([email protected]@intel.com))
Stefan RusuStefan RusuSenior Principal EngineerSenior Principal Engineer(([email protected]@intel.com))
Kenneth ShoemakerKenneth ShoemakerSenior Principal EngineerSenior Principal Engineer
(([email protected]@intel.com))
Intel CorporationIntel CorporationESSCIRC / ESSDERC 2002ESSCIRC / ESSDERC 2002
Sept 25, 2002Sept 25, 2002
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©2002©2002 Intel Corp.Intel Corp. Page Page 22Robert YungRobert Yung
AgendaAgenda
•• Process Driven TrendsProcess Driven Trends–– Moore’s LawMoore’s Law–– Transistors: Frequency, Power, Gate LengthTransistors: Frequency, Power, Gate Length–– Interconnection: WiresInterconnection: Wires–– Power DissipationPower Dissipation–– PackagingPackaging
•• Architecture Driven TrendsArchitecture Driven Trends–– Increased ParallelismIncreased Parallelism–– Cache And MemoryCache And Memory–– Input/OutputInput/Output
•• ConclusionConclusion
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©2002©2002 Intel Corp.Intel Corp. Page Page 33Robert YungRobert Yung
Microprocessor Evolution
•• 40044004–– 19711971–– 2300 transistors2300 transistors–– 10um process10um process–– 2”, 50mm wafer2”, 50mm wafer–– 12mm12mm22
–– 108 kHz108 kHz
•• PentiumPentium®® 4 processor4 processor–– 2002 (31 yrs)2002 (31 yrs)–– 55M (24K X)55M (24K X)–– 0.13um (1/77 X)0.13um (1/77 X)–– 12”, 300mm (6X)12”, 300mm (6X)–– 142mm142mm22 (12 X)(12 X)–– 2.8 GHz (26K X)2.8 GHz (26K X)
•• ItaniumItanium®® 2 processor2 processor–– 2002 (31 yrs)2002 (31 yrs)–– 220M (96K X)220M (96K X)–– 0.18um (1/55 X)0.18um (1/55 X)–– 12”, 300mm (6X)12”, 300mm (6X)–– 421mm421mm22 (35 X)(35 X)–– 1 GHz (9K X)1 GHz (9K X)
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1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
1,000,000,000
1970 1980 1990 2000 2010
Tran
sist
ors
386
486
Pentium®
286
Pentium® II
Pentium® III Pentium® 4
8086
8080
8008
Moore’s Law ContinuesMoore’s Law Continues
•• Transistors per IC doubles every two yearsTransistors per IC doubles every two years•• In less than 30 yearsIn less than 30 years
–– 1,000X decrease in size1,000X decrease in size–– 10,000X increase in performance10,000X increase in performance–– 10,000,000X reduction in cost10,000,000X reduction in cost
•• Heading toward 1 billion transistors before end of this decadeHeading toward 1 billion transistors before end of this decade
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©2002©2002 Intel Corp.Intel Corp. Page Page 55Robert YungRobert Yung
In the Last 25 YearsIn the Last 25 YearsLife was EasyLife was Easy
•• Die sizes increase, allowed by Die sizes increase, allowed by –– Increasing wafer sizeIncreasing wafer size–– Process technology moving from “black art” Process technology moving from “black art”
to “manufacturing science”to “manufacturing science”•• Doubling of transistors every 18 monthsDoubling of transistors every 18 months•• And, only constrained by cost & mfg. limitsAnd, only constrained by cost & mfg. limits
What Are The Future Challenges?What Are The Future Challenges?What Are The Future Challenges?
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©2002©2002 Intel Corp.Intel Corp. Page Page 66Robert YungRobert Yung
10
100
1000
1971 1976 1981 1986 1991 1996 2001
Die
siz
e (m
m2 )
0.1
1
10
Feat
ure
size
(um
)
Feature, Die Size TrendFeature, Die Size Trend
•• 30% feature size reduction every 3 and now 2 yrs30% feature size reduction every 3 and now 2 yrs•• Before mid 1990’s, 7% die size increase/yr; lithography limitedBefore mid 1990’s, 7% die size increase/yr; lithography limited•• After that, die size growth will be limited by power dissipationAfter that, die size growth will be limited by power dissipation
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©2002©2002 Intel Corp.Intel Corp. Page Page 77Robert YungRobert Yung
Processor Frequency TrendProcessor Frequency Trend
•• Gates per clock reduces by 25% each generation; Gates per clock reduces by 25% each generation; leveling outleveling out•• Frequency doubles each generation enabled by advancedFrequency doubles each generation enabled by advanced
circuit and architectural techniquescircuit and architectural techniques
10
100
1000
10000
1987 1989 1991 1993 1995 1997 1999 2001 2003
Freq
uenc
y [M
Hz]
1
10
100
386486
Pentium®
Pentium Pro®
Pentium® II Pentium® III
Pentium® 4
# G
ates
per
clo
ck
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©2002©2002 Intel Corp.Intel Corp. Page Page 88Robert YungRobert Yung
Processor Power TrendProcessor Power Trend
•• Lead processor power increases every generation Lead processor power increases every generation —— power power constrainedconstrained•• VccVcc will scale by only 0.8 (not 0.7)will scale by only 0.8 (not 0.7)•• Active power will scale by ~0.9 (not 0.5)Active power will scale by ~0.9 (not 0.5)•• Active power density will increase by ~30Active power density will increase by ~30--80% (not constant)80% (not constant)•• Leakage power will make it worse as process shrinksLeakage power will make it worse as process shrinks
•• Process scaling provides higher performance at lower powerProcess scaling provides higher performance at lower power
0
10
20
30
40
50
60
70
80
500 1000 1500 2000 2500Frequency [MHz]
Pow
er [W
]Pentium® 40.18um
Pentium® 40.13um
Pentium® III0.13um
Pentium® III0.18um
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©2002©2002 Intel Corp.Intel Corp. Page Page 99Robert YungRobert Yung
Some ImplicationsSome Implications
•• Moore’s Law will continue beyond this decadeMoore’s Law will continue beyond this decade–– 2X transistors growth per technology generation2X transistors growth per technology generation
•• Die size increase will level outDie size increase will level out–– Constraint is power Constraint is power –– not manufacturabilitynot manufacturability
•• Frequency will continue to increaseFrequency will continue to increase–– Faster process, advanced microFaster process, advanced micro--architecturearchitecture–– Reduction of gates per clock will slow downReduction of gates per clock will slow down
•• What is the future look like?What is the future look like?–– Process technology trendProcess technology trend–– Microprocessor and platform architectural trendMicroprocessor and platform architectural trend
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©2002©2002 Intel Corp.Intel Corp. Page Page 1010Robert YungRobert Yung
AgendaAgenda
•• Process Driven TrendsProcess Driven Trends–– Moore’s LawMoore’s Law–– Transistors: Frequency, Power, Gate LengthTransistors: Frequency, Power, Gate Length–– Interconnection: WiresInterconnection: Wires–– Power DissipationPower Dissipation–– PackagingPackaging
•• Architecture Driven TrendsArchitecture Driven Trends–– Increased ParallelismIncreased Parallelism–– Cache And MemoryCache And Memory–– Input/OutputInput/Output
•• ConclusionConclusion
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©2002©2002 Intel Corp.Intel Corp. Page Page 1111Robert YungRobert Yung
Transistor Physical Gate Length Transistor Physical Gate Length
Source: Robert Chau, 12/2001Source: Robert Chau, 12/2001
30nm
0.18um0.13um
90nm65nm
45nm
0.25um0.35um
0.5um
15nm
130nm
0.2um
70nm
50nm
30nm20nm
0.01
0.1
1
1991 1993 1995 1997 1999 2001 2003 2005 2007 2009
Mic
ron
Technology NodeTechnology Node
Transistor Physical Transistor Physical Gate LengthGate Length
New Process Generation Every 2 Years New Process Generation Every 2 Years New Process Generation Every 2 Years
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©2002©2002 Intel Corp.Intel Corp. Page Page 1212Robert YungRobert Yung
Process Technology TrendsProcess Technology Trends
Intel: To the Terahertz TransistorIntel: To the Terahertz TransistorTransistor Leadership ContinuesTransistor Leadership Continues
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©2002©2002 Intel Corp.Intel Corp. Page Page 1313Robert YungRobert Yung
SRAM Cell Size ScalingSRAM Cell Size Scaling
•• SRAM cell size will continue to scale ~0.5x per generationSRAM cell size will continue to scale ~0.5x per generation•• Larger caches can be incorporated on dieLarger caches can be incorporated on die
44
21
10.65.6
2.1 1.005
101520253035404550
SRA
M C
ell S
ize
(um
2 )
0.5 0.35 0.25 0.18 0.13 0.09
Technology Generation (um)
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©2002©2002 Intel Corp.Intel Corp. Page Page 1414Robert YungRobert Yung
AgendaAgenda
•• Process Driven TrendsProcess Driven Trends–– Moore’s LawMoore’s Law–– Transistors: Frequency, Power, Gate LengthTransistors: Frequency, Power, Gate Length–– Interconnection: WiresInterconnection: Wires–– Power DissipationPower Dissipation–– PackagingPackaging
•• Architecture Driven TrendsArchitecture Driven Trends–– Increased ParallelismIncreased Parallelism–– Cache And MemoryCache And Memory–– Input/OutputInput/Output
•• ConclusionConclusion
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©2002©2002 Intel Corp.Intel Corp. Page Page 1515Robert YungRobert Yung
OnOn--chip Interconnect Trendchip Interconnect Trend
0.1
1
10
100250 180 130 90 65 45 32
Feature size (nm)Relativedelay
Gate delay (fanout 4)Local interconnect (M1,2)Global interconnect with repeatersGlobal interconnect without repeaters
•• Local interconnects scale with gate delayLocal interconnects scale with gate delay•• Intermediate interconnects benefit from low k materialIntermediate interconnects benefit from low k material•• Global interconnects do not scale because of RC!Global interconnects do not scale because of RC!
More metal layers may not helpMore metal layers may not help
Source: ITRS, 2001Source: ITRS, 2001
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©2002©2002 Intel Corp.Intel Corp. Page Page 1616Robert YungRobert Yung
Pipe Length vs. Frequency TrendPipe Length vs. Frequency Trend
•• As feature size reduces, longer pipeline enables higher frequencAs feature size reduces, longer pipeline enables higher frequencyy•• Performance benefits from higher frequency, advanced microPerformance benefits from higher frequency, advanced micro--
architectural techniques, larger cachesarchitectural techniques, larger caches
0
500
1000
1500
2000
2500
3000
100300500700900feature size (nm)
Frequency (Mhz)
0
500
1000
1500
2000
2500
3000re
lativ
e in
tege
r pe
rform
ance
5 stages: Pentium5 stages: Pentium®®
20 stages (OOO): Pentium20 stages (OOO): Pentium®® 44
10 stages (OOO): Pentium10 stages (OOO): Pentium®®IIIIII
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©2002©2002 Intel Corp.Intel Corp. Page Page 1717Robert YungRobert Yung
AgendaAgenda
•• Process Driven TrendsProcess Driven Trends–– Moore’s LawMoore’s Law–– Transistors: Frequency, Power, Gate LengthTransistors: Frequency, Power, Gate Length–– Interconnection: WiresInterconnection: Wires–– Power DissipationPower Dissipation–– PackagingPackaging
•• Architecture Driven TrendsArchitecture Driven Trends–– Increased ParallelismIncreased Parallelism–– Cache And MemoryCache And Memory–– Input/OutputInput/Output
•• ConclusionConclusion
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©2002©2002 Intel Corp.Intel Corp. Page Page 1818Robert YungRobert Yung
Power Density: Cache vs. LogicPower Density: Cache vs. Logic
•• As die temperature increases, CMOS logic slows downAs die temperature increases, CMOS logic slows down•• With low power density (past), can assume uniformityWith low power density (past), can assume uniformity•• With increasing power density and onWith increasing power density and on--die caches, need to die caches, need to
consider simplistic nonconsider simplistic non--uniformityuniformity
X1
X3
X5
X7
X9
X11
X13
X15
X17
X19
Y1
Y4
Y7
Y10
Y13
Y16Y19
0
10
20
30
40
50
60
X1
X3
X5
X7
X9
X11
X13
X15
X17
X19
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Y4
Y7
Y10
Y13
Y16Y19
0
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X1
X4
X7
X10
X13
X16
X19
Y1
Y4
Y7
Y10Y13
Y16Y19
0
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X1
X4
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X10
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X16
X19
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Y4
Y7
Y10Y13
Y16Y19
0
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60
Past: Thermal UniformityPast: Thermal Uniformity Present: Logic vs. CachePresent: Logic vs. Cache
Caches
Core logic
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©2002©2002 Intel Corp.Intel Corp. Page Page 1919Robert YungRobert Yung
Power Density: The FuturePower Density: The Future
•• With high power density, cannot assume uniformityWith high power density, cannot assume uniformity–– As die temperature increases, CMOS logic slows downAs die temperature increases, CMOS logic slows down–– At high die temp., longAt high die temp., long--term reliability can be compromisedterm reliability can be compromised
0
50
100
150
200
250
Hea
t Flu
x (W
/cm
2)
40
50
60
70
80
90
100
110
Tem
pera
ture
(C)
Power MapPower Map OnOn--Die TemperatureDie Temperature
Hot Spots RemainHot Spots Remain
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©2002©2002 Intel Corp.Intel Corp. Page Page 2020Robert YungRobert Yung
Power ManagementPower Management
•• Intel Intel SpeedstepSpeedstep®® Technology (Technology (GeyservilleGeyserville))–– VoltageVoltage--freq scaling with active thermal feedbackfreq scaling with active thermal feedback–– MultiMulti--operating states from high operating states from high perfperf. to deep sleep. to deep sleep
•• Throttling to reduce instruction rateThrottling to reduce instruction rate•• Power management reduces average and peak power dissipationPower management reduces average and peak power dissipation•• Trend: Static logic, clock gating, split power planes, active poTrend: Static logic, clock gating, split power planes, active power mgmt.wer mgmt.
FrequencyFrequency
Pow
erPo
wer
MinimumMinimumOperating Operating VoltageVoltage
Power Power αα VV33
Most efficient Most efficient operating pointoperating point
IncreasingIncreasingPerformancePerformance
Increasing EfficiencyIncreasing Efficiency(Freq/Power)(Freq/Power)
Max PerformanceMax Performance
Power scalingPower scalingrange ~ 3range ~ 3--44
Deep Sleep /Deep Sleep /Quick Start Quick Start
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©2002©2002 Intel Corp.Intel Corp. Page Page 2121Robert YungRobert Yung
AgendaAgenda
•• Process Driven TrendsProcess Driven Trends–– Moore’s LawMoore’s Law–– Transistors: Frequency, Power, Gate LengthTransistors: Frequency, Power, Gate Length–– Interconnection: WiresInterconnection: Wires–– Power DissipationPower Dissipation–– PackagingPackaging
•• Architecture Driven TrendsArchitecture Driven Trends–– Increased ParallelismIncreased Parallelism–– Cache And MemoryCache And Memory–– Input/OutputInput/Output
•• ConclusionConclusion
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©2002©2002 Intel Corp.Intel Corp. Page Page 2222Robert YungRobert Yung
Microprocessor Packaging
•• 1971 1971 –– 4004 Processor4004 Processor–– 1616--pin ceramic packagepin ceramic package–– wire bond attachwire bond attach–– 750Khz I/O750Khz I/O
•• 2002 2002 -- PentiumPentium®® 4 Processor4 Processor–– 478478--pin organic packagepin organic package–– flipflip--chip attachchip attach–– 133Mhz, quad133Mhz, quad--pumped I/Opumped I/O
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©2002©2002 Intel Corp.Intel Corp. Page Page 2323Robert YungRobert Yung
FCPGA vs. BBULFCPGA vs. BBUL
•• Package built around diePackage built around die shorter profileshorter profile smaller form factorsmaller form factor•• Results inResults in lower inductance, higher frequencylower inductance, higher frequency
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©2002©2002 Intel Corp.Intel Corp. Page Page 2424Robert YungRobert Yung
AgendaAgenda
•• Process Driven TrendsProcess Driven Trends–– Moore’s LawMoore’s Law–– Transistors: Frequency, Power, Gate LengthTransistors: Frequency, Power, Gate Length–– Interconnection: WiresInterconnection: Wires–– Power DissipationPower Dissipation–– PackagingPackaging
•• Architecture Driven TrendsArchitecture Driven Trends–– Increased ParallelismIncreased Parallelism–– Cache And MemoryCache And Memory–– Input/OutputInput/Output
•• ConclusionConclusion
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©2002©2002 Intel Corp.Intel Corp. Page Page 2525Robert YungRobert Yung
Apps Show Different Sensitivity To Bandwidth And CPU FrequencyApps Show Different Sensitivity To Bandwidth And CPU FrequencyApps Show Different Sensitivity To Bandwidth And CPU Frequency
CPU, Memory Sensitivity of AppsCPU, Memory Sensitivity of Apps
wupwisewupwise quake IIIquake III
apsiapsi
fma3dfma3d
bzip2bzip2
artart
equakeequake
mgridmgridmcfmcf
lucaslucas
appluapplu
swim
swim ammpammp
galgelgalgel
facerecfacerec
flask_mpegflask_mpegvolanovolano sony_mpeg2sony_mpeg2
parserparserV
ortexV
ortexvprvprsony_mpeg4sony_mpeg4
gccgcc
perlbmk
perlbmk
twolf
twolf
gapgapcraftycraftysixtrack
sixtrack
mesa
mesa
sony_mpeg1
sony_mpeg1
flaskflask
eoneon
media_encoder
media_encoder
Sensitivity to CPU GHzSensitivity to CPU GHz
Sens
itivi
ty to
DR
AM
Ban
dwid
thSe
nsiti
vity
to D
RA
M B
andw
idth
Multi Media AppsMulti Media AppsMulti Media Apps
EngineeringAnalysis AppsEngineeringEngineering
Analysis AppsAnalysis Apps
Productivity Apps
Productivity Productivity AppsApps
Memory Performance mattersMemory Performance matters
CPU, Memory mattersCPU, Memory matters
CPU performance mattersCPU performance matters
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©2002©2002 Intel Corp.Intel Corp. Page Page 2626Robert YungRobert Yung
ProcessorProcessor--DRAM Gap (latency)DRAM Gap (latency)
1
10
100
1000
10000
1980 1985 1990 1995 2000 2005
Rel
ativ
e Pe
rfor
man
ce
DRAMCPU
Processor-DRAM Gap Grows >40% YearProcessorProcessor--DRAM Gap Grows >40% YearDRAM Gap Grows >40% Year
DRAM growth ~7%/yr
Processor growth >50%/yr
Growing gap
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©2002©2002 Intel Corp.Intel Corp. Page Page 2727Robert YungRobert Yung
Bus Bandwidth TrendBus Bandwidth Trend
0
1000
2000
3000
4000
5000
386
486
Pent
ium
®
Pent
ium
®Pr
o
Pent
ium
® II
(.35u
)
Pent
ium
® II
(.25u
)
Pent
ium
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Memory And I/O Bandwidth Are Crucial For High Performance Memory And I/O Bandwidth Are Crucial For High Performance Memory And I/O Bandwidth Are Crucial For High Performance
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©2002©2002 Intel Corp.Intel Corp. Page Page 2828Robert YungRobert Yung
Cache Memory TrendCache Memory Trend
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10
386
486
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1
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L1 cache latencyL2 cache latencyL1 cache sizeL2 cache size
• Hierarchy of caches reduce widening CPU-memory gap
• Reduce average miss rates
• Reduce average memory access latency
•• Hierarchy of caches reduce widening CPUHierarchy of caches reduce widening CPU--memory gapmemory gap
•• Reduce average miss ratesReduce average miss rates
•• Reduce average memory access latencyReduce average memory access latency
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©2002©2002 Intel Corp.Intel Corp. Page Page 2929Robert YungRobert Yung
Itanium® 2 Processor
•• Transistors: 221MTransistors: 221M–– Caches, I/O: 3.3MB or ~170M (75%)Caches, I/O: 3.3MB or ~170M (75%)–– Core: ~51M (25%)Core: ~51M (25%)
•• Die size: 19.5 x 21.6mm = 421 mmDie size: 19.5 x 21.6mm = 421 mm22
–– Caches, I/O: L3C ~50%; others ~16%Caches, I/O: L3C ~50%; others ~16%–– Core: 142mmCore: 142mm22 (34%)(34%)
Caches becoming an increasing portion of the die because of its performance impact and low power density
Caches becoming an increasing portion of the die because Caches becoming an increasing portion of the die because of its performance impact and low power densityof its performance impact and low power density
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©2002©2002 Intel Corp.Intel Corp. Page Page 3030Robert YungRobert Yung
ConclusionConclusion•• Moore’s Law will continue beyond this decadeMoore’s Law will continue beyond this decade
–– 2X transistors growth per technology generation2X transistors growth per technology generation–– 30nm and smaller transistors realized30nm and smaller transistors realized
•• Die size increase will level outDie size increase will level out–– Constraint is power Constraint is power –– not manufacturabilitynot manufacturability–– Increasing cache sizes and multiIncreasing cache sizes and multi--cores on die enable cores on die enable
performance increase within power constraintperformance increase within power constraint
•• Towards 10Ghz microprocessor in this decadeTowards 10Ghz microprocessor in this decade–– Faster processFaster process–– Advanced architectural and circuit techniquesAdvanced architectural and circuit techniques
•• ProcessorProcessor--Memory gap continues to growMemory gap continues to grow–– Larger caches help reduce impactLarger caches help reduce impact–– Innovative processorInnovative processor--cache memory design crucial to cache memory design crucial to
continual performance scalingcontinual performance scaling
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Page Page 3131Robert YungRobert Yung
®®