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Fundamentals of HDL Design

Prelims.indd 1Prelims.indd 1 2/10/2009 7:42:53 PM2/10/2009 7:42:53 PM

Fundamentals of HDL Design

Cyril Prasanna RajAssistant Professor & Course Manager

(VLSI System Design Center)MS Ramaiah Institute of Advance Studies,

Bangalore - 560 54.

Sanguine Technical PublishersBangalore - 560016

2009


Price:Rs. 340.00US$ 24.99

9 7 8 8 1 8 8 8 4 9 4 3 X

ISBN 978 81 88849 43 X

Title: Fundamentals of HDL DesignCyril Prasanna Raj

This book contains information obtained from authentic and highly regarded sources. Reprinted material is quoted with permission, and sources are indicated. Reasonable efforts have been made to publish reliable data and information, but the author and the publisher cannot assume responsibility for the validity of all materials or for the consequences of their use.

Neither this book nor any part may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying, microfi lming and recording, or by any information storage or retrieval system, without prior remission in writing from the publishers.

The consent of SANGUINE TECHNICAL PUBLISHERS does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specifi c permission must be obtained in writing from SANGUINE for such copying.

The export rights of this book are vested solely with the publisher.

Direct inquiries: E-mail: [email protected], or Postal address: #361/A, 4th Main, Banasawadi Main Road, Ramamurthy Nagar, Bangalore – 560 016, India.

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© 2009 by Sanguine Technical Publishers, Bangalore – 560 016.

Published by Lal M Prasad for SANGUINEProduction Editor: R.SubramanianTypeset in Times New Roman by Sigma Publishing Services, Chennai – 600 033.Printed in India at Viralam Graphics, Bangalore – 560 018.


Dedicated to my wife, mother and my children


Acknowledgments

The author would like to express his gratitude to Dr. S.R. Shankapal, Director, M.S Ramaiah School of Advanced Studies for providing an opportunity to work in the filed of VLSI System Design. His constant support, encouragement and valuable guidance during every stage and every day of my stay at MSRSAS has not only encouraged me but also has provided me a new experience and platform to take up new challenges in the field of VLSI design. This has motivated me to Endeavour into writing this books.

My sincere thanks and acknowledgments to Mr. Lal M Prasad, CEO, Sanguine Technical Publishers and his team members. I take opportunity to express my deepest gratitude and heartfelt wishes to Mr. Lal; it was only his perseverance and encouragement that was instrumental to author this book.

I would like to thank the many individuals who have contributed their time and effort to the development of this book. My experience at MSRSAS is purely a blend of my association with my students, their valuable contribution and suggestions in every HDL class of mine was a learning experience.

I would like to thank the faculty members who reviewed and contributed in completing this book. I specially would like to thank the faculty members at MSRSAS for their cooperation and support extended particularly

1. Mr. Selva Kumar 2. Mr. Padmanabhan 3. Mr. Vasudeva murthy

I express my gratitude to Mr. Suresh, Mr. Subramanian and their team for supporting me for the last two years in getting this book done from my side. And thank Sigma Publishing Service for their wonderful work done to bring out this book in its present form.

I also express my deepest gratitude to my HOD, Dr. Govind Kadambi for his valuable support and timely guidance. My sincere thanks to all my students and faculty members at MSRSAS, for their support and timely help.

Cyril Prasanna Raj P


Preface

In order to achieve sophistication in our livelihood, electronic equipments for industrial, commercial, consumer, medical and defense applications are increasingly becoming complex, smaller in size and operate on low power. In today’s highly aggressive digital electronics industry, equipment vendors must create products that provide greater speed and functionality using less money, power, and physical area. Demand for newer technologies with additional features supporting flexibility and adaptability to constant change, driven by time to market of new products engineers need to operate with caution and ease the complexity in design and testing. Hardware description languages(HDL) have been widely adapted by digital engineers to design, model and validate complex systems. HDL models for complex systems reduces the design, verification time and also helps in debugging designs at the initial stage. Designs modeled at higher level language such as HDL can be easily converted to its equivalent gate level with the help of power synthesis tools. This process called as synthesis carried out automatically using sophisticated tools further reduces the design time and also reduces the complexity in designing complex gate level schematics manually.

The gate level schematics automatically generated with the aid of commercial synthesis tools also optimize the design for number of gates, power and speed. This is one of the greatest advantages of the software tools available, these tools are also very powerful in verification of functionality of the complex designs modeled, and helps in debugging the design. There is a need for writing HDL’s efficiently, in a systematic manner to exploit the features of these tools. With the maturity and multiple programming options available of HDL’s using them to design complex digital hardware has become the mainstream practice. Knowledge of C programming language helps in better understanding and learning of HDL, however HDL being almost similar to C, there is always a misconception among beginners learning HDL. We need to be aware that HDL is used for modeling design that get converted to gate level schematic, at the same time HDLs are also widely used for verifying the functionality of the design in other words helps in debugging the design at the gate level.

This book provides in-dept coverage on the introduction of HDL languages like VHDL and Verilog for beginners. The book covers both basic principles of programming skills for HDL and design and modeling of advanced digital systems using HDL. The modeling of digital systems at gate level, algorithmic level and at architecture level is emphasized with basic examples. Knowledge of basic examples enables to understand the concept of HDLs, which further aids in understanding other benefits of HDL like design of complex systems efficiently, verifying designs using test benches. Mixed level modeling, hierarchical design modeling and Finite State Machine Modeling are discussed with examples. The emphasis of the book is on learning the art of writing


efficient HDLs by using proper syntaxes and appropriate statements supported and recommended by HDL users and tools respectively.

Students doing their first level of HDL course would find this book more useful, as the focus in this book is not in teaching the syntaxes available, but assist them to use the available syntaxes in modeling complex digital systems efficiently. Multiple case studies and examples have been introduced and discussed to help the student in understanding the concepts to its breadth.

Scope:The book focuses primarily on assisting the reader in understanding the basic concepts of VHDL and Verilog language. Multiple examples and case studies are being used for better understanding of the language syntax. The examples incorporated are self explanatory if the syntaxes and digital concepts are known to the reader. This book is recommended for a reader doing his first level of course in HDL. The topics covered and examples discussed help in doing the advanced course in digital design. Exclusive session on synthesis, test benches and mixes level coding is incorporated.

Unique features:This book is a hardware design and modeling text. Several unique features distinguish the book:

• Explains HDL basics with simple design examples • Design examples modeled in both Verilog and VHDL clearly helps the reader to

differentiate the HDL syntaxes and its merits • Design examples modeling carried out using multiple coding styles helps reader to adopt

and appreciate the efficiency of HDL • Use of toplevel models and conceptual diagrams, helps the reader in understanding the

examples in better way • Details on coding guidelines explained with examples • Test benches for every design model explained gives better understanding and need for

testing and verification • Contains large number of design examples modeled in Verilog and VHDL • Large number of examples included at the end of every chapter • Standard exercises at end of every chapter • Topics on learning VHDL and Verilog in One Day in the appendix section • Discussion on simulating the HDL codes and verifying them using Modelsim simulator

Book Organization:The book has seven chapters, systematically organized, beginners are recommended to read from chapter one onwards. A sincere recommendation from the author is that reading the preface and the appendix gives better understanding of HDL at a first glance. Examples discussed in every chapter gives better understanding of the topics covered. Solving exercises provided in every chapter can builds readers confidence level. More detailed descriptions of the chapters are as follows:


IntroductionThis gives a clear understanding of need for HDL, history of HDL and a brief of industry practices on HDL.

Chapter 1 Introduces to VHDL and Verilog with basic examples, language constructs, simple syntaxes, literals, basic operators and interfaces. Simulation of HDL using Modelsim is also discussed.

Chapter 2This chapter introduces to data flow descriptions of digital systems using VHDL and Verilog languages. Multiple examples gives a detailed understanding of data flow concepts supported by HDL.

Chapter 3Chapter 3 describes the behavioral modeling or sequential modeling constructs supported by HDL. Modeling combinational and sequential blocks using behavioural modeling is discussed for the same set of examples considered in Chapter 2.

Chapter 4This chapter discusses the structural modeling constructs adopted in HDL. The examples discussed in chapter 2 and chapter 3 are used as simple building blocks and are interconnected to build complex systems, the syntaxes and techniques supported for top level modeling is explained in this chapter with multiple examples.

Chapter 5In order to ease the complexity in design modeling, complex design are divided into hierarchical subblocks and are modeled as functions, procedures that are reusable for any designs, these topics are discussed with examples in this chapter.

Chapter 6Mixed level modeling and test benches are discussed with examples in this chapter. Testbenches for examples discussed in earlier chapters are modeled in this chapter. Number of examples at the end of the chapter gives a detailed and clear understanding of mixed level modeling and Testbenches.

Chapter 7Synthesis issues and efficient coding guidelines for synthesis is discussed in this chapter. Simplistic examples are explained in detail, this enables to understand the major issues to be considered in modeling HDLs for synthesis.

Worked out examples at the end gives better understanding of HDL language, examples covered almost covers important digital examples available and discussed in every textbook on HDL.

Appendix chapter gives a quick reference of all syntaxes available for HDL, it also discusses on syntaxes that are important and used predominantly in the industry. Summary of syntaxes is also included at the end. Learning VHDL and Verilog in one day is the key highlight of this book, which is included at the end.


Audience:The intended audience for this book is students, faculty members and practicing engineers who wish to learn HDL from basics. As the focus is on use of examples to assist the reader to understand the concepts of HDL, the reader should not look out for detailed explanation of HDL syntaxes. Readers should have basic knowledge of any programming language like C and should be aware digital design concepts. No prior experience or knowledge in HDL is needed.

Most of the theory and programming examples discussed in this book are based on the knowledge and experience of the author. The information provided in this book is also an extract of discussion provided in the following:


Key Features

This book intends to meet the requirements of basic course in HDL modeling, this discussions presented in this book targets audience doing their first level course in HDL design. Emphasis on use of multiple examples to explain the concepts of HDL coding in Verilog and VHDL is the main advantage of this book. Readers with no prior knowledge of HDL language, with basic knowledge in digital design and programming skill may appreciate the contents and the concepts discussed in this book. The topics presented and explained using examples are taken from most commonly used digital designs taught in every course curriculum on digital design. Most of the examples are based on sub blocks required to model complex digital designs that are adopted by most of the practicing engineers.

Worked out examples at the end of every chapter, exercises problems and discussions presented in the appendix would be more useful to a reader to learn, remember and appreciate the advantages of HDLs for design and modeling.

Solution manual for the exercise problems can be downloaded from publisher’s web link.


Contents

Introduction Introduction to HDL 2 History of HDLs 3 Verilog 4 VHDL 4

VHDL 1.1 What Is VHDL? 7 1.2 The Requirement 8 1.3 Asic Mandate 8 1.4 VHDL’93 8 1.5 Levels of Abstraction 9 1.6 Scope of VHDL 10 1.7 Design Process 11 1.8 System-level Verifi cation 12 1.9 Benefi ts of using VHDL 13 1.10 Executable Specifi cation 13 1.11 Language-features-Terminologies 14 1.12 Entity and Architecture 15 1.13 Architectural Styles 18 1.14 Literals 21 1.15 Types 24 1.16 Enumeration Types 26 1.17 The Verilog Hardware Description Language 30 1.18 Modules 32 1.19 Gate Types 34 1.20 Lexicography 35 1.21 Connection Rules 41 1. 22 Writing to Standard Output 49 1.23 VHDL Examples of Basic Logic Gates 50 1.24 Use of Model Sim to Simulate A Vhdl Code 58 1.25 Comparison of VHDL and Verilog 74


Data Flow Descriptions 2.1 Section 1-A First Example 89 2.2 How it Works 90 2.3 The Delay Model 92 2.4 Other Types 93 2.5 Other Operators 95 2.6 Operators 96 2.7 Attributes 99 2.8 User-defi ned Attributes 99 2.9 Usage of Attributes 100 2.10 Blocks 101 2.11 Data fl ow Modeling 102 2.12 Delays 104 2.13 Expressions, Operators, and Operands 105 2.14 Operator Types 106 2.15 Examples 113 2.16 Modeling Combinational Logic in Verilog 120

Sequential Modeling 3.1 Sequential Statements 131 3.2 The Process Statement 131 3.3 Assignment 134 3.4 Signal Assignments in Process 139 3.5 Processes with Sensitivity Lists 140 3.6 Using Processes for Combinational Logic 141 3.7 Using Processes for Registered Logic 143 3.8 If-Then-Else Statements 146 3.9 Case Statements 147 3.10 Loops 147 3.11 While Loop 150 3.12 Behavioral Modeling — Verilog 152 3.13 Procedural Assignments 154 3.14 Procedural Continuous Assignments 158 3.15 Branch Statements 161 3.16 The Case Statement 162 3.17 Looping Constructs 163 3.18 Block Statements 166 3.19 Block Types 168 3.20 Special Features of Blocks 170 3.21 Examples 172 3.22 Start and Finish Times 177 3.23 Timing Control 178 3.24 Worked Example 181


Structual Descriptions 4.1 Introduction 183 4.2 Generation of Instances 184 4.3 Use of Packages 186 4.4 Confi gurations 186 4.5 Generics 191 4.6 Packages and Libraries 193 4.7 Structural modeling in Verilog 196 4.8 Verilog examples for Structural modeling 200 4.9 Rise, Fall and Turn-off Delays 206 4.10 Delay Example 208 4.11 Technology Independent Coding Styles 215

Functions and Procedures 5.1 Functions 239 5.2 Operators as Functions 240 5.3 Subprogram Overloading 241 5.4 Procedures 242 5.5 Parameter Types 243 5.6 Mapping of Parameters 244 5.7 Summary 244 5.8 Procedure 245 5.9 Tasks and Functions 246 5.10 Task Examples 248 5.11 Functions 250 5.12 Tasks and Task Enabling 253 5.13 Task Memory Usage and Concurrent Activation 256 5.14 Defi ning a Function 256 5.15 State Machines 259 5.16 The State Machine consists of Three Parts 261

Test Benches and Mixed Signal Descriptions 6.1 Mixed Level Descriptions 271 6.2 Invoke a VHDL entity from a Verilog Module 271 6.3 Invoking a Verilog Module from a VHDL Module 282 6.4 Test benches 285 6.5 Worked Example 305

Synthesis 7.1 VHDL 357 7.2 Synthesis 357 7.3 Latch vs Flip-fl op 357


7.4 Mapping Statements to Gates 358 7.5 VHDL Style Guidelines 367 7.6 Verilog Synthesis Methodology 371 7.7 Synthesizeable Templates 371 7.8 Coding Guidelines 381 7.9 State Machine Guidelines 382 7.10 Input-Output Buffers 393

Appendix 401

B-1 Verilog Language 505 B-2 506 B-3 Additional Requirements 514 B-4 What’s New in Verilog 2001 519 B-4.2 Verilog in One Day 527 B-5 Abbreviations 537 B-6 Common Errors Encountered 538 B-7 VHDL Syntax with Examples 538 B-7.1 VHDL Constructs 538 B-8 Vhdl in On Day 543

Bibliography 553

Index 555


In order to achieve sophistication in our livelihood, electronic equipments for industrial, commercial, consumer, medical and defense applications are increasingly becoming complex, smaller in size and operate on low power. In today’s highly aggressive digital electronics industry, equipment vendors must create products that provide greater speed and functionality using less money, power, and physical area. Creating or designing a new electronic product is undertaken by multiple groups working in parallel. For example for designing a mobile phone, identifying the marketing and business aspects even before it could be designed is a major task, identifying the shape, size, features, aesthetic view, color combination of the mobile phone is another major challenge. Design and verification of power sources, i.e identifying the type of batteries, battery requirements, power planning is also a one more major task. PCB design and analysis of the mobile system that mounts power supply unit, LCD panels, battery, keypad interface, special function keys, microphone, speakers, camera, antenna, receivers, transmitters and the integrated chip is a major task involved in product design. The IC of mobhile phone consisting of analog and digital processing system needs to be designed and analyzed for its functionality, before it could be physically realized.

The major work involved in accomplishing the task of designing an electronic product should be automated this needs the role of computers executing software programs for design and verification of various building block. Use of software’s for modeling and verification of designs drastically reduces the design time as it reduces the human error, as well as it executes complex software routines with multiple iterations in a shorter time. The designer has to just monitor the results provided by the software and verify them.

The design and analysis of digital system of a mobile phone IC amounts to 40 % of the entire work involved. The digital logic requires millions of transistors to realize the same. In terms of gate complexity it involve few million gates like basic gates, functions like counters, shifters, multiplexers, adders, subtractors, multipliers, memories, control unit, timers and many more. These building blocks need to be arranged in appropriate order to meet the desired functionality and hence they need to be verified. Designing the system arranging the digital blocks and interfacing them together requires more time and experience; this is called as bottom up approach. Instead, if the system is designed using top down approach, the complexity in designing and verifying the system reduces. In top down approach, in order to meet the specifications, or in other words to

Introduction

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2 Fundamentals of HDL Design

generate the output from the inputs available based on the specifications, algorithms expressing the relation between input and output is identified and expressed in high level languages or programming languages.

These algorithms expressed in high level languages for modeling the algorithms are verified using computers that execute the programs. The results obtained are analyzed and if they are meeting the desired specifications, there is a need to convert these software routines to digital blocks for hardware realization. This process is called as synthesis. Programming languages like C, C ++ etc. are predominantly used for these purpose, as these languages support high level description of algorithms, however there are no compilers available to convert these programs into efficient digital logic blocks, as well as the syntaxes available in these languages are not so flexible for designing digital logic and verifying them, hence there was a need for a language that can be dedicatedly used for modeling and verifying digital logic.

Design methodologies and design automation tools play a vital role in addressing the challenges faced by engineers as they attempt to create more complex designs in shorter span of time. The use of high level hardware description languages (HDLs), such as Verilog HDL, and VHDL along with powerful synthesis software is a key ingredient in the success of these methodologies, for these tools allow engineers to specify designs that can be quickly compiled, synthesized, and simulated before ever being physically put on a chip. Furthermore, HDLs provide a higher level of abstraction, freeing designers from tedious implementation details and permitting them to focus their time and energy on the functionality of their designs. Using Verilog or VHDL to describe a design, several iterations can be made to correct mistakes and redesign circuits without severe penalties.

This book exposes the student to modeling of digital systems. Explore the use of Verilog HDL and VHDL.

Learning HDL is very easy process, before we could learn HDL we need to be well versed with two things. First, we should have sound knowledge in digital design, secondly basics of programming language like C should be known. A very important point to remember most is HDL should not be treated as learning C programming, C Programme is very good for computation, and HDL is only for modeling digital systems.

The designers of HDL wanted a language with syntax similar to the C programming language so that it would be familiar to engineers and readily accepted. Hence HDL language syntaxes were developed in the similar lines. However, over the years HDL engineers get misguided with this syntax and start learning the language like C. In this book this very important issue is addressed. This book is prepared for students, staff members, working professionals, those who would like to learn HDL faster and master the same with its features for modeling and verifying digital systems.

INTRODUCTION TO HDLIn electronics, a hardware description language or HDL is any language from a class of computer languages for formal description of electronic circuits. It can describe the circuit’s operation, its design and organization, and tests to verify its operation by means of simulation.

Introduction.indd 2Introduction.indd 2 2/10/2009 4:39:07 PM2/10/2009 4:39:07 PM

Fundamentals Of HDL Design

Publisher : Sanguine Publishers ISBN : 9788131732472 Author : Cyril Prasanna Raj

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