fundamental issues of power...

Fundamental Issues of

Power Integrity

Textbook, Sec. 1.1 ~ 1.3

1

R. B. Wu

Outline

Challenges of System Integration

Technology Scaling in Transistors

Functioning of Transistors

Power Delivery Network

Power Supply Noise

Target Impedance

Outline

2

Challenges of

System Integration

3

R. B. Wu

0

0.5

1

1.5

2

2.5

3

3.5

4

1999 2000 2001 2002 2003 2004 2005

GH

z

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Vo

lts

Clock Frequency Bus Frequency Supply Voltage

(data from International Technology Roadmap for Semiconductors - http://public.itrs.net) 4

System Faster but Lower Margin

R. B. Wu

Structure More Complicated

5

Transistors

Moore’s Law

http://www.embedded.com/design/programming-languages-and-tools/4375996/Using-Java-for-multicore-programming-complexity--Part-1

R. B. Wu

Multi-Core CPU

6

R. B. Wu

Wire Problem? D

ela

y (

ps)

R. Ho, K. W. Mai, & M. A. Horowitz,

“The future of wires,” IEEE

Proc., vol. 89, pp. 490-503,

April 2001.

D. Sylvester et al., “Getting to the

bottom of deep submicron,”

Proc. ICCAD, pp. 203-211, Nov.

1998.

L. Cooke, “Signal integrity effects

in system-on-ship designs – a

designer’s perspective,” in R.

Singh Ed., Signal Integrity

Effects in Custom IC and ASIC

Designs, IEEE Press, 2002

Gate & wire scaling, 1997 NTRS

2

Al 3.0

Cu 1.7

SiO 4.0

Low 2.0

Al & Cu .8 Thick

43 Long

cm

cm

7

R. B. Wu

Market Impacts on Package

8

R. B. Wu

RF Die

Digital Processor Die

Memory Die

Sensor Die

Beyond Moore’s Law

Digital/RF/Memory

Package Integration

New Technologies

System in Package (SiP) and

System on Package (SoP)

Ultra-min. Mobile Computing Platform

9

R. B. Wu

RF Die

Digital Processor

Die

Excitation of Edge

Radiation

GND

PWR

Memory

Die Sensor

Die Decoupling

Capacitor

Wire Bond

Signal Line

SSN

Generation SSN Coupling to Signal/Clock Via

SSN Coupling to Power/Ground Via

P/G Via

Signal

Via

• Signal Integrity

• Power Integrity

• Electromagnetic Radiation

• Cross Talk

• Interconnect Coupling

• Substrate Coupling

• Clock Jitter/Skew

• Eye Patterns

• Process Variations

• Yield and Diagnosis

• Mixed Signal Challenges

System Integration Challenges

10

R. B. Wu

Key Trends in High-Speed Electronics

Year Feature

(nm)

Power

(W)

Vdd

(V)

Current

(A)

Chip Freq

(GHz)

Target Z

(m)

1997 250 70 2.5 28 0.75 4.5

1999 180 90 1.8 50 1.25 1.8

2001 150 110 1.5 73 1.5 1.0

2003 130 130 1.5 87 2.1 0.9

2006 100 70 160 180 1.2 1.1 133 164 3.5 3.9 0.45 0.34

2009 70 50 170 200 0.9 1.0 189 200 6.0 7.6 0.23 0.25

2012 50 36 175 200 0.6 0.9 292 222 10.0 14.9 0.10 0.20

2015 25 200 0.8 250 29.1 0.16

2018 18 200 0.7 286 56.8 0.12

2020 14 200 0.7 286 88.8 0.12

Signal & power integrity is crucial to the success of future

high-speed Electronics!

ITRS – High Performance 1997/2005

11

R. B. Wu

Simple Calculation

• Z0_tx-line ~ 50 ohm

• v_tx-line ~ 2 * 1010 cm/sec

• L_tx-line = Z0/v ~ 2.5 nH/cm

• PCB length ~ 10 cm

• f_max ~ 3 GHz

• L ~ 2*3.14* (3 G) * (2.5*10 nH) ~ 500 ohm

• How to reduce it to < 1 mohm?

12

Technology Scaling

in Transistors

13

R. B. Wu

Goal: 1 TIPS by 2010

0.01

0.1

1

10

100

1000

10000

100000

1000000

1970 1980 1990 2000 2010

MIP

S

Pentium® Pro Architecture

Pentium® 4 Architecture

Pentium® Architecture

486 386

286 8086

How do you get there? Courtesy: S. Borkar, Intel 14

R. B. Wu

GATE

SOURCE

BODY

DRAIN

Xj

Tox D

GATE

SOURCE DRAIN

Leff

BODY

Dimensions scale down by 30%

Doubles transistor density

Oxide thickness scales down

Faster transistor, higher performance

Vdd & Vt scaling Lower active power

Technology has scaled well, will it in the future? Courtesy: S. Borkar, Intel

CMOS Technology Scaling

15

R. B. Wu

0%

10%

20%

30%

40%

50%

1.5 1 0.7 0.5 0.35 0.25 0.18 0.13 0.09 0.07 0.05

Technology ()

Leakag

e P

ow

er

(% o

f T

ota

l)

Must stop

at 50%

Leakage power limits Vt scaling

A. Grove, IEDM 2002

Courtesy: S. Borkar, Intel

Leakage Power

• Junction leakage

• gate-induced drain leakage

• Subthreshold channel currents

• Gate-insulator tunnel currents

D. J. Frank, Power-constrained CMOS scaling limits,” IBM J. R&D, pp. 235-244, 2000.

16

R. B. Wu

1

1.5

2

2.5

3

3.5

1 2 3 4

Die Area, PowerR

ela

tiv

e P

erf

orm

an

ce

Multi Core

Single Core

C1 C2

C3 C4

Cache

• Multi-core, each core Multi-threaded

• Shared cache and front side bus

• Each core has different Vdd & Freq

• Core hopping to spread hot spots

• Lower junction temperature Courtesy: S. Borkar, Intel

Chip Multi-Processing

17

R. B. Wu

1 TeraByte/s

Power/Freq./BW Tradeoff for Multi-core Processors

18

R. B. Wu

Single core processor (45nm)

Multi-core processor (45nm)

Vdd 1.0V 1.0V

I/O pins (total) 1280 (ITRS) 3000 (Estimated)

Operating frequency 7.8GHz 4GHz

Chip-package data rate 7.8 Gb/s 4Gb/s

Bandwidth 125GByte/s 1 TeraByte/s

Power 429.78W 107.39W

Total # of pins on chip 3840 9000 (Est.)

# of pins on package 2480 4500 (Est.)

Comparison btw Single c& Multi-core for 45nm Node

19

Functioning of Transistors

20

R. B. Wu

FN_W

FN_L

FN

_H

2*FN_W

2*FN_W

1.2

*FN

_H

2.4

*FN

_H

Source/Drain

GateDrain/Source

Oxide

OX_T

FN_W

0.5*FN_W

Fin

Transistor from 2D to 3D

NMOS電晶體立體截面圖

https://zh.wikipedia.org/wiki/

鰭狀電晶體結構

R. B. Wu

Layout of CMOS Inverter

http://www.vlsi-expert.com/2014_11_01_archive.html

R. B. Wu

Two Types of Transistors

23

R. B. Wu

Basic CMOS Output Buffer

※ CMOS output buffer is very common in digital designs. It is

chosen to demonstrate basic principles of buffer modeling.

G.H. Shiue

Basic CMOS Output Buffer

24

R. B. Wu

])(2[ 2dsdstgsd vvVvKi

)1()( 2

dstgsd vVvKi

Triode region：

Saturation region：

2

ox

ox

WK

t L

2)(1

tgs

ds

d

out

VvKv

i

Z

0typical highveryZout __

CMOS Basic Operation CMOS Basic Operation

2

0

: device mobility (m /V-s)

: oxide permittivity (=3.97 )

: oxide thickness (~5.7 m)

: device width

: gate length

ox

oxt

W

L

25

R. B. Wu

Vi = Low to High

Vi = High to Low

CMOS Receiver - Operation

26

R. B. Wu

The Operation of the Basic CMOS Buffer

Pull-

down

Impedance

= inverse of

slope along

I-V curve.

Vi = Low to High

Vi

Vo

Pull-down Operation

27

R. B. Wu

Pull-up

Impedance =

inverse of slope

along I-V curve

w.r.t. O point

Vi = High to Low

Vi

Vo

Pull-up Operation

28

R. B. Wu

Capacitance

Load

Effects of Capacitive Load

29


30

R. B. Wu

Functioning of PDN

D: output node

Ron: on resistance

• Driver is used to charge

& discharge Rx input

capacitance . How

quickly it will be?

• PDN provides the

framework to supply

transistors sufficient

voltage & current to

switch states.

31 (upper) Driver (inverter) connected to a receiver (inverter)

(bottom) Input capacitance of receiver being charged to Vdd

R. B. Wu

Problems with Power Delivery?

• R&L of wire cause DC drop & time-domain voltage fluctuation, called power supply noise, delta I noise, or Simultaneous switching noise (SSN).

– Decrease in V -> slowdown IC

– Increase in V -> reliability concern.

– Leakage to quiet transistor -> incorrect switching along with crosstalk.

– Degraded waveform -> timing margin error

32

R. B. Wu

33

port1

port3

port2

port4

DQ13

Power trace

A Sample PDN for DDR3

Controller

DDR-1

DDR-2 3.3V->1.5V

VRM

GND (TOP)

GND (Bot.)

Top layer Bottom layer

Power traces

Darwin_TFBGA448_DEMO_S4B_L1B_2L

R. B. Wu

0 1 2 3 4 50.5

1

1.5

2

2.5

VP

Volt

age

(V)

time (ns)

PI-SI cosim

no coupling

Transient Simulation (pull-down)

34

No decap.

Max. voltage diff. is 27mV.

Small ripple is caused by VP .

If p-p diff. of VP is larger,

ripple becomes larger.

Driver

0-1.5V

Ron=36Ω

tr=125ps

Vdd=1.5V

RL=70Ω

CPW couple line

C=1.23pF

Power trace

DQ13

0 1 2 3 4 5-0.2

0

0.2

0.4

0.6

0.8

1

1.2

VP

Volt

age

(V)

time (ns)

PI-SI cosim

no coupling

1 1.5 2 2.5 3-0.04

-0.02

0

0.02

0.04

Pull-down

Volt

age

(V)

time (ns)

pi-si cosim

no coupling27mV

VP

VL

1.8V 1.7ns

LV

R. B. Wu

It might Cause Closed Eye

35

Logic 1 becomes very small when

VP is small. Driver

0-1.5V

Ron=36Ω

tr=125ps

Vdd=1.5V

RL=70Ω

CPW couple line

C=1.23pF

Power trace

DQ13

VP

VL

0 1 2 3 4 50

0.5

1

1.5

VL

Vo

ltag

e (V

)

time (ns)

y101-y100

y001

0 1 2 3 4 50

0.5

1

1.5

2

2.5

VP of y101

Volt

age

(V)

time (ns)

R. B. Wu

RL

PTL_Ctrl Pwr_CTRL

VSSQ

CTRL_NTL_DQN

Data_OUTN

Data_IN_N

VsupZsig

ZCTRL

RL

CTRL_1TL_DQ1 Data_

OUT1Data_IN_1 Zsig

Rs

Ron

It might Cause Detrimental Voltage

36

32 DQ lines.

No coupling: no DQ line

coupled with power trace.

PI-SI cosim: only one DQ line

coupled with power trace.

VP VL

_ sup ( )

on LCTRL

Pwr CTRLon L

R RZ

N NV VR R

N N

0 1 2 3 4 5-40

-20

0

20

40

VP

Vo

ltag

e (V

)

time (ns)

PI-SI cosim

no coupling

0 1 2 3 4 5-1.5

-1

-0.5

0

0.5

1

VP

Vo

ltag

e (V

)

time (ns)

PI-SI cosim

no coupling

LV

R. B. Wu

Reliability Wall

50MHz

Increase

In FMAX

+/- 100mV

+/- 50mV

1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80

825

785

745

705

665

625

FMAX (MHz)

VCC (V) Courtesy: Intel

Importance of Power Delivery

37

R. B. Wu

High-f Caps

Mid-f Caps

Motherboard

VRM


. VRM

. Interconnects

. DeCap’s on PCB & package 38

R. B. Wu

Noise Signature

A. Muhtaroglu, G. Taylor, and T. Rahal-Arabi, “On-die droop detector for analog sensing

of power supply noise,” IEEE J-SSC, pp. 651–660, Apr. 2004, © 2004 IEEE.

Noise Signature

39

Power Supply Noise

40

R. B. Wu

Signal Wires

Active Device (IC)

Core Circuits

(Comm. within IC) I/O Circuits

(Comm. outside IC)

Core and I/O Circuits

Current

Vdd

Gnd

Core and I/O Circuits

Core: transistors within

an IC and communicate with each other.

I/O: need communicate with other ICs though package

and motherboard. 41

R. B. Wu

42

Vo

0R

Linear Behavior Model -1

R. B. Wu

Linear-Linear Model -2

Better if run in freq domain rather than time domain

model

interpretation

43

R. B. Wu

Core Circuits Switching

(1 )( )

( )( 1 )

(1 )

( )

r

r

t s

dd rL

t s

dd r

V e t LV s

s R L s RC

V e t L

s s R L

44

PMOS

R. B. Wu

( ) ( )( ) ( ) ( )

0( ) ( ) (1 ) ( )

L

ddr

r dd dd r

r r

dd r

di t di tV t L L Ri t v t

dt dt

V tt t t t

tV t V u t V u t tt t

V t t

45

2

2

1

,max

1( ) ( ) (1 )

1 1( ) (1 )

( ) (1 ) ( ) Shift of

( )( ) ; ( ) (1 )

r

r

r

stdd

r

stdd

r

Rt

dd Lr

r

Rt

dd LL L L r

r

VL sI s RI s e

t s

VI s e

t s sL R

V Li t t e u t t

R t R

di t VV t L V V t L e

dt R t

L

L

Voltage Drop due to SSN

R. B. Wu

I/O Circuits Switching

max. voltage drop:

or

)1(max

ro t

L

Z

ro

ddL e

tZ

VLvV

0

; if ddr

o r

V Lv L t

Z t Z

46

R. B. Wu

Delay Due to SSN

• Voltage at input end of tx-line

2 2

2

(1.12) 1

(1.13) 1

1( ) ( )

1

o

o or

o

Zt

dd dd Lchip r

r r o

Z Zt t

dd L Lchip dd r

r o

Zt

dd L

r o o o

ddr

r o o

V t L VV e t t

t t Z

L VV V e e t t

t Z

V L LI t t e u t

t Z Z Z

V Lt t

t Z Z

2

or

Zt t

Lr

o

Le u t t

Z

47

R. B. Wu

CORE CIRCUITS I/O CIRCUITS

Transient current through inductors causes voltage fluctuations across Vdd

and Gnd terminals of the circuit

dt

dILV

Power Supply Noise

48

R. B. Wu

Jitter caused by SSN for I/O

Uncertainty in Delay due to SSN causing Jitter

Varying voltage

droop on power

supply due

to SSN

time

Output driver waveform

Vdd

Jitter caused by SSN for I/O

49

Target Impedance

50

R. B. Wu

Target Impedance

• Target impedance states that voltage to current ratio has to equal the impedance in the network. If exceeds it at any freq., resultant power supply noise will exceeds 5% of Vdd

51

p.s. allowed

transient

%

50%

T

dd

Max

VZ

I

V Ripple

I

R. B. Wu

Courtesy: Larry Smith (SUN)

Power Distribution Historical Trends

Target impedance for intel microprocessor decreases

500X in 1991-2002.

R. B. Wu

Realistic Target Impedance

• Spectrum of pulse is

frequency dependent, with

higher freq. spectrum smaller,

target impedance can be

frequency dependent too.

53

0.1 1 10 100 1000Frequency(MHz)

0.001

0.01

0.1

1

Z r

es

po

nse

(Oh

ms)

R. B. Wu

Resonance of

Decoupling

Capacitor

@ 0.5MHz

Anti-resonance

Circuit of PDN & Freq. Response

2

3

320

100

1

800

dd

s

s

chip

V V

R m

L pH

C F

ESL nH

C nF

target5%

10 10I A Z m

Max. imped. allowed

R. B. Wu

Voltage assuming 3m in impedance network

Idea: Switching circuit is represented using a time-dep.

resistor and simulate voltage across it.

Simulation of Power Supply Noise

97 197

rise time 10

only 3 in PDN

@97 , 20

@197 , 10

10

DC

DC

R m m

ns

m

m I A

m I A

I A

DC

tot

20A 10A under 2V

2 / 20 2 /10 100 200

I V

R m m

R. B. Wu

(b) 1us current period

(settled after 50ns)

(c) 80ns current period

(~ 13MHz)

(b)

97 m to

197 m

(c)

Voltage

assuming 3m

in impedance network

+5%

-5%

+5%

-5%

Two Current Signatures

R. B. Wu

Have you Learned?

• What is PDN?

• Why and how the PDN will cause noise?

• What is power supply noise?

• Why it is also called inductive noise, SSN noise?

• What are key parameters for inductive noise?

• What is target impedance? Why?

• How to simulate and assure it meets target

impedance?

• What is noise signature? How to simulate it?

57

R. B. Wu

Summary

• Power delivery noise is a challenge nowadays.

• The challenge will increase since:

– Device scale, more transistors, & smaller system

– Power & current increase, but voltage decreases

– Need clean power to transistor circuits, with Gbps propagating through package & boards

– EMI levels kept low to manage coupling & crosstalk

• Leakage power problem leads to multi-core processors

• Core & I/O circuit analysis is presented to estimate power delivery noise voltage and its effects on delay and jitter.

• Target impedance is an important parameter for power delivery design

• Power noise signature can depict PI in time domain. 58

fundamental issues of power...

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