ftf-fds-f0090 designing transmission lines in high-speed...

External Use

TM

FTF-FDS-F0090

Designing Transmission Lines in

High-Speed Circuit Boards:

To Prevent Problems

A p r i l . 0 9 . 2 0 1 4

Rick Hartley | Sr. Principal Engineer

L-3 Avionics Systems and RHartley Enterprises

TM

External Use 1

Agenda

• SI and EMC Recommended Reading

• What is Noise?

• Frequency Spectrum – Impact on Noise

• Basics of Grounding and Return Currents

• Low & High Frequency Currents and Field Movement

• Signal Propagation and Line Critical Length

• Misuse of Power/Ground Planes

• Routing to Control Common Mode EMI

• Impact of Connector pin out on CM EMI

• Impact of IC pin out on CM EMI

• Component Placement - Impact on EMI

TM

External Use 2

Agenda

• Planes - To Split or Not to Split

• Impact of I/O Connector Location on EMC

• DDR2 and other SI Routing Methods

• Low Noise Power Delivery System

• Impact of ICs on Power Delivery

• Decoupling for 2 Layer PC Boards

• Decoupling for 4 Layer PC Boards

• Decoupling for High Layer Count PC Boards

• Decoupling – Analog vs Digital

• Impact of Planes on Noise in Power Delivery

• PCB Stack-up for Signal Integrity and EMI

TM

External Use 3

1. Right the First Time- A Practical Handbook on High Speed PCB and

System Design - Volumes I & II - Lee W. Ritchey (Speeding Edge) -

ISBN 0-9741936-0-7

2. High Speed Digital System Design- A handbook of Interconnect

Theory and Practice - Hall, Hall and McCall (Wiley Interscience

2000) - ISBN 0-36090-2

3. High Speed Digital Design- A Handbook of Black Magic - Howard W.

Johnson & Martin Graham (Prentice Hall) - ISBN 0-13-395724-1

4. High Speed Signal Propagation- Advanced Black Magic - Howard W.

Johnson & Martin Graham - (Prentice Hall) - ISBN 0-13-084408-X

5. Signal and Power Integrity Simplified - Eric Bogatin (Prentice Hall) -

ISBN 0-0-13-702502-0

6. Digital Circuit Boards- Mach 1 GHz – Ralph Morrison (Wiley & Sons) –

ISBN 978-1-116-23532-4

TM

External Use 4

1. PCB Design for Real-World EMI Control - Bruce R. Archambeault

(Kluwer Academic Publishers Group) - ISBN 1-4020-7130-2

2. Digital Design for Interference Specifications- A Practical Handbook

for EMI Suppression - David L. Terrell & R. Kenneth Keenan

(Newnes Publishing) - ISBN 0-7506-7282-X

3. Electromagnetic Compatibility Engineering - Henry Ott (John Wiley

and Sons) - ISBN 978-0-470-18930-6

4. Introduction to Electromagnetic Compatibility - Clayton R. Paul

(John Wiley and Sons) - ISBN 0-471-54927-4

5. EMC for Product Engineers - Tim Williams (Newnes Publishing) -

ISBN 0-7506-2466-3

6. Grounding & Shielding Techniques - Ralph Morrison (5th Edition -

John Wiley & Sons) - ISBN 0-471-24518-6

TM

External Use 5

“Circuit Application notes produced by IC

manufacturers should be assumed Wrong

until Proven Right!”

Lee W. Ritchey

TM

External Use 6

Impact of Circuit Frequency on Design

Methods and Strategies

TM

External Use 7

• The title of this session asserts that we

can design Transmission Lines without

‘Problems’

• That we can design Transmission

Lines without the presence of what we

classically call ‘Noise’.

……. Meaning???

TM

External Use 8

• We refer to anything that changes the level of

energy in a circuit as “Noise”.

• Noise typically comes from one of 3 sources – – When “Intended energy in a circuit moves to an

unintended place(s)”!

– When ‘losses’ reduce the level of signal Energy.

• We will discuss the first 2 items.

– When Energy bouncing around a transmission

line distorts the signal (Ringing).

• What is “Noise”?

TM

External Use 9

• From 1950s into mid 1980s, most PC boards

could be laid out in almost ANY manner.

Why?

• Because frequencies were SO Low that every

circuit was a Lumped Length element.

• The circuits we put on PC boards are a –

• Yet seldom had Noise Problems…….

– Distributed Length at High Frequencies

– Lumped Length at Low Frequencies

TM

External Use 10

• Thinking in terms of the propagation time and

slew rate (Rise Time) of a circuit -

• Lumped circuits have a LONG Rise Time

compared to Propagation Time.

IN

CLOCK Prop Time

Slew Rate

• Distributed circuits have a SHORT Rise Time

compared to Propagation Time.

TM

External Use 11

• In the days of 5 MHz clocks and 100 ns Rise

Times, a circuit on a PC board was lumped until

its length exceeded ….. 10 feet (120 inches)!

• Today, with IC rise times in the range of 100 ps

to 2 ns, lumped lengths are …… 1/8 inch to 2.5

inches.

• Even in the 1980s, with clocks of 20 MHz and

rise times of 10+ ns, lumped lengths were…..

18 inches to 36 inches.

• How extreme is the effect?

TM

External Use 12

• Problems begin when the Time to Propagate a

Conductor’s Length is Greater than 1/4 of the

Signal Rise or Fall Time.

• Most extreme when Time to Propagate the

Conductor’s Length is Equal to or Greater than

the Signal Rise or Fall Time.

IN

CLOCK Prop Time

TM

External Use 13

• How do we calculate when line length starts

to become a Distributed element?

Inner Layer-

r

.25 x Tr x c =

(Where: c = Speed of Light- 11.80 inches/ns)

Outer Layer-

0.457r + 0.67

= .25 x Tr x c

TM

External Use 14

Max Line Length- Max Line Length-

DEVICE TYPE RISETIME Inner (Inch/mm) Outer (Inch/mm)

Standard TTL 5.0 nSec 7.27 / 185 9.23 / 235

Schottky TTL 3.0 nSec 4.36 / 111 5.54 / 141

10K ECL 2.5 nSec 3.63 / 92 4.62 / 117

ASTTL 1.9 nSec 2.76 / 70 3.51 / 89

FTTL 1.2 nSec 1.75 / 44 2.22 / 56

BICMOS 0.7 nSec 1.02 / 26 1.29 / 33

10KH ECL 0.7 nSec 1.02 / 26 1.29 / 33

100K ECL 0.5 nSec .730 / 18 .923 / 23

GaAs 0.3 nSec .440 / 11 .554 / 14

(Calculated assuming a nominal r = 4.1)

Line Length where control factors are needed

TM

External Use 15 15

• Outer Layer Trace – – DK of Air above Trace = 1.008.

– DK of FR4 below Trace = approx 4.1).

– Effective Relative ( ) is 3.00 to 3.50.

• Equations on next slide can Calculate

Effective Relative ( ).

r eff

r eff

• Sometimes Dielectric of

Line is not Constant, as

with Outer Layer Trace.

TM

External Use 16

• At 1 GHz = approx .550” (Microstrip- FR4)

• At 1 GHz = approx .475” (Stripline - FR4)

12

11

eff

criticalf

cL

eff if line is Microstrip

r if line is Stripline

– Function of 1/12th l of Frequency in DK

• Analog- Distributed Line Length –

TM

External Use 17

Effective Relative Er ( ) - Microstrip

2

104.012

1

1

2

1

2

1

h

w

w

h

rreff

1

h

w

w

h

rreff

121

1

2

1

2

1

otherwise

If-

eff_________________________________

TM

External Use 18

• A series of Sine waves, that are algebraically

summed to create a Square Wave

Harmonics

• If an analog signal is fundamentally a Sine Wave,

what is a Digital Square Wave?

TM

External Use 19

Time Domain Frequency

Domain

-20dB/

Decade

-40dB/

Decade

Freq

F1 F0 F2 (knee)

Amp T

Tr

Td

F0 = 1/T

F1 = 1/Td

F2 = 1/pTr

TM

External Use 20

F(freq-GHz)= .50 / Tr (rise/fall time- nSec*) * (Tr = 10-90% (Typical))

* (Tf = 10-90% (Typical))

• Frequency Bandwidth is from Clock to Maximum

Pulse Frequency.

• Highest Frequency of concern IS NOT the Clock.

• IS Frequency of the High Harmonics necessary to

create the Fast Rising Edges of the Signal.

• Called Maximum Pulse Frequency.

TM

External Use 21

• Initially to keep up with increased clock speeds,

needed to accomplish more tasks per second, so as

not to violate timing budgets.

• Today, fast rise times exist for 2 reasons –

– To keep pace with High MHz & GHz clocks.

– To manufacture more die per wafer, as a means of

keeping prices to a minimum.

• Why did Digital rise times get faster?

• ‘To manufacture more Die per Wafer’ is putting all of

us into High Speed Design, regardless of Clock

Frequency.

TM

External Use 22

Basic Circuit Behavior

TM

External Use 23

• The issue of Proper Grounding will be

discussed extensively, in this course.

• Designing to prevent problems, before they

happen, is fairly easy.

• Solving (or even Bandaiding) problems,

once a design is done, can be extremely

challenging.

• A Big part of controlling all Noise issues is

to establish proper Grounding.

TM

External Use 24

• An extremely Important aspect of “Grounding”

is to establish a good ‘Reference’ for return

current in Signal Lines (AKA- Transmission

Lines).

• This is important for Signal Integrity and for

control of all Noise and EMI.

• This will be an important part of every section

and topic during this presentation.

• As an example, with a trace on Layer 1 and a

plane on Layer 2, list the order…….

TM

External Use 25

….. from Least to Most, of Radiated EMI.

(Source: Prof. Tzong-Lin Wu, National Taiwan University)

TM

External Use 26

• A Transmission Line is any Pair of Wires or Conductors used to Move Energy.

• Voltage across Copper, Current in Copper.

• E and H Fields travel in the Dielectric.

Location of this side of the line is very important.

• ALL the energy is in the Fields!

TM

External Use 27

• Why is there current IN copper features and

voltage across the copper features?

• Because the fields establish the voltage and

induce the current, between the copper features,

as they travel in the Dielectric of the PC board.

• The Forward and Return Currents are created

simultaneously in the trace and the return plane.

• The energy is in the fields….. We must take care

of those fields, to stay out of trouble.

TM

External Use 28

• The return side of the line is the return plane or,

in some cases, the return trace.

• If we fail to fully understand how to set up the

return side of the transmission line, we create

field spread and put our circuits in ‘Harms Way’

with regard to noise.

• Whenever we route a trace on some layer of a

board, we are routing HALF of a transmission

line, the forward half of the line.

TM

External Use 29

L2- Ground.

Where does signal’s return current flow?

L1- Routed Signal, routed Power and poured Ground copper.

Signal Line

• 2 Layer PC Board -

TM

External Use 30

• Nature will always generate the lowest volume

of fields possible.

• In the board on the previous page, the lowest

volume of fields will exist between the trace

and plane, directly under the trace.

• Soooo….Why does return current take the path

under the trace, at frequencies beyond a few

KHz?

TM

External Use 31

• The traces or the trace and plane that make up

the Transmission Line steer the energy from

point A to point B.

• These copper elements act as a Wave Guide!

• The energy (E & H/M Fields) in a transmission

event is called a Wave, an Electro-Magnetic Wave.

TM

External Use 32

• Impedance is

Basically –

Lo

Co Zo =

• The path of least impedance is the path of

Lowest Inductance and the path of Highest

Capacitance.

…….Why?

• When the return current path is directly under the

trace, we often refer to this as the ‘Path of Least

Impedance’.

TM

External Use 33

• Doing this minimizes spread of both fields and creates low

impedance paths with Low Inductive losses and low spreading

of the Electric Field.

• Tight coupling between forward and return path are secret to

lowering Inductance and to Low Magnetic Field coupling.

• Inductance is an Inertia to Changes

in Current flow, caused by energy

stored in the Magnetic Field.

• Keep the volume of Fields low,

Energy in the Fields will be low

and Inductance will be low.

• To Keep Capacitance High. ......Same thing, tight spacing.

TM

External Use 34

• Fields will generate a current in copper features

based on ‘Skin Depth’.

• OK, Then….. why does low frequency current

spread out across the majority of the plane?

• Current spread across the plane occurs as a

substitute for deep penetration into the copper.

• At low frequencies ‘Skin Depth’ is very thick and

current wants to penetrate to a depth that is

greater than the thickness of the plane copper.

TM

External Use 35

• Where is this Trace’s Return Path, with NO planes,

at slow speeds of many years ago?

Vcc (DC Voltage Rail) Vss (DC ‘Ground’)

Vss (DC ‘Ground’) Vcc (DC Voltage Rail)

• At Today’s high speeds???

TM

External Use 36

At Audio Frequencies! • Where would this be used?

• At Frequencies above 20 KHz or so return currents

would be in other signal lines, NOT in Ground.

Ckt 1 Ckt 2 Ckt 3 Ckt 4

TM

External Use 37

• Is low noise in 2 layer boards w/o continuous planes

possible?

… with returns routed with each trace!

Yes… if designed correctly…

TM

External Use 38

-- ----------------- --- Signal – Layer 1

-- -- -- -- -- -- Signal – Layer 2

---------------------------- Ground – Layer 3

-- -- -- -- -- -- Signal – Layer 4

• What’s Wrong with this Board Stack-up???

• The fields associated with the signals on layer 1

will couple to and thru layer 2 and to the plane on

layer 3. …Serious field Spreading!!!

TM

External Use 39

-- -- -- -- -- -- Signal – Layer 1

---------------------------- Power – Layer 2

---------------------------- Ground – Layer 3

-- -- -- -- -- -- Signal – Layer 4

• What’s Wrong with this Board Stack-up???

• Almost EVERYTHING!!!

• We will discuss the problems as we go!!!

TM

External Use 40

• Where is the Return Current?

• IC powered by

+12V & Gnd -

• What’s Wrong here?

• Where are the Fields?

TM

External Use 41

• Some of us are taught to look for the Direct

Connection (Ground) that completes the circuit.

• The ‘Direct Connection’ concept only holds true

at DC and very low frequencies.

• Current follows the fields, taking the path of least

impedance, whatever that might be.

• Why did the engineer in the previous example

believe the Ground plane was the return path for

the signal on Layer 1?

• At low MHz, certainly in the 100s of MHz and up,

the AC connection is MORE important.

TM

External Use 42

• Earth Ground is NOT a good return path for

ANYTHING at high frequency.

• In today’s electronics ‘Earth Ground’ should only

be used for - – Safety Connection (Green Wire in 3 Wire AC Line).

• As an aside- It is NOT necessary to attach a

system or unit to the Earth to pass EMI

Testing!!!

– Lightning Protection.

TM

External Use 43

• ‘Ground’ is often thought of as a place to attach

components to bleed off or filter noise as if it is a

sink hole that eliminates noise from circuits.

• Only CLOSE to true at DC.

NOT TRUE!!!

• Concept and belief that many people have of

‘Ground’ Does Not exist !!!

• ‘Ground’ on PC Boards is often considered a

region of ZERO Volt Potential with Zero Re-

sistance, Zero Impedance, etc.

TM

External Use 44

“Ground is a

place where

Carrots and

Potatoes

Thrive!”

Source: Dr. Bruce Archambeault

• To illustrate his concern for the misuse of the

term ‘Ground’, Dr. Bruce Archambeault is quoted

as saying -

TM

External Use 45

-- -- -- -- -- -- -- Signal

-- -- -- -- -- -- -- Signal

---------------------------- Power

---------------------------- Ground

-- -- -- -- -- -- -- Signal

-- -- -- -- -- -- -- Signal

• Years ago, before understanding what causes

‘Noise’, we were faced with an EMI problem from

a 6 layer board -

• Thought we had ideal layout. Not sure what to do.

TM

External Use 46

----------------------------- Chassis

-- -- -- -- -- -- -- Signal

-- -- -- -- -- -- -- Signal

----------------------------- Power

----------------------------- Ground

-- -- -- -- -- -- -- Signal

-- -- -- -- -- -- -- Signal

----------------------------- Chassis

• After a long meeting of uninformed minds, we

decided we needed to ‘Shield’ layers 1 & 6 -

TM

External Use 47

• Return currents had NO easy path back to their

source.

• The signals on the new layers 2 and 7 were

mostly referenced to a plane that did NOT

connect to the board at any location!!!

• Field spread was extreme, hence much higher

levels of common mode current and EMI.

...Why? our EMI

signature got worse, instead of better!

• After adding ‘Chassis’ layers to board,

TM

External Use 48

• Determine the location, in the circuit, where the

fields will establish the lowest volume and where

they will generate voltage and current!!!

• Make those copper features the reference for

return currents, whether the reference is other

trace(s) or plane(s)!!!

• Think in terms of “Return Paths” used to reference

Field Energy!!!

• Don’t think in terms of “Ground”!

TM

External Use 49

Remember this… what is the order, best to Worst?


TM

External Use 50

EMI Signatures of all 4 cases -

(Source: Prof. Tzong-Lin Wu,

National Taiwan University)

TM

External Use 51

Why is the ‘Best to Worst’ order 1, 3, 4, then 2?


TM

External Use 52

• What is a “Microstrip Coupled, Slotline Fed Antenna”?

• This is intentional coupling of the trace’s energy,

into the slot to feed the edges of the plane,

to cause radiation!!!

Trace on Layer 1 Slot in Gnd Plane-

Layer 2

TM

External Use 53

• What if the Line crosses a Split Return Plane?

• Where does Return Current Flow in case above?

• Where are the E and M/H Fields??????

TM

External Use 54

• What if Return Plane is Split for entire width?

• Where does Return Current Flow in case above?

• Where are the E and M/H Fields??????

TM

External Use 55

– Couple energy into the edges of planes, causing

edges to resonate like an antenna.

– Cause the board to resonate and possibly radiate

like an antenna.

• All of these items will likely increase EMI!

– Couple energy into other traces and vias on

the board, resulting in Common Mode currents

that spread across the board.

• The spreading Fields that result from routing

across Split Planes will –

TM

External Use 56

• When moving signals between layers, route on either

side of the same plane, as much as possible!!!

Return Current

Signal Current in Trace

Ground

Via Hole in plane

Signal Current in Trace

Return Current Ground

Ground

• When moving signals between 2 different planes,

use a transfer via VERY near the signal via.

Via Hole in planes Ground Via

TM

External Use 57

(Source: Dr. Howard Johnson)

Even with

‘Ground’ on

Different

Layers the

via structure

creates a

slight E & H

Field Loop!!!

TM

External Use 58

• Routing from Power reference to Ground reference – – Return Current below 200ish MHz uses Decoupling Caps.

• This works fairly well when Plane Separation is

reasonably small (i.e.- Less than 8 mils).

Return Ground

Power

Signal

Via Hole

– Higher Frequency return couples using displacement current.

Return Ground

Power

Signal

Via Hole

TM

External Use 59

Cap works to about 3-4 times Self Resonant Frequency.

Capacitive

Impedance

• Capacitor’s ability to move energy efficiently is a

function of the device’s impedance due to

Capacitance and impedance due to Inductance-

Inductive

Impedance

Frequency

Imp

ed

an

ce

Self

Resonance

TM

External Use 60

Return Ground

Power

Signal

Via Hole

• Current spreads over large area, to form large

enough capacitance that displacement current

of sufficient amplitude can form.

• When routing signals from Power reference to

Ground reference, with widely spaced planes

(i.e.- 4 Layer Board) -

TM

External Use 61

These same rules apply to Diff Pair routing – • When a pair of Diff lines change layers……

• Having NO return path vias….

• Almost guarantees creation of common mode

currents, leading to EMI.

or having imbalanced return vias…..

TM

External Use 62

• Simply balancing return vias, like……

• Will effectively eliminate CM Currents!

This

This

Or this

TM

External Use 63

– Couple energy into the edges of planes, causing

edges to resonate like an antenna.

– Cause the board to resonate and possibly radiate

like an antenna.

• All of these items will likely increase EMI!

– Couple energy into other traces and vias on

the board, resulting in Common Mode currents

that spread across the board.

• The spreading Fields that result from poor layer to

layer routing will –

TM

External Use 64

What about Connector Pin Assignment?......

Why Reference Power and Ground???

- Very Poor!

G G S

G G S

S

S

S

S

S

S

S

S

S

S

S

S

S

S

S

S

S

S

S

S

S

S

S

S

S

S

P

P

- Better.

S G S

S S S S G S

S S S S P S

S S S

S S S

S G S S S S

S P S S S

G S

S

P S

G

- Much Better!

S G S

S G

S S P S

S P S S G S

S P S

S P S

S G S

S G S

S P S

- Best!!!

P

G S

S

G S G

P S

P S P S

S G S G S G

S P S

S G S

P S P

G S G

S P S

TM

External Use 65

F1120 had 5X greater noise level than FF1148 -

(Source: BGA Crosstalk

- Dr. Howard Johnson)

Impact of Lead Frame on signal noise and Vcc/Ground Bounce

TM

External Use 66

Component Placement

TM

External Use 67

– Analog in one area, Digital in another.

– Devices Operating at Different Voltages.

– Devices at Different Frequencies.

– By Function within a Given Family or Voltage.

– All ICs routing to Connectors MUST be placed

Very Near their respective connector.

Positions of Components -

• Group Components by Function / Family.

TM

External Use 68

Sections must not

route thru one another. 1- Power Conn. 1- Conn to Front Switches.

1- Digital I/O Conns.

1- Analog

I/O Conns.

1- IC with

Heat Sink

to Case.

1- Conn to

another PCB.

1- Mounting

Holes

2- Main I/O Circuit.

2- High Freq

Analog.

3- Power

Input

Circuit.

3- Switch

Interface

Circuit.

4- D/A

Converter

.

4- Low Freq

Analog.

5- PCB Inter-

face Circuit.

6- Remaining

Digital.

TM

External Use 69

– Frequency of each circuit.

– Position of components in each circuit.

• If Traces are isolated to their own Sections,

the Need to split Analog & Digital Ground is

Rare. Decision based on -

(When 100+ dB of isolation between circuits is a

requirement and when circuits are in very close

proximity, even at high frequency, isolating planes

may be necessary.)

(Low frequency Analog may need split plane)

But…….

TM

External Use 70

• Mixed Analog and Digital Designs -

• Keep EVERYTHING Analog in Analog Section!

• It will NOT be Necessary to Split Ground!!!

• Keep EVERYTHING Digital in Digital Section!

Analog

A/D

Digital

20H+ Separation

of Components

and Routes

TM

External Use 71

– Along One Edge of the PC Board.

• Locate High Frequency Circuits and Conn-

ectors away from Lower Frequency Circuits

and Connectors.

• Signals Connecting to Cables:

– Group Connectors by Frequency and

Function.

TM

External Use 72

• To illustrate issue of Connector Placement, the Ldi/dt

voltage drop across a Ground Plane, in a circuit with

conventional ICs, is sufficient……

PCB + –

• To cause an FCC, Class B or CISPR Radiated

Emissions Failure.

… when attaching cables to both sides of PCB, with

connections of Un-filtered Ground –

I/O Cable I/O Cable

TM

External Use 73

– The "ground" plane in this design does carry

signal currents.

– In fact, the current flowing in the plane

generates a magnetic flux that wraps around

the plane.

– If we view the two cables as parts of an antenna

and represent the antenna current path by an

antenna impedance as illustrated on the next

slide……

• From Dr. Todd Hubing (Research Professor

at Clemson University) -

TM

External Use 74

Picture- Dr. Todd Hubing

– … it becomes apparent that the currents

flowing in the trace circuit induce a voltage

across the plane that drives one cable relative

to the other.

TM

External Use 75

– … a few millivolts of noise on an efficient

antenna is sufficient to exceed FCC and

CISPR radiated emissions requirements.

• Dr. Todd Hubing (continued) – – While it is true that the voltages induced

across the plane are generally a few

orders of magnitude lower than the

signal voltages….

TM

External Use 76

IC + –

I/O Cable I/O Cable IC

• Dr. Todd Hubing (continued) – – In fact, when high-speed digital ICs are

located between connectors on a board,

in an unshielded product, it is very

difficult to meet radiated emissions

requirements.

TM

External Use 77

• Dr. Todd Hubing (continued) – – On the other hand when two connectors are

located next to each other, it is unlikely that

magnetic fields will induce enough voltage

between them to cause a problem

PCB

+ –

I/O Cable

I/O Cable

TM

External Use 78

• Don’t do this……

A board with –

• Un-filtered I/O

• Micro-Controller

near the center

• Feeding signals to

many connectors….

• ALMOST CERTAIN to

Fail EMI testing!!!

Micro

I/O

I/O

I/O

I/O

I/

O

I/O

TM

External Use 79

Trace Routing Strategy

TM

External Use 80

% Reflection = ZDownstream - Z0

x 100 ZDownstream + Z0

• When a Pulse propagates a Transmission Line of

Impedance Z0 and reaches a Load of the same

Impedance, ALL the energy is Transferred.

• If Downstream Impedance is Un-terminated IC Input

(ZLoad), having extremely High Impedance, the signal

doubles in amplitude and Reflects back toward the

Source.

TM

External Use 81

− The two lines routing off this Tee point are Parallel

impedances, hence they look like 30W Not 60W.

60W

60W

60W

This parallel set of

lines look like 30W to

the wave energy

propagating the line. energy

• When a wave hits a Downstream impedance Lower

than Zo, the Reflection will be Negative.

− From the previous equation, the downstream Zo of 30W will cause a -33% reflection.

− Large Negative reflections cause circuit malfunction!

TM

External Use 82

60W

60W

60W energy

• As a result, TEE ROUTING IS NOT AN ACCEPTABLE

DESIGN PRACTICE!!!

60W 60W

60W energy

(How short is acceptable will be discussed)

(Unless one of the lines off the Tee point is short)

TM

External Use 83

or the branch lines kept at lumped length ……

the ringing on the line can be eliminated!!!

• With DDR design, for example, if either the

entry line can be kept a lumped length….

TM

External Use 84

Result of Long Stubs and No Line Termination.

OSCILLOSCOPEDesign f ile: SIMPTLUT.TLN Designer: LEE RITCHEY

BoardSim/LineSim, HyperLynx Inc.

Comment: Fast TTL Driver, 3 load net 7.000 volts

-2.000 volts

0.0 volts

0.000ns 50.000ns

1 V/div

5 nsec/div

Date: Tuesday Jun. 3,1997 Time: 13:36:02

Probe 1:RS(0,0).2

Probe 2:U(0,1)

Probe 3:U(0,1)

Probe 4:U(0,2)

Probe 6:U(1,1)

Show Previous Waveform = YES, Show Saved Waveform = YES

TTL "1"

TTL "0"

TM

External Use 85

SI Partial Solution -

Dotted Line is rerouted Trace.

Cause of Extreme Ringing -

Keep Stubs Shorter than ½ Length in Table (Pg. 14)

TM

External Use 86

Parallel Resistor

• Used with Strong Drivers (Needing Incident Wave Switching).

• Some Logic Families Must be Parallel Term (ECL, GTL, etc.).

• Place Resistor at, or just beyond Last Load, within ½ distance

of table on page 14.

• Resistor Value = Zo.

• Resistor Needed at Both Ends of Bidirectional Net.

• High Power Consumption (DC Load when Output is High).

• Low Power Outputs CANNOT drive this Low Impedance.

TM

External Use 87

Parallel Terminated Transmission Line

OSCILLOSCOPEDesign file: SIMPTLUT.TLN Designer: LEE RITCHEY


Comment: Simple Series Unterminated Transmission Line 7.000 volts

-2.000 volts

0.0 volts

0.000ns 10.000ns

1 V/div

1 nsec/div


Probe 1:RS(0,0).2

Probe 2:U(0,1)


TM

External Use 88

Series Resistor

• Must place Resistor at Driver, within ½ of distance in

table on page 14.

• Resistor Value = Zo - Rs(Output Impedance).

• Reflection occurs and is Absorbed back at the Driver.

• Most common w/ Single Load or ALL Loads at end of

Line.

• Low Power Consumption.

• Helps Eliminate Ground Bounce.

• Lowers Power Transients and EMI Dramatically.

TM

External Use 89

Series Terminated Transmission Line

(DO NOT Parallel AND Series Term)

OSCILLOSCOPEDesign file: SIMPTLUT.TLN Designer: LEE RITCHEY


Comment: Simple Series Terminated Transmission Line 8.000 volts

-1.000 volts

0.0 volts

0.000ns 20.000ns

1 V/div

2 nsec/div


Probe 1:RS(0,0).2

Probe 2:U(0,1)


TM

External Use 90

Point-to-Point

Tee Route

Daisy Chain

Branch by ‘N’

(D = Driver)

TM

External Use 91

Power Delivery System

TM

External Use 92

• Design feature of PC board with enormous

impact on Signal Integrity and EMI.

• PDS is the Foundation of the ‘Building’.

• If PDS fails to provide Current to Output Stages

at any Frequency from Clock to .50/Tr -

– Transients Develop and EMI risk increases.

– IC Rising / Falling Edges can be distorted, creating

Non-Monotonic Signals.

TM

External Use 93

• Just a reminder, High Inductance in pins

leads to High levels of Switching Noise –

• Usually leading to EMI Issues!!!

Sig

Gnd

Pwr Ground

Power

TM

External Use 94

Great example of Very Well Designed IC!!!

This is how ICs of the future must be designed!!!

Began as 324 pins. Is Now 416 pins!

TM

External Use 95

• By Design, Power Supply cannot respond

Rapidly to Demands for Current to ICs.

• Power System Capacitance Provides Current

until Power Supply can respond.

• Multiple Harmonics Require -

– Power Bus Capacitance be high at broad range

of Frequencies.

– Power Bus Inductance MUST be Low.

– Power Bus Impedance MUST be VERY Low.

TM

External Use 96

Power Bus Decoupling - • Decoupling capacitance provides local energy source

to feed IC stages driving transmission lines.

• Decoupling capacitance recharges with energy from

the power supply when outputs are not driving.

• Decoupling also helps stabilize the power bus, to

drastically lower switching noise (Ldi/dt) Losses).

• Decoupling structure’s Inductance must also be very

low to help minimize switching noise.

• Boards without adequate decoupling can suffer from

SI issues and usually suffer from EMI problems.

TM

External Use 97

Power Bus Decoupling - • Early PC Boards were Analog circuits and required

carefully planned Decoupling to work at all.

• Early Digital boards had such slow rise time outputs

that decoupling was sometimes not even needed.

• Even when needed, early Digital Decoupling was very

often treated as an afterthought.

• Nominal amounts of decoupling capacitance often

netted designs which worked without problems.

• As digital Rise Times got faster it became imperative

to focus on precise decoupling schemes.

TM

External Use 98

Cap works to about 3-4 times Self Resonant Frequency.

Capacitive

Impedance

Self

Resonance Frequency

Imp

ed

an

ce

• Capacitor’s ability to move energy efficiently is a

function of the device’s impedance due to

Capacitance and impedance due to Inductance-

Inductive

Impedance

TM

External Use 99

Capacitor Lead Frame Inductance (Per AVX):

Axial Lead - 2000 pH

1206 SMD - 1250 pH

0805 SMD - 1050 pH

1210 SMD - 980 pH

0603 SMD - 870 pH

0402 SMD - 650 pH Side Mounted Leads

0612 SMD - 610 pH

0508 SMD - 600 pH

16 Pin BGA - 50 pH

TM

External Use 10

0

• How Much Decoupling is enough???

• Large Vias connecting Caps to Planes???

• Which Decoupling strategy is Best?

Speaking of Power Bus Decoupling - • Do we need Power / Ground Planes in the PCB???

Via to

Plane

Via to

Plane

Via to

Plane

Via to

Plane

TM

External Use 10

1

Power Bus Decoupling - • The decoupling strategy needed for a given board is

based almost entirely on the type of board used.

• In general there are 4 types of boards in use –

– Digital boards with Routed Power Rails, whether

Ground Plane only or Routed Ground.

– Digital circuit boards with Widely spaced Power &

Ground planes.

– Digital boards with Closely spaced P & G planes.

– Boards containing Analog circuits, regardless of the

plane arrangement in the board.

TM

External Use 10

2

• At least 1 High Frequency capacitor (ie- .1uF) for

each IC.

• 2 high frequency caps, in Parallel, are better than

one capacitor of twice that value. Two caps –

– Potentially have half the connection Inductance.

Power Bus Decoupling (General Rules)- • At least 1 "bulk“ capacitor (ie- 25uF, 50uF) for

each voltage rail, located where rail is Developed

or where rail Enters the board.

– Better High Frequency Filtering to Power Bus.

… located as described in later slides.

TM

External Use 10

3

• Minimize Loop Area Inductance of capacitor

connection to the IC Power Pins.

Cap connection with Routed Power- Via to

Rail

Via to

Rail

Locate the Decoupling

Capacitor on the same

side of board as IC and

Very Close to IC power

pins.

• Raise Inductance of cap connection to board Power

Rails, creating True Decoupling between ICs.

• Can add Ferrite, for additional isolation of IC to

board Power Rails, but generally NOT needed.

This will-

TM

External Use 10

4

Cap connection, Widely Spaced Planes-

Preferred Connection,

to Minimize Inductance

of connection to both

IC and Planes.

(Widely Spaced = Greater than 12 mils separation)

Via to

Plane

Via to

Plane

• Capacitor can be on same side as IC or opposite

side of board, but MUST be close to IC Pins.

• Capacitor feeds power to IC before Planes feed

energy to the IC, since Inductance of Cap connec-

tion is Lower than Inductance of Plane Pair.

TM

External Use 10

5

• Locate Capacitor at IC Pin connected to Plane

that is farthest away, in the board stack.

Via to

Plane

Vias to

Plane Ground Power

When IC Power /

Ground pins are

separated by a

Wide distance –

• If Power is on Layer 2 and Ground on Layer 3 (of

a 4 Layer, 1.5mm thick PCB)…..

• This is simply making the best of a bad situation!!!

Place Cap next

to Ground Pin of IC, as shown above.

Cap connection, Widely Spaced Planes-

TM

External Use 10

6

Closely spaced Power/Ground Planes- (Closely Spaced = 10 mils or Less separation)

• In this type board, planes contribute to decoup-

ling through fairly high Capacitance and Very

Low Inductance.

• The Inductance of the planes is MUCH lower

than the connection Inductance of the Capacitors

to the Planes.

• During the entire Rise Time of the IC’s Output

transition, all the decoupling current is delivered

through the Inter-Plane Capacitance of the board….

… Therefore –

TM

External Use 10

7


… regardless of how well the Decoupling Capac-

itors are attached to the planes.

• As a result the location of the decoupling capac-

itors is not important (they do not have to be

close to the ICs)….

• As long as they are “Close Enough”, meaning…

• The Low Impedance (Low Inductance) of the

planes dominates performance.

TM

External Use 10

8


• The capacitors are located within a radius defined

by rise time of the IC Output.

• Energy in FR4 travels at

6 inches / ns, so for an IC

with 250 ps Tr, the caps

need to be within 1-1/2

inches of the desired

Power Pins.

TM

External Use 10

9

TI’s ‘Opinion’ on Decoupling

• The Top Structure, above, is Especially

Important on boards with Closely Spaced

Power and Ground Planes.

TI’s App Note is

correct for boards

with Routed Power

Rails.

Many research papers

explain why ‘NOT’ to

use the bottom

structure on Boards

with Power Planes.

TM

External Use 11

0

Power Bus Decoupling – • In all cases, Bulk Decoupling should be

between 1 to 10 times Total High Frequency

Decoupling.

• High Frequency Capacitors (ie- .1 uF) should be in

the smallest package your production processes

can support without having assembly problems.

• Once a capacitor size is chosen, select parts with

the highest value available in that package style

(never use a capacitor whose value is less than the

value of the board’s Inter-Plane capacitance).

(Good Rule-of-Thumb = 5X)

TM

External Use 11

1

Power Bus Decoupling- Where? • Whenever possible, mount High Frequency Cap-

acitors on the surface of the board nearest the

power plane pair.

− This comes into play with high layer count boards, where the

Power / Ground pair will likely be nearer one side of the board

(ie- Top or Bottom Layer).

• With routed power or Widely spaced planes, Bulk

Decoupling needs to be near the Power Feed Point.

• With Closely spaced planes, Bulk decoupling is

shared and can be anywhere on the board.

TM

External Use 11

2

• Caps and Planes together can achieve this impedance.

Ideal Power Delivery

Impedance

Frequency Clock .5 / Tr

0.1W

TM

External Use 11

3

• Many ICs need current at broader frequency range

than can be provided by one value of capacitor.

• Many IC manufacturers recommend 2 (or More)

Values of Caps at IC Pins.

− Small Value (High Freq) Nearest IC Pins.

− 100 x Small Value (provides Current).

(ie- 1000pfd and .1mfd.)

• This Carries an Inherent Danger!!!

TM

External Use 11

4

• Intended Goal of Two Parallel Capacitors.

Z

Frequency

1000pF

0.1uF

TM

External Use 11

5

1000pF

0.1uF Z

Frequency

• This is what REALLY Happens!!!

TM

External Use 11

6

• If Clock Frequency is below 30 MHz and IC Output

Rise/Fall times are slower than 2.0ns –

− Decoupling Capacitors alone can delivery the spectrum of

frequencies in the IC outputs.

− Place one(1) decoupling cap per IC power pin, as near

the power pin as reasonably possible.

− Power delivery can be a Plane or can be routed.

• Example is 8 bit Micro-Controller for the automotive or

appliance industries.

TM

External Use 11

7

Caps alone can handle frequencies up to 200ish MHz.

.01

.1

1

10

Imp

edan

ce -

W

Frequency - MHz 10

6

0.1uF

Caps

10 7 10

8 10 9

TM

External Use 11

8

• With Fast Tr ICs Power/Ground Planes

across Digital Boards MAY be required!!!

− High in Capacitance / Low in Inductance.

− Planes are the path of Very Low

Impedance, at High Frequencies.

− In Digital Systems, where Many ICs simul-

taneously switch - Distinct improvement in

Transients, Switching Noise, even Ground

and Vcc Bounce (All Ldi/dt events).

TM

External Use 11

9

Most circuits in the world of today!!!

• If Clock Frequency is 30 MHz to the mid 100s of MHz

and IC Output Rise/Fall times are Faster than 1.0ns –

− Decoupling Capacitors and close set Power and Ground

Planes in combination are needed to delivery spectrum of

frequencies to IC outputs.

− Place one(1) decoupling cap per IC power pin, reasonably

near IC Power pins.

• Example is….

− Place Vias from IC Power / Ground pins in close set pairs,

directly to the planes.

TM

External Use 12

0

10

0.1uF

Caps Power / Ground

Planes - 7 mils

.01

.1

1

Imp

edan

ce -

W

Frequency - MHz 10

6 10 7 10

8 10 9

Caps and Planes needed for frequencies up to 1 GHz.

TM

External Use 12

1

• At higher GigaBit rates, 2 or more sets of close set

Power and Ground plane pairs may be needed.

• If Signal Speed is in the GigaBit region and Clock

Frequency in the GHz range –

− Decoupling Capacitors and extremely close set Power and Ground Planes in combination are needed to delivery board spectrum of high frequencies to IC outputs.

− Place as many decoupling caps as will fit near IC Power

pins. These are less important than the planes.

− Place Vias from IC Power / Ground pins in close set pairs,

directly to the planes.

TM

External Use 12

2

0.1uF

Caps

Power / Ground

Planes - 2 mils

.01

.1

1

10

Imp

edan

ce -

W

Frequency - MHz 10

6 10 7 10

8 10 9

Caps and Very Low Z Planes needed for GBit speeds.

TM

External Use 12

3

• Via Inductance [.062 long (PCB thickness)] -

Lv = 5.08h x [2 ln(D/R)]

Lv = 5.08(.062) x [2 x

ln(.025/.005)] = 1.01nH

20

D=25

R=5

S G

Lv = 5.08h x [2 ln(D/R)]

Lv = 5.08(.062) x [2 x

ln(.250/.005)] = 2.50nH

20

D=250

R=5

S G

• To illustrate the importance that proximity (Spacing)

has on Inductance -

TM

External Use 12

4

= Power Plane Inductance =

Dielectric

thickness Inductance

----------- -------------

2 mils 65 pH/square

4 130

8 260

16 520

50 mils 1.625 nH/square

Source: Sun Microsystems

TM

External Use 12

5

Power and Ground Planes .003” (.075mm) to .008” (.2mm) Spacing creates a

Large Plate Capacitor of Low Inductance.

- Don’t try this on 4 Layer Boards -

.006”

(0.15mm)

150 pF / sq. inch

23 pF / sq. cm

TM

External Use 12

6

Most PC Boards are “Foil Laminated”

‘C’ Stage Core

‘C’ Stage Core

25 to 45 Mil Thick ‘C’ Stage Core

Pre

pre

g

Copper Foil

Copper Foil

TM

External Use 12

7

• Power Bus

Switching

Noise

relative to

spacing

between

Power and

Ground.

(Source: Missouri University of Science and Technology)

TM

External Use 12

8

Observations from Bypass Capacitor Research Paper *

* (Power Bus Decoupling on Multilayer Printed Circuit Boards. Hubing, Drewniak, Van Doren and Hockanson, IEEE Transactions on Electromagnetic Compatibility, Vol. 37, No 2, May 1995.)

• At frequencies where surface mount capacitors are functional (below 200 MHz), all capacitors are shared and location is relatively unimportant, so long as power planes are continuous and closely spaced.

(- Continued -)

TM

External Use 12

9

• The capacitance formed by the parallel plates of the power planes provides all switching currents from about 150 to 200 MHz and up.

Observations from Bypass Capacitor Research Paper *

• Multilayer boards with a few nanofarads of interplane capacitance that have decoupling capacitors con-nected through a few nanohenries of inductance derive little, if any, benefit from any added capacitors above approximately 100- 200 MHz.

TM

External Use 13

0

• Each Power Plane should be referenced to a

Ground Plane on next layer (except layers 2

and 3 of a 4 layer board).

• Power can be Routed (regardless of Frequency)

on the Analog side of board.

• Power should ALWAYS be distributed through

Planes in Digital portion of a board.

TM

External Use 13

1

• Analog Power Decoupling Consists of Pi Filter

(Low Pass) with Several Capacitors to create

resonant circuit at Frequency of operation of

Analog IC output -

TM

External Use 13

2

(Notice Order of Capacitors)

How do we

keep solder

from spreading

everywhere at

these joints?

TM

External Use 13

3

– Digital ICs switch a broad range of High Freq-

uencies (Clock to .5 / Tr).

– Since Digital ICs need power at a broad range of

frequencies, power must be delivered at a broad

range of frequencies.

• For Digital, use Tight Power/Ground Plane pairs

and one value of Decoupling Cap.

• Connecting Power to Digital ICs through a Pi

Filter usually causes starvation of power to the

IC output stages.

TM

External Use 13

4

(Source - Right the First Time, Lee Ritchey) Pi Filter Removed

• Connecting Power to Digital ICs through a Pi

Filter will likely result in Signals like -

TM

External Use 13

5

PC Board Stack-Up

TM

External Use 13

6

• Since Decoupling Capacitors cannot provide energy above 150 MHz (at Best), Energy for Fast Switching edges is drawn from the capacitance formed by the parallel plates of the power planes in the PCB.

• Many PCBs do not have sufficient power plane area to create a capacitor large enough to supply the switching currents required.

• The result is excessive high frequency ripple on the power planes and associated high EMI.

(Info largely from Speeding Edge)

TM

External Use 13

7

• Most PCBs have significant unused spaces on Signal Layers.

• This unused area can be Filled with Copper to provide Additional Plate area to increase the size of this capacitor.

• Copper fill areas must be tied to the appropriate voltage using component power leads or single pin parts with the appropriate designation. (Use vias to do the tie.)

(Info largely from Speeding Edge)

TM

External Use 13

8

Power plane capacitance without fill, 500 pF.

LAYER 1, SIGNAL LAYER 2, Vcc LAYER

LAYER 3, SIGNAL LAYER 4, SIGNAL

LAYER 6, SIGNAL LAYER 5, GROUND LAYER

FILLED WITH GROUND

FILLED WITH GROUND

FILLED WITH Vcc

FILLED WITH Vcc

…with fill 4100 pF.

TM

External Use 13

9

0

5

10

15

20

25

30

35

40

45

30 40 50 60 80

80.18

110

120

130

140

150

160

180

200

225

250

275

300

325

350

375

400

425

450

500

550

600

700

800

900

1000

EM

ISS

ION

S (

db

uV

/M)

FREQUENCY (Mhz)

EMISSIONS TEST RESULTS WITH AND W ITHOUT SIGNAL PLANE FILLS

CISPRB LIMIT

(From Speeding Edge)

Light Green Bars are Unit w/o Power Plane Fills.

Dark Blue Bars are Unit with

Power Plane Fills.

TM

External Use 14

0

Four(4) Layer Designs

(A) ----Ground----- (B) ---Sig/Poured Pwr---

----Sig/Pwr---- -------Ground---------

----Sig/Pwr---- -------Ground---------

----Ground----- ---Sig/Poured Pwr---

TM

External Use 14

1

----Sig/Pwr----

----Ground-----

----Sig/Pwr----

----Ground-----

-----Power------

----Sig/Gnd----

-----Power------

----Ground------

----Ground------

-----Power------

----Sig ---- /Gnd

----Sig ---- /Pwr

Six(6) Layer Designs

TM

External Use 14

2

Six(6) Layer Designs to AVOID

-----Signal------ -----Signal-----

-----Signal------ -----Power-----

----Ground------ -----Signal------

-----Power------ -----Signal------

-----Signal------ ----Ground-----

-----Signal------ -----Signal------

TM

External Use 14

3

Six(6) Layer Designs

-Short Sig/Pwr- ----Sig/Pwr-----

----Sig/Gnd----- ----Ground-----

-----Power------ ----Sig/Pwr-----

----Ground------ ----Sig/Gnd-----

----Sig/Pwr----- -----Power------

-Short Sig/Gnd- ----Sig/Gnd-----

TM

External Use 14

4

8 Layer Stack-up recommended by a MAJOR

IC company, for use with a High Speed CPU

----Signal------

---Ground-----

----Signal------

---Power 1----

---Power 2----

----Signal------

---Ground-----

----Signal------

With enough capacitance on

Die and Substrate, Signal

Integrity could be OK……

BUT……

Clearly they completed NO

EMI testing!!!

TM

External Use 14

5

Eight(8) Layer Designs

(A) ----Signal----- (B) ---Sig/Pwr----

---Ground----- ---Ground-----

----Signal----- ---Sig/Pwr----

----Power----- ---Ground-----

---Ground----- ----Power-----

----Signal----- ---Sig/Gnd----

---Ground----- ----Power-----

----Signal----- ---Sig/Gnd----

(‘B’ is even better than ‘A’ due to Copper Pours)

TM

External Use 14

6

Eight(8) Layer Designs to AVOID

----Signal----- ----Signal----- ----Signal-----

----Signal----- ----Signal----- ----Power-----

----Signal----- ----Power----- ----Signal-----

----Power----- ----Signal----- ----Signal-----

---Ground---- ----Signal----- ----Signal-----

----Signal----- ---Ground----- ----Signal-----

----Signal----- ----Signal------ ---Ground-----

----Signal----- ----Signal------ ----Signal-----

TM

External Use 14

7

Twelve (12) ----Sig/Pwr----

Layer Board - ----Ground----

----Sig/Gnd----

-----Power-----

----Ground-----

----Sig/Pwr----

----Sig/Gnd----

----Ground-----

-----Power-----

----Sig/Gnd----

----Ground-----

----Sig/Pwr-----

When 2 or more sets of

Power/Ground planes are

needed, higher layer

count becomes the norm!

Higher layer count boards

also afford opportunity for

great impedance control

and high quality SI.

TM

External Use 14

8

• Containing Fields is critical for Noise / EMI control.

− Controlling return path of Transmission Lines is one key to field containment.

• Low inductance is critical for Noise / EMI control.

− Proximity is the key to low inductance.

• Constant Impedance and timing control in lines are keys to good Signal Integrity.

• Series termination is best, whenever possible.

• High capacitance, low inductance planes are key to low power bus SSN, at high frequencies.

• Proper board stack is critical for all noise issues.

TM

© 2014 Freescale Semiconductor, Inc. | External Use

www.Freescale.com

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