fsm examples. odd parity checker design a circuit that detects whether there are an odd number of 1s...
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FSM examples
Odd Parity Checker
Design a circuit that detects whether there are an odd number of 1s in an input bit stream. Assume that the rate of inputs is 1 every clock cycle.
We have input bit streamNext State will depend on current state as well as the
current input
Odd Parity Checker- State Graph
S0 S1
in=1
in=1
in=0
in=0
Odd Parity Checker- State Table
Present State
Input Next State Output
0 0 0 0
0 1 1 0
1 0 1 1
1 1 0 1
Even number of ones = State S0 = 1’b0Odd Number of Ones = State S1 = 1’b1
Odd Parity Checker – Next State Logic
0
0
1
1
inPresent State 0 1
1
0
Odd Parity Checker - Circuit
in
clk
DQ
Odd Parity Checker – Verilog Code
module odd_parity( in, clk, reset, Out);
input in, clk, reset;
output Out;
reg state, next_state;
wire Out;
parameter S0 = 1’b0,
S1 = 1’b1;
Odd Parity Checker – Verilog Code
// Next State Logicalways @ (in or state or reset)begin
if( reset ==0) next_state =S0;elsebegin case(state)
S0: beginif(in==1) next_state = S1;else next_state = S0;
endS1: begin
if(in ==1) next_state =S0;else next_state = S1;
end endcaseend
end
Odd Parity Checker – Verilog Code
// State Registeralways @ (posedge clk or negedge reset)begin
if(reset==0) state <=S0;else state <= next_state;
end
// Output Logicassign Out = state;
State Machine Example
S0
S1
S2
S3
X=1
X=0
X=0
X=1
X=0
X=1X=0
X=1
State Machine Example – State Table
Q0 Q1 X N0 N1
0 0 0 0 0
0 0 1 0 1
0 1 0 1 0
0 1 1 1 1
1 0 0 1 0
1 0 1 1 1
1 1 0 0 0
1 1 1 1 1
State Machine Example – Circuit Realisation
0 1 0 1
0 1 1 1
00 01 11 10
0
1
Q0 Q1x
N0
N1
0 0 0 0
1 1 1 1
Q0 Q1x 10110100
0
1
N1 = x
State Machine Example – Verilog Code
module state_machine(x, clk, reset, Out);input x, clk, reset;output[1:0] Out;
reg[1:0] state, next_state;wire[1:0] Out;
parameter S0 = 2’b00,S1 = 2’b01,S2 = 2’b10,S3 = 2’b11;
State Machine Example – Verilog Code// Next State Logic
always @ (x or state or reset)
begin
if(reset ==0) next_state =S0;
else
begin
case(state)
S0: begin
if(x==0) next_state = S0;
else next_state = S1;
end
S1: begin
if(x==0) next_state = S2;
else next_state = S3;
end
S2: begin
if(x==0) next_state = S2;
else next_state = S3;
end
S3: begin
if(x==0) next_state = S0;
else next_state = S3;
end
endcase
end
end
State Machine Example – Verilog Code
//State Register Logic
always @ (posedge clk or negedge reset)
begin
if(reset == 0) state <= S0;
else state <= next_state;
end
//Output Logic
assign Out = state;