frequency response of amplifiers and 3-db bandwidth

8/9/2019 Frequency Response of Amplifiers and 3-Db Bandwidth

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Ching-Yuan Yang

National Chung-Hsing UniversityDepartment of Electrical Engineering

Frequency Response of Amplifiers

類比電路設計(3349) - 2004

6-1 Ching-Yuan Yang / EE, NCHU Analog-Circuit Design

Overview

Reading

B. Razavi Chapter 6.

Introduction

In this lecture, we study the response of single-stage and differential

amplifiers in the frequency domain. Following a review of basic concepts, we

analyze the high-frequency behavior of common-source and common-gate

stages and source followers. Next, we deal with cascode and differential

amplifiers. Finally, we consider the effect of active current mirrors on the

frequency response of differential pairs.


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Miller effect

Application of Miller effect to a floating impedance

=−

=−

2

1

Z

V

Z

V V

Z

V

Z

V V

Y X Y

X Y X

That is,

−

=

−=

Y

X

X

Y

V

V

Z Z

V

V

Z Z

1

1

2

1


The overall transfer function can be written as

We may say “each node in the circuit contributes one pole to the transfer function.”

The pole is determined by the total capacitance seen from each node to ground

multiplied by the total resistance seen at the node to ground.

In general, the transfer function is given as

where each pole with one node of the circuit, i.e., , where τ j is the productof the capacitance and resistance seen at node j to ground.

Association of poles with nodes

( )s C R s C R

A s C R

A s V V

P N in S in

out

21

21

11

11 +⋅

+⋅

+=

( )

j

j v

j

j

j in

out

s A

s

A s

V

V

ω ω +

∏=+

∏=1

1

1

1−= j j τ ω

Cascade of amplifiers


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Common-source stage

High-frequency model of a CS stage

( Miller multiplication)

(Assume λ = 0 and M 1 operates in saturation)

At the input node, the total capacitance seen

from X to ground is equal to

C in = C GS + (1 − A v )C GD ,

where A v = − g m R D .

The input pole is( )[ ]GD D m GS S

in C R g C R ++

=1

1ω

At the output node, the total capacitance seen to ground is equal to

C out = C DB + (1 − A v −1)C GD ≈ C DB + C GD

The input pole is

( )GD DB D out C C R +=

1

ω


Common-source stage (cont’d)

Model for calculation of output impedance

(If R S is relative large, the effect of R S is neglected.)

The output pole:

where

Thus, the output pole is roughly equal to

Finally, we surmise that the transfer function is

⋅

+=

1

1||

1

m GD

GS GD

eq

X g C

C C

s C Z

GS GD

GS GD eq

C C

C C C

+=

( )DB eq m GD

GS GD D

out

C C g C

C C R +

⋅

+=

1

1

1ω

( )

+

+

−=

out in

D m

in

out

s s

R g s

V

V

ω ω 11


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Equivalent circuit of CS stage

( ) ( )

( ) ( )[ ] 112 ++++++−

=⇒s C C R C R C R g R s R R

R g s C s

V

V

DB GD D GS S GD D m S D S

D m GD

in

out

ξ

where ξ = C GS C GD + C GS C DB + C GD C DB .

Note the transfer function is of second order even through the circuit contains three

capacitors. While the denominator appears rather complicated, it can yield intuitive

expressions for the two poles, ω p 1 and ω p 2, if we assume |ω p 1| (1 + g m R D )C GD + R D (C GD + C DB )/R S ,

then ( ) ( ) out DB GD D DB GS GD GS D S GS S

p C C R C C C C R R

C R ω ω =

+=

+≈

12


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Feedforward path through C GD

The transfer function exhibits a zero given by ω z = +g m /C GD . Located in

the right half plane, the zero arises from direct coupling of the input to the

output through C GD at very high frequency. Note that a zero in the righthalf plane introduces stability issues in feedback amplifiers



Calculation of the zero in a CS stage

Zero:

For a finite V in , this means that V out (s z ) = 0 and hence the output can

be shorted to ground at the frequency with no current. Therefore, the

currents through C GD and M 1 are equal and opposite:

V 1C GD s z = g m V 1.

That is , s z = +g m /C GD .

( ) 0== z in

out

s s s

V

V


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Input impedance

At high frequency, the effect of the output node must be

taken into account.

hence

( )

( )( )s C R R g s C

s C C R

I

V Z

V s C

I

s C R

R V g I

DB D D m GD

DB GD D

X

X X

X

GD

X

DB D

D X m X

++++==⇒

=++

−

1

1

1

s C Z Z

GS

X in

1=

At frequencies where |R D (C GD + C DB )s |


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Source followers (cont’d)

Input impedance

C GD is ignored, we have

s C g s C g

s C I V Z

s C g s C

I g I

s C

I V

L mb GS

m

GS X

X in

L mb GS

X m X

GS

X X

+

++==∴

++=

111

11

At relative low frequencies, g mb >> |C L s | and

indicating that the equivalent input capacitance is equal to C GS g mb / (g m + g mb ).

By Miller approximation: The low-frequency gain A v = g m / (g m + g mb )

Thus, C eq = C GS (1 − A v ) = C GS g mb / (g m + g mb ), and

mb GS

mb m

mb mb mb

m

GS

in g

s C g g

g g g

g

s C Z

1111

1+

+

=+

+≈

mb m

mb GS GD total in

g g

g C C C

++=,

At high-frequencies, g mb 1

S

m

R g

<1


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Source followers (cont’d)

Equivalent output impedance of a source follower

If Z 1 = Z out , find R 1, R 2 and L :

Take R 2 = 1/g m , R 1 = R S − 1/g m , then

That is, the dependence of L upon R S implies that if a source follower is driven by alarge resistance, then it exhibits substantial inductive behavior.

s C g g

R s C

g Z

GS m

m S GS

m

out +

−

=−

1

1

−=⇒

+=

−

+−

=−

⇒

m

S

m

GS

m

S

m

GS

m

S

m

out

g R

g

C L

Ls R

g R

g

s C g

R g

Z

1

11

1

1

1

1

1

1

1


Common-gate stage

CG stage at high frequencies

Input impedance , where

Since Z in now depends on Z L , it is difficult to associate a pole with the input node.

1

1−

+=

mb m

S S in g g

R C ω , where C S = C GS + C SB

ω out = ( R D C D )−1, where C D = C DG + C DB

At low frequency,

Thus,

An important property of CG stage is that it exhibits no Miller multiplication of

capacitances, potentially achieving a wide band.

( )( ) S mb m

D mb m v

R g g

R g g A

+++

=1

( ) ( )( )

( )s C R s R g g

C R g g

R g g

s s A s

V

V

D D

S mb m

S S mb m

D mb m

out in

v

in

out

+

++

+++

+=

+

+

⋅=

− 11

1

111

1

1ω ω

( ) mb m o mb m L

in g g r g g

Z Z

++

+≈

1

s C R Z

D

D L

1=


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Common-gate stage (cont’d)

CG stage

Transfer function:

The gain at low frequencies is equal to 1 + g m r o .

Input impedance:

As C L or s increases, Z in approaches

1/(g m + g mb ) and hence the input pole

can be defined as

( )

( )

( )( )[ ] 11

12

11

11

++++++=⇒

=−−−

−=++−

s R C r g R C C r s R C C r

r g s

V

V

V V V g s C V r

V V R s C V s C V

S L o m S in L o S in L o

o m

in

out

out m L out o

in S in L out

( ) o mb m L mb m in

r g g s C g g Z

+⋅+

+=

111

in

mb m

S

in p

C g g

R

+

=1

1,ω


Cascode stage

High-frequency model of a cascode stage

Cascode stage = CS stage (input impedance) + CG stage (suppressing the millereffect)

Gain:

Node A:

Node X:

Node Y:

In actual design, ω p ,X is typically chosen to be farther from the origin than the other

two. This choice plays an important role in the stability of op amps.

mb m

m

A

X

g g

g

V

V

+−≈

2

1

+

++

=

1

2

11

,

1

1

GD

mb m

m GS S

A p

C

g g

g C R

ω

2211

1

22

22,

1 GS SB DB GD m

mb m

mb m X p

C C C C g

g g

g g

+++

++

+=ω

( )22,

1

GD L DB D

Y p C C C R ++

=ω


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Cascode stage (cont’d)

Simplified model of a cascode stage with a current source

V X = −(V out C Y s + I in ) / (C X s )

I D 2 = −g m V GS 2 = g m 2V X = − g m 2 (V out C Y s + I in ) / (C X s )

for g m 2r o 2 >> 1 and g m 2r o 2C Y /C X >> 1 (i.e., C Y > C X ),

hence

We can find that the pole at node X is given by g m 2 / C X .Neglecting C GD 1 and C Y , we have Z out = (1 + g m r o 2)Z X + r o 2, where Z X = r o 1||(C X s )

−1.

( ) ( )

( ) s r C C

C r g s C

r g

I

V

V s C I s C V s C V s C

g

I s C V r

o Y

X

Y o m

X

o m

in

out

out X

in Y out Y out X

m

in Y out o

222

22

2

2

11

11

1

+++⋅

+−=⇒

=+−

++−

s C g C

C s C

g

I

V

Y m

X

Y X

m

in

out

+−≈

2

2 1

s C g s C C

g g

I

V

V

I

V

V

X m X Y

m m

in

out

in

in

in

out

+−≈=

/

1

2

21


Differential pair

Differential pair

Equivalent circuit for common-mode input

If the output pole is much farther from the origin than

is the pole at node P , the common-mode rejection of

the circuit degrades considerably at high frequencies.

( ) 11

1

321

,

+

+

∆

−=

s C r g g

s C R g

A

P

o m m

L

D m

CM v

Half-circuit equivalent


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Differential pair (cont’d)

Effect of high-frequency supply noise in differential pair

If the supply voltage contains high-frequency noise and the circuit exhibits

mismatches, the resulting common-mode distance at node P leads to a differential

noise component at the output.

A trade-off between voltage headroom and CMRR : To minimize the headroom

consumed by M 3

, its width is maximized, introducing substantial capacitance at the

sources of M 1 and M 2 and degrading the high-frequency CMRR . The issue

becomes more serious at low supply voltages.



Differential pair with current-source loads

Node G is an ac ground.

The output pole is given by , the dominant pole.( ) L o o

out C r r 31

1=ω


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In addition, there is a zero with a

magnitude of in the left half

plane. The appearance of such a zero

is that the circuit consists of a “slowpath” (M 1, M 3 and M 4) in parallel witha “fast path” (M 1 and M 2).

Representing the two paths, we have

That is, the system exhibits a zero at

2ω p 2.

( )( )( )

( )( )2120

1

0

21

0

/1/1

/2

/1/1/1

p p

p

p p p in

out

s s

s A

s

A

s s

A

V

V

ω ω

ω

ω ω ω

++

+=

++

++=

E

mP

C

g 2



Determine the zero (method)

For zero frequency, I L = 0 and I D 4 = I X .

We have

I D 4 = −g mP V E I X = V E (g mP + C E s )

Thus, −g mP V E = V E (g mP + C E s )

E

mP z

C

g 2−=ω

I L

I D4


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Small-signal analysis applies when transistors can be adequately characterized by their

operating points and small linear changes about the points.

The use of this technique has led to application of frequency-domain techniques to the

analysis of the linear equivalent circuits derived from small-signal models.

The transfer function of analog circuits to be discussed can be written in rational form

with real-valued coefficients, that is as a ratio of polynomials in Laplace Transformvariable s,


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3


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4.1.2 First order circuits

It is a first-order low-pass transfer function.

It arises naturally when a resistance and capacitance are combined.

It is often used as a simple model of more complex circuits, such as OpAmp.

4


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Step response of first order circuitsAnother common means of characterizing linear circuits is to excite the with step inputs

(such a square waveform).

5


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6


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4.1.3 second order low-pass H(s) with real

poles

Here, w0 is the resonant or pole frequency and Q the quality factor, K the DC gain of H(s).

Equating yields


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wp1, wp2 are widely-spaced real poles

The step response consists of two first-order terms, and when wp1 1/wp2, the first term dominates.

8


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Chapter 4 Figure 04

4.1.4 Bode plot

9


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4.1.5 Second-order low-pass H(s) with

complex poles

Recall

Subt. In

10


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4.1.5 Second-order low-pass H(s) with

complex poles1. The step response in this case has sinusoidal term whose envelope

exponentially decays with a time constant equal to the inverse of real parts of

poles, 1/wr=2Q/w0.

2. A system with high Q factor will have oscillation and ringing for some time. The

oscillation frequency is determined by the imaginary parts of the poles.3. In summary, when Q0,5,

there are overshoot and ringing.

Chapter 4 Figure 09

Chapter 4 Figure 10

t

11


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4.2. Frequency response of elementary

circuitsSmall-signal analysis is implicitly assumed as only linear circuits can have well-defined

frequency response.

The procedure for small-signal analysis remains the same as that in Chapter 3 for

single-stage amplifiers, however parasitic capacitance are now included.

12


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Chapter 4 Figure 12

Chapter 4 Figure 11

4.2.1 High frequency small-signal model

13


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Chapter 4 Figure 13

4.2.2 Common-source amplfier

Chapter 4 Figure 14

Note: assumed that Q1, Q2 are in active mode.

14


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If

15


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One more reason why analog design is tough.

16


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Chapter 4 Figure 15

4.2.3 Miller effect

17


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Chapter 4 Figure 17

18


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Chapter 4 Figure 18

Miller effect applied to CS amplifier

Chapter 4 Figure 14

19

Miller effect allows one to quickly estimate the 3dB bandwidth in many cases.


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4.2.4 Zero-value time constant methodExcept Miller effect, the most common and powerful technique for frequency response

analysis of complex circuits is the zero-value time constant analysis method.

It is very powerful in estimating a circuit’s 3dB bandwidth with minimal complication and

also in determine which nodes are most important.

Generally, the approach is to calculate a time-constant for each capacitor in the circuit by

assuming all other capacitors are zero, then sum all time constants to estimate the 3dB

bandwidth.

Detailed procedure:

20


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Example 4.9 (page 174)

The same as obtained previously21

Chapter 4 Figure 14


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Chapter 4 Figure 13

Design example 4.11 (page 177)

In this example, the load capacitance is modest and source resistance is high, so C gd1 may

become a major limitation of the bandwidth. This means that W1 should be small.

So, given a current, Veff1 has to be relatively large: choose Veff1 to be 0.3V

Then suppose L1rds1 so R2=rds1 and A0=-gm1rds1

22


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Then solve L1 to be

Then note that increasing drain current of Q1 while keeping Veff1=0.3V will increase gm1

and reduce rds1 roughly in proportion, which results in about the same gain, but a smaller

R2 is achieved which increase 3db bandwidth. So, bandwidth is maximized by maximizing

he drain current of Q1.

Then, we can compute the required gate width

To ensure L2>>L1, we can take L2=3L1=0.72μm

Then, we can arbitrarily and conveniently set W2=3W1

Finally, Q3 is sized to provide the desired current mirror ratio

Then, need to make sure that all transistors are in active region 23


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Chapter 4 Figure 13


In this example, the load capacitance is very large and source resistance is small, so C 2

may become a major limitation of the bandwidth, so

24


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Chapter 4 Figure 13


25

rds=2rds1


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The above two design examples illustrate the manual analysis to provide an initial design

solution, which thereafter needs to be refined iteratively using simulation. A number of

challenges here:

1. there is no guarantee that the initial solution is valid or good;2. the refinement may take many many iterations until a good design is achieved;

3. at each iteration, what are not working or good in the circuit, what parameters to

modify, and how to modify them requires in depth understanding of analog circuits.

What about those cases when it is hard to decide which capacitance dominates?

Experience counts here, after you had many designs and were aware of the biasing

conditions, capacitance conditions?

The time domain response of common-source amplifier? (two widely spaced poles)

26

Comments


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Chapter 4 Figure 20

4.2.6 Common-gate amplifier

Chapter 3 Figure 09

27


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Chapter 4 Figure 21

We estimate the time constant associated with Cgs (note that Cgs is connected between

source and ground therefore may need to include Csb).

Superior 3dB bandwidth, but input impedance is too small.

28


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Compared to CS amplifier, CG amplifier has much better 3dB bandwidth, but much

smaller input impedance.

To achieve a good tradeoff, we can combine a CG amplifier with a CS amplifier.

4.3 Cascode gain stage

Chapter 4 Figure 22

Telescopic Folded-cascode

rin2

29


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Chapter 4 Figure 23

Small-signal model for the cascode

Cout=Cgd2+Cdb2+ CL+Cbias

Cs2=Cdb1+Csb2+Cgs2

Please derive Rout

Using zero-value time constant method

rin2

The total resistance seen at the drain of Q1 is

30

See Slide 21

See slides 30 (Ch3)

Miller effect


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Chapter 4 Figure 24

31

On the Miller effect on Cgd1


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32

Example 4.13, 4.14 (page 184-185)

Recall that a large gain of the cascode amplifier requires the Ibias to have an

output resistance on the order of In this case, and especially when

there is also a large load capacitance CL, the output time constant

would dominate.

This approximation is valid since Rs is the same order as rds


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Chapter 4 Figure 26

33

4.3 Source follower amplifierThe SF amplifier may have complex poles and therefore ringing and overshoot may

happen for a pulse input.

Norton equivalent circuit

Q1


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Chapter 4 Figure 27

34

Cs=CL+Csb1

Chapter 4 Figure 28


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35

Next we find the admittance Yg looking into the gate of Q1 (but not

including Cgd1 as it is already combined into Cin’).

Recall Q


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Chapter 4 Figure 32

37

4.5 Differential pairWhen using T model for differential pair, the analysis may be simpler compared to the

hybird-pi model.

CL

Vs


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38

4.5.2 Symmetric differential pairIn the small-signal model, half circuit is analyzed to allow simpler analysis.

Also note that the Vs node is small-signal ground due to symmetry, so Csb1 and Csb2 can

be neglected.

The half circuit corresponds to that of a CS amplifier, so the 3dB bandwidth is either

or 1/[R2 * (Cgd1 + Cdb1 + CL)]

Which one is the 3dB bandwidth depends on the CL.

Where R2 = RD||rds1


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39

Active loaded differential pairAgain note that Vs is at small-signal ground, so half circuit can be used for analysis.

Again the load capacitor will determine which one is the 3dB bandwidth.

]))//(1[(2

1

])[//(2

1

11311

2

313131

1

gs gd oom s

b

dbdb gd gd Loo

b

C C r r g R f

C C C C C r r f

Vs


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Chapter 3 Figure 19

Capacitance at input node of the current mirror:

Capacitance at the output node:

Note that Q1 will conduct an current of gmVid/2

flowing through Q3 (the parallel of 1/gm3 and Cm),

where we neglected the effect of rds1 and rds2, so

Va

From Miller effect

Current-mirror loaded differential pair


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41



CL

Cm

RL

-Ix4

-Ix4

Va

Va

Io

-Ix4-Ix3


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42



We can them multiply Gm with the total load

impedance to obtain the voltage Vo

CL

Cm

RL

Io

Compared to the fully differential version, the current-mirror differential amplifier

adds one more pole to the transfer function, therefore may significantly affect the

frequency response.


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43

Chapter 4 Figure 37

If output load capacitance is dominated, then the following simple model can be used.

Simplified small-signal model for


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Chapter 4 Figure 34

44


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Chapter 4 Figure 35

45


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Chapter 4 Figure 36

46


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Ching-Yuan Yang

National Chung-Hsing UniversityDepartment of Electrical Engineering

Stability and Frequency Compensation

類比電路設計(3349) - 2004


Overview

Reading

B. Razavi Chapter 10.

Introduction

In this lecture, we deal with the stability and frequency compensation of

linear feedback systems to the extent necessary to understand design

issues of analog feedback circuits. Beginning with a review of stability

criteria and the concept of phase margin, we study frequency compensation,introducing various techniques suited to different op amp topologies. We

also analyze the impact of frequency compensation on the slew rate of two-

stage op amps.


60/75


Basic negative-feedback system

General considerations

Close-loop transfer function:

if β H (s = j ω 1) = −1, the gain goes to infinity,

and the circuit can amplify is own noise untilit eventually begins to oscillate at frequency

ω 1.

Barkhausen’s Criteria:

| β H (s = j ω 1)| = 1∠ β H (s = j ω 1) = −180o .

The total phase shift around the loop at ω 1 is 360o because negative

feedback itself introduces 180o of phase shift. The 360o phase shift isnecessary for oscillation since the feedback must add in phase to theoriginal noise to allow oscillation buildup. By the same token, a loop

gain of unity (or greater) is also required to enable growth of theoscillation amplitude.

( ))(1

)(

s H

s H s

X

Y

β +=


Bode diagram of loop gain

A negative feedback system may oscillate at ω 1 if

(1) the phase shift around the loop at this frequency is so much that the

feedback becomes positive.

(2) the loop gain is still enough to allow signal buildup.

Unstable system Stable system


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Time-domain response

Root locus: Pole frequency sP = j ω P + σ P

σ P > 0, unstable with growing

amplitude

σ P = 0, unstable with constant-

amplitude oscillation

σ P < 0, stable

a

b

c


Bode plots of one-pole system

Assuming H (s) = A0/(1 + s/ω 0), β is less than or equal to unity and doesnot depend on the frequency, we have

Bode plots of loop gain: Root locus: sP = −ω 0(1 + β A0)

A single pole cannot contribute a

phase shift greater than 90o and

the system is unconditionally

stable for all non-negative

valuesof β .

( )

( )00

0

0

11

1

)(1

)(

A

s

A

A

s H

s H s

X

Y

β ω

β

β

++

+=

+=

20dB/dec

10ω00.1ω0


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Bodes plots of two-pole system

Assuming the open-loop transfer function

Bode plots of loop gain:

The system is stable because | β H | drops to below

unity at a frequency for which ∠ β H < −180o.To reduce the amount of feedback, we decrease

β , obtaining the gray magnitude plot in the figure.

For a logarithmic vertical axis, a change in β

translates the magnitude plot vertically. Note that

the phase plot does not change.

The stability is obtained at the cost of weaker

feedback.

+

+

=

21

0

11

)(

p p

s s

A s H

ω ω


Bodes plots of three-pole system

Assuming the open-loop transfer function

Bode plots of loop gain:

If the feedback factor β decreases, the

circuit becomes more stable because the

gain crossover moves toward the origin

while the phase crossover remains

constant.

+

+

+

=

321

0

111

)(

p p p

s s s

A s H

ω ω ω


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Phase margin

Close-loop frequency and time response

Small margin Large margin


Phase margin (cont’d)

Phase margin (PM) is defined as

PM = 180o + ∠ β H (ω = ω 1)

where ω 1 is the gain crossover frequency.

Example

A two-pole feedback system is designed such that | β H (ω = ω P 2)| = 1 and

| ω P 1|


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How much phase margin is adequate?

For PM = 45o, at the gain crossover frequency ∠ β H (ω 1) = −135o and

| β H (ω 1)| = 1, yielding

It follows that

The frequency response of the feedback

system suffers from a 30% peak at ω = ω 1.

Close-loop frequency response for 45o

phase margin:

( ) j j H

j

j H

X

Y

71.029.0

)(

135exp11

)( 11

−=

°−⋅+=

ω ω

β β

3.1

71.029.0

11≈

−

⋅=

j X

Y


How much phase margin is adequate? (cont’d)

Close-loop time response for 45o, 60o, and 90o phase margin:

For PM = 60o, Y ( j ω 1)/ X ( j ω 1) = 1/ β , suggesting a negligible frequency peaking.

This typically means that the step response of the feedback system exhibitslittle ringing, providing a fast settling. For greater phase margins, the systemis more stable but the time response slows down. Thus, PM = 60o is typicallyconsidered the optimum value.

The concept of phase margin is well-suited to the design of circuits thatprocess small signals. In practice, the large-signal step response offeedback amplifiers does not follow the illustration of the above figure. Forlarge-signal applications, time-domain simulations of the close-loop systemprove more relevant and useful than small-signal ac computations of theopen-loop amplifier.


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How much phase margin is adequate? (cont’d)

Example:

Unity-gain buffer: PM ≈ 65o, unity-gain frequency = 150 MHz.However, the large-signal step response suffers from significant ringing.

The large-signal step response of feedback amplifiers is not only due toslewing but also because of the nonlinear behavior resulting from largeexcursions in the bias voltages and currents of the amplifier. Suchexcursions in fact cause the pole and zero frequencies to vary during thetransient, leading to a complicated time response. Thus, for large-signalapplications, time-domain simulations of the close-loop system prove more

relevant and useful than small-signal ac computations of the open-loopamplifier.


Frequency compensation

Typical op amp circuits contain many poles. For this reason, op amps must

usually be “compensated,” that is, the open-loop transfer function must be

modified such that the closed-loop circuit is stable and the time response is

well-behaved.

Stability can be achieved by minimizing the

overall phase shift, thus pushing the phase

crossover out . Moving PX out

Discussion :

This approach requires that we attempt

to minimize the number of poles in the

signal path by proper design.

Since each additional stage contributes

at least one pole, this means the number

of stages must be minimized, a remedy

that yields low voltage gain and/or limited

output swings.


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Frequency compensation (cont’d)

Stability can be achieved by dropping Moving GX in

the gain thereby pushing the gain

crossover in.

Discussion:

This approach retains the low

frequency gain and the output

swings but it reduces the

bandwidth by forcing the gain

to fall at lower frequencies.


Telescopic op amp with single-ended output

Determine the poles of the circuit:

We identify a number of poles in the signal paths:

path 1 contains a high-frequency pole at the source

of M 3, a mirror pole at node A, and another

high-frequency pole at the source of M 7, whereas

path 2 contains a high-frequency pole at the source

of M 4. The two paths share a pole at the output.

Dominant pole: the closest to the origin.

ω p,out = 1/(R out C L), usually sets the open-loop3-dB bandwidth.

Nondominant poles:

ω p, A = g m5/C A, the closest pole to the origin after ω p,out . Pole locations:

where C A = C GS5 + C GS6 + C DB5 + 2C GD6 + C DB3 + C GD3.

ω p,N = g m7/C N , ω p, X = g m3/C X = g m4/C Y = ω p,Y .

Since g m = 2I D/|V GS − V TH |, if M 4 and M 7 aredesigned to have the same overdrive, they exhibit

the same transconductance. From square-law characteristics, we have

W 4/W 7 = µ p/µ n ≈ 1/3. Thus, nodes N and X (Y ) see roughly equal small-signalresistances but node N suffers from much more capacitance.

(mirror pole)


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Telescopic op amp with single-ended output (cont’d)

Bode plots of loop gain for op amp: using β = 1 for the worst case.

The mirror pole ω p, A typically limits the phase margin because its phase

contribution occurs at lower frequencies than that other nondominant

poles.


Telescopic op amp with single-ended output (cont’d)

Translating the dominant pole toward origin to compensate the op amp:

Assuming ω p, A > 10ω p,out , we must force

the loop gain crossover point moves

toward the origin. We can simply lower

the frequency of the dominant pole

(ω p,out ) by increasing the load capacitance.

The key point is that the phase contributionof the dominant pole in the vicinity of the

gain or phase crossover points is close to

90o and relatively independent of the

location of the pole. That is, translating

the dominant pole toward the origin affects

the magnitude plot but not the critical part

of the phase plot.


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Compensation of two-stage op amps

We identify three poles at X (or Y ), E (or F ) and A(or B).

A pole at X (or Y ) lies at relatively high frequencies. Since the small-signalresistance seen at E is quite high, even the capacitances of M 3, M 5 and M 9can create a pole relatively close to the origin. At node A, the small-signalresistance is lower but the value of C L may be quite high. Consequently, thecircuit exhibits two dominant poles.

One of the dominant poles must be moved toward the origin so as to placethe gain crossover well below the phase crossover. If the magnitude of ω p,E is to be reduced, the available bandwidth is limited to approximately ω p, A, a

low value. Furthermore, this required dominant pole translates to a verylarge compensation capacitor.


Miller compensation of a two-stage op amp

In a two-stage amp as shown in Fig.(a), the first stage exhibits a high output

impedance and the second stage provides a moderate gain, therebyproviding a suitable environment for Miller multiplication of capacitors.

In Fig.(b), we create a large capacitance at E , the pole is

As a result, a low-frequency pole can be established with a moderate

capacitor value, saving considerable chip area.

In addition to lowering the required capacitor value, Miller compensation

entails a very important property: it moves the output pole away from the

origin. ( pole splitting )

( )[ ]C v E out E p

C AC R 21,

1

1

++=ω


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Miller compensation of a two-stage op amp (cont’d)

Pole splitting as a result of Miller compensation.

Discussion

Two poles: (based on the assumption |ω p,1| > C E , ω p,2 ≈ g m9/(C E + C L).

Typically C E


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Addition of R z to move the right hand plane zero.

The zero is given by .If , then ω z ≤ 0.

We may move the zero well into the left plane so as to cancel the firstnondominant pole. That is

, because C E


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Method of defining g m9 with respect to R S.

Goal: ⋅⋅⋅⋅⋅⋅⋅⋅ (A)

The technique incorporates M b1-M b4

along with R S to generate

Thus,

Proper ratioing of R Z and R S therefore

ensures (A) is valid even with temperature

and process variations

C m

C L z

C g

C C R

9

+=

2−∝ S b R I

11199

−∝∝∝ S D Dm R I I g


Effect of increased load capacitance on step response

In one-stage op amps, a higher load capacitance brings the dominant polecloser to the origin, improving the phase margin (albeit making the feedback

system more overdamped).

In two-stage op amps, since Miller compensation establishes the dominant

pole at the output of the first stage, a higher load capacitance presented to

the second stage moves the second pole toward the origin, degrading the

phase margin.

Illustrated in the figure is the step response of a unity-gain feedback

amplifier, suggesting that the response approaches an oscillatory behavior if

the load capacitance seen by the two-stage op amp increases.

One-stage op amps: Two-stage op amps:


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Slewing in two-stage op amps

The positive slew rate equals I SS /C C . During slewing, M 5 must provide two

currents: I SS and I 1. If M 5 is not wide enough to sustain I SS + I 1 in saturation,

then V X drops significantly, possibly driving M 1 into the triode region.

During negative slew rate, I 1 must support both I SS and I D5. For example,

if I 1 = I SS, then V X rises so as to turn off M 5. If I 1 < I SS, then M 3 enters the

triode region and the slew rate is given by I D3 /C C .

Positive slewing: negative slewing:


Compensation technique using a source follower

Two-stage op amp with right half plane zero due to C C :

Addition of a source follower to remove zero:

Since C GS of M 2 is typically much less than C C , we

expect the right frequencies.

and , then

Assume ω p 1 > 1,

(1 + g m 1g m 2R L R S )C C >> g m 2R L C L , we have

Equivalent circuit :

Source follower

( ) ( )s C R R g V

V s C R V V g L L L m

out L L out m +−

=+=− − 1 1

1111

S

in

C m

out

R

V I

s C g

V V 1

2

1

11 =+

+

−

[ ] 22212

2

21

)1()1(

)(

m L L m C S L m m S m C L L

C m S L m

in

out

g s C R g C R R g g s R g C C R

s C g R R g

V

V

++++++−

=

Zero in the left hand plane

L

m

L L C

g

C R11 →

C S L m

p C R R g 1

1

1≈ω

L

m p

C

g 12 ≈ω and (Note ω p 2: )


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Compensation technique using a CG stage

The primary issue is that the source follower limits the lower end of the

output voltage to V GS 2 + V I 2. In the CG topology, C C and the CG stage M 2convert the output voltage swing to a current, returning the result to the

gate of M 1.

, and , we obtain

Using approximations, and .

222 V

sC

V g V

C

mout −=+ 2211

1V g sC

RV V g m L

L

out m =

++ 22

1 V g R

V I m

S

in +=

( )( )[ ] 2221

221

1 m L LmC C LmS mC L L

S m LS m

in

out

g sC R g C C R g R g sC C R

sC g R R g

I

V

++++++−

=

C S Lm

pC R R g 1

11≈ω

L

mS m p

C g R g 12

2 ≈ω

Equivalent circuit :


Compensation technique using a CG stage (cont’d)

For positive slewing, M 2 and I 1 must support I SS,

requiring I 1 ≥ I SS + I D1. If I 1 is less, then V P drops,

turning M 1 off, and if I 1 < I SS, M 0 and its tail

current source must enter the triode region,

yielding a slew rate equal to I 1/C C .

For negative slewing, I 2 must support both I SS

and I D2. As I SS flows into node P , V P tends to rise,increasing I

D1. Thus, M

1absorbs the current

produced by I 3 through C C , tuning off M 2 and

opposing the increase in V P . We can therefore

consider P a virtual ground node.

For equal positive and negative slew rates, I 3

(and hence I 2) must be as large as I SS, raising the

power dissipation.

Positive slewing:

Negative slewing:


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Alternative method of compensation two-stage op amps

frequency response of amplifiers and 3-db bandwidth

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