FPGA IMPLEMENTATION OF HIGH

SPEED ARITHMETIC UNIT USING VEDIC

MATHEMATICS Mrs. G. Shobana, Assistant Professor, S. RamaLakshmi,J. Lavanya gshobana@mepcoeng.ac.in ramalaxmisubramanian@gmail.com lavanyapandian2013@gmail.com Department of Electronics and Communication Engineering Mepco Schlenk Engineering College (Autonomous), Sivakasi

Abstract – Arithmetic Logic Unit (ALU) is an important

building block of any computing systems. In this paper,

high speed and energy efficient architecture for ALU is

designed by using the concepts of Vedic mathematics. The

arithmetic operations such as addition, subtraction,

multiplication and division are performed using

Vilokanum, Urdhav Triyagbhyam , Paravartya sutras .

The proposed architecture is simulated using Verilog

followed by synthesis using Xilinx ISE 14.1 and is

implemented in Spartan – 6 FPGA .The performance of

the proposed ALU architecture is analyzed and compared

with the already available traditional arithmetic unit in

terms of delay and resource complexity. It is shown that

the proposed architecture is highly efficient in terms of

delay compared to available methods.

I.INTRODUCTION:

Multipliers have been proven to be an

important component while designing microprocessors

and other applications where processing of a signal is in

foreground.Since the processor depends upon on

multiplier,multiplication is the key arithmetic technique

for improving the performance of fast

processor.Therefore,the technologies are looking for a

new algorithm and hardware so as to implement the

obtained operation in much optimized way in the terms

of area and speed.The word “Vedic” is a consequential

of “Vedic” comprising the accumulation of knowledge

at a single platform.Jagadguru Swami Sri Bharati

Krishna Tirthaji in between 1884-1960,implemented the

concept of this ancient methodology that became very

popular to achieve the processing of the data.Vedic

mathematics deals with the various operation of

mathematics like arithmetic algebra,geometry,equation

etc.The use of Vedic mathematics concepts in the

computation algorithm of a processor will reduce the

complexity of execution time,speed,delay,area and

power consumption etc.

The paper starts with an introduction

pertaining to the section I. Thereafter , Section II

literature survey.Section III about the proposed model of

vedic arithmetic unit.Section IV proposes Vedic

methodology used for addition. Section V illustrates

the steps approaching Vedic methodology for

subtraction.SectionVI comprises the design of Vedic

multiplication .Section VII discuss about the Vedic

divider. Finally, obtained results are discussed in next

section.

II. LITERATURE SURVEY:

Based on the Vedic mathematics concepts for

digital signal processing applications,many researchers

have proposed ALUs and other computational

units.From these research, they have proved that

conventional arithmetic computational algorithms are

very robust when compared to proposed arithmetic

computations. Garima Rawat have proposed an ALU

design using vedic mathematics approach.He designed

and analyzed about high speed 8*8 bit multiplier.This

method is different from the conventional method of

employing product of two numbers accomplished by

the process of add and shift.And the proposed method

involves the vertical and crossed multiplication and it

was efficient and fast.[1]. Rahul Nimje have proposed

an ALU design using Vedic mathematics concepts.He

designed and analyzed vedic multiplier using Urdhav

Triyagbhyam sutra.In this method of multiplication,he

eliminate the unwanted multiplications steps with

zeros,by enabling parallel generation of intermediate

product.By this,he achieved high speed power efficient

multiplier[2].

Abhishek Gupta,have prposed an ALU design using

vedic mathematics approach.Every digital domain based

technology was operated only by ALU either partially or

whole. For this we required high speed ALU.The

proposed ALU is able to perform three arithmetic

operations[3].S.P.Pohokar, have proposed an 8 bit ALU

design using vedic mathematics concepts. In this

technique, he reduces the propagation delay in processor

and hardware complexity in terms of area and speed by

eliminating the unwanted multiplication

steps[4].Surabhi Jain, have proposed that VLSI

architecture have higher orders of time and space

complexities. In this he designed binary division

architecture using Nikhilam sutra and Paravartya

sutra[5].

III. SYSTEM DESIGN:

Fig.3.1 Proposed Arithmetic Unit Integration

Fig.3.1 shows the block diagram of the proposed vedic

mathematics based AU design. The two binary inputs

are given and output result is the arithmetic operation i.e

addition,subtraction,multiplication and division. It

contains only one unit called arithmetic unit to perform

arithmetic operations.The addition is carried out using

vilokanam sutra. The subtraction is also carried out

using vilokanam sutra based on 2’s complement

method. The multiplication is carried out using Urdhav

Triyagbhyam sutra. The division is carried out using

Paravartya sutra.

IV. VEDIC ADDITION

Fig4.2 shows the block diagram of 16 bit addition using

vilokanam sutra. Vedic addition is performed using the

Vilokanam Sutra.Vilokanam is the corollary to

Shesanyankena Charamena, the twelfth sutra of Vedic

mathematics. Vilokanam can also be applied to algebra

problems involving simultaneous equations, quadratic

equations, etc., and to resolve certain algebraic

equations into partial fractions.

Eg: Consider two16 bit binary inputs

Fig.4.1Vedic addition example using Vilokanam Sutra

Fig.4.2 Block Diagram of 16 Bit Vedic Adder using Vilokanam Sutra

V. VEDIC SUBTRACTION

Fig 5.1 shows the block diagram of 16 bit subtraction

using vilokanam sutra. This is almost similar to Vedic

adder and only difference is the 2’s complement

method. The 2's complement of a binary number can be

obtained by adding 1 to its 1's complement and proceed

with the Vedic addition method. It involves two

methods.

i) Subtraction of a smaller number from a larger one by

the 2's complement method involves following

steps:

Determine the 2's complement of the smaller

number

Add this to the larger number.

ii) The 2's complement method for subtraction of a

larger number from a smaller one is as follows:

Determine the 2's complement of the larger

number.

Add the 2's complement to the smaller number.

There is no carry.

The result is in 2's complement form and is

negative; to get an answer in true forms take

the 2's complement and change the sign.

Fig.5.1Block Diagram of 16 Bit Vedic Subtraction using

Vilokanam Sutra

VI. VEDIC MULTIPLICATION

Fig.6.1shows the block diagram of 32 bit Vedic

multiplier using Urdhav Triyagbhyam sutra. This sutra

is also called as “vertically and crosswise”

multiplication.The digits on the two ends of the line are

multiplied and the result is added with the previous

carry. And hence the least significant digit of the

number thus obtained acts as one of the result digits and

the rest acts as the carry for the next step. Initially carry

will be taken to as zero. The number of steps taken for

multiplication can be calculated by the formula i.e

(2*N)-1 where N is the number of digits. Here it get

compared with different multipliers such as Booth

multiplier, pipelined multiplier etc. From the analysis

we have conclude that the proposed multiplier takes less

amount of time in terms of delay.

Fig.6.1 Vedic Multiplication method using Urdhav Triyagbhyam

Sutra

Fig.6.2 Block diagram of 32 bi t Vedic multiplier using Urdhav

Triyagbhyam Sutra

VII.VEDIC DIVISION

Fig.7.1. shows the flow chart of 32 bit Vedic divider and

it is implemented using paravartya sutra. Initially the

divisor must be subtracted from the its base number. For

example 89 should be subtracted from 100. If the result

is negative, then we should take 2’s complement of that

number. It should be multiplied with MSB bit of the

dividend. The multiplied answer should write at the next

line of the dividend shifting one bit right. Perform

addition to the 2nd MSB bit. Same operation should be

performed till the last digit of the dividend. In this

manner finally the quotient and remainder should be

obtained. When compared to conventional division, it

takes minimum amount of delay and hardware

complexity is; also less.

Fig.7.1 Flow chart of division using Paravartya Sutra

Eg : 32 bit divided by 16 bit:

Dividend – 1 4 5 6 3 2 7 2, Divisor - 1 2 2 2

Fig.7.2 Vedic division method using Paravartya Sutra

VIII.RESULTS AND DISCUSSIONS

Fig.8.1Simulation results of 16 bit Conventional Arithmetic Unit

Fig.8.2 Simulation results of 16 bit Vedic Arithmetic Unit

The figure shows the simulation of Conventional and

Vedic ALU, in which Out1 is the result of addition, Out

2 is the result of subtraction, Out 3 is the result of

multiplication and Out 4,Out 5 is the result of Quotient

and Remainder of division.

Table 1 Comparison of different Arithmetic operation

Table 1 displays the comparison of synthesis results of

various arithmetic operations in terms of delay(in

nanoseconds). To show the efficiency of proposed vedic

ALU at 16 bit level, it has been compared with

conventional ALU. For the comparison purpose some

standard papers have been used. Addition using ripple

carry scheme is less efficient when compared to

applying vedic addition using vilokanam sutra in terms

of delay and area. Subtraction using ripple carry scheme

is less efficient when compared to applying vedic

subtraction using vilokanam sutra in terms of delay and

area. The efficiency of proposed vedic multiplier at 16

bit level has been compared with other popular

multiplier structures and vedic multiplier showed lowest

path delays.The result of device utilization and delay as

the restoringdivision method shows a larger delay as

compared to the proposed divider & the percentage of

device utilization in restoring division method is quite

high from Vedic divider.

Table 2 Comparison result of 16 bit ALU

Table 2 displays the comparison of synthesis results of

conventional ALU with proposed Vedic ALU. From

these analysis, proposed ALU is more efficient in terms

of delay and area.

IX. CONCLUSION AND FUTURE WORK

In this paper, less complex and high speed

architecture for ALU has been proposed , simulated

using Modelsim and implemented in Spartan -6 FPGA

device in Xilinx PlanAhead tool. The operations are

made simple by using Vedic sutras. In future, ALU

capable of performing floating point operations are also

implemented and a total hardware of ALU capable of

performing both fixed and floating point computations

could be synthesized and implemented.

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