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FPGA-Based Design and Implementation of the Greatest Common Divisor using Presented by: Ibrahim Hazmi Supervised by: Dr. Mihai Sim

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Page 1: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

FPGA-Based Design and Implementation of the Greatest Common Divisor using

Presented by: Ibrahim Hazmi Supervised by: Dr. Mihai Sim

Page 2: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 20142

Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design such circuit and examine the area-speed tradeoff in order to get the result at reasonable speed with optimal utilization of the FPGA resources. So, the design came in different Levels:

High Behavioural Level ASM Behavioural Level Direct Structural Level Optimized Structural Level

Design Problem & Motives

Page 3: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 20143

Overview of Xilinx Spartan6 FPGA Overview of the GCD

Euclidean Algorithm Behavioural Level Design

High Level (While/For Loop) ASM Level (ASM —> FSM)

Structural Level Design Direct Structural (Data-path + FSM) Optimized Structural Design (SAD)

Conclusion Summary & Future Work

Outline

Page 4: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 20144

Xilinx Spartan6 (Overview)PlanAhead

XC6SLX25

Page 5: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 20144

Xilinx Spartan6 (Overview)PlanAhead

XC6SLX25

Page 6: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 20144

Xilinx Spartan6 (Overview)PlanAhead

Device LogicCells

CLB DSP SlicesSlices FFs Max RAM LUT6

XC6SLX25 24,051 3,758 30,046 229 15,032 38

XC6SLX25

Page 7: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 20145

Greatest Common Divisor (GCD) Greatest Common Factors (GCF) Greatest Common Measure (GCM) Highest Common Divisor (HCD) Highest Common Factor (HCF)

What is GCD ? 36, 54

Euclidean Algorithm ?

Actually, It has many names:

Page 8: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 20146

36, 54

A B

N

Y

Euclidean Algorithm

Page 9: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 20146

36, 54

A B

N

Y

Euclidean AlgorithmA B

Page 10: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 20147

36, 54

A B

Euclidean Algorithm

Page 11: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 20148

36, 54

A B

36 54

Euclidean Algorithm

Page 12: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 20149

36, 54

A B

A = 36

Euclidean Algorithm

36 54

Page 13: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 20149

36, 54

A B

A = 36

Euclidean Algorithm

36 54

B = 18

Page 14: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 201410

36, 54

A B

Euclidean Algorithm

B = 18

36 18

Page 15: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 201411

36, 54

A B

Euclidean Algorithm

B = 18

A = 18

36 18

Page 16: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 201412

36, 54

A B

36 54

Euclidean Algorithm

36 18

GCD = 18

18 18

Page 17: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 201412

36, 54

A B

36 54

Euclidean Algorithm

36 18

GCD = 18

18 18

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iHaz 201413

Behavioural Model (Loop)A B

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iHaz 201413

Behavioural Model (Loop)

A B

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iHaz 201413

Behavioural Model (Loop)

A B

Page 21: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 201414

For Loop (Simulation)

Post-Route Simulation

Behavioural Simulation

Behavioural Simulation

Post-Route Simulation

Page 22: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 201414

For Loop (Simulation)

Post-Route Simulation

Behavioural Simulation

Behavioural Simulation

Post-Route Simulation

Page 23: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 201414

For Loop (Simulation)

Post-Route Simulation

Behavioural Simulation

Behavioural Simulation

Post-Route Simulation

Page 24: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 201415

For Loop (RTL, Implementation)

Page 25: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 201415

For Loop (RTL, Implementation)Device # # Bits Note

# Adders/Subtractors 198 16 -# Registers 0 - -# Comparators 200 16 "100= & 99<”# Multiplexers 298 16 2-1# FSM 0 - -# DSP 0 - -# XOR 0 - -Time Delay 478

# out of %# Slices 2748 3758 73# LUTs 8776 15032 58# MUXCYs 4760 7516 63# Registers 0 30064 0

Page 26: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 201416

Register Transfer Model (SM)A B

Page 27: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 201416

Register Transfer Model (SM)

A B

Page 28: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 201417

ASM (Code Sample)

Page 29: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 201418

ASM (Implementation)

Page 30: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 201418

ASM (Implementation)

Page 31: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 201418

ASM (Implementation)Device # # Bits Note

# Adders/Subtractors 2 16# Registers 32 1 FF# Comparators 2 16 "= & <”# Multiplexers 14 16 (8,1), 1(5) 2-1(13), 3-1(1)# FSM 1 - -# DSP 0 - -# XOR 0 - -Time Delay 20.7

# out of %# Slices 36 3758 1# LUTs 98 15032 1# MUXCYs 48 7516 1# Registers 34 30064 1

Page 32: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 201419

Direct Structural LevelA B

Page 33: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 201419

Direct Structural LevelA B

Page 34: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 201420

Dir. Structural (Implementation)

Page 35: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 201420

Dir. Structural (Implementation)

Page 36: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 201420

Dir. Structural (Implementation)Device # # Bits Note

# Adders/Subtractors 2 16 Sub/Accum.# Registers 2 16 32 FF# Comparators 2 16 "= & <”# Multiplexers 11 2 (16), 9 (1) 2-1# FSM 1 - -# DSP 0 - -# XOR 0 - -Time Delay 15.5

# out of %# Slices 30 3758 1# LUTs 85 15032 1# MUXCYs 52 7516 1# Registers 34 30064 1

Page 37: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 201421

Optimized Structural Level

Page 38: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 201421

Optimized Structural Level

Page 39: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 201422

Opt. Str. (Code Sample)

Page 40: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 201422

Opt. Str. (Code Sample)

Page 41: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 201423

Opt. Structural (Implementation)

Page 42: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 201423

Opt. Structural (Implementation)

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iHaz 201423

Opt. Structural (Implementation)Device # # Bits Note

# Adders/Subtractors 1 16 Carry in# Registers 2 16 32 FF# Comparators 0# Multiplexers 7 2 (16), 5 (1) 2-1# FSM 1# DSP 0# XOR 33 1 (16), 32 (1)Time Delay 23.6

# out of %# Slices 33 3758 1# LUTs 110 15032 1# MUXCYs 16 7516 1# Registers 34 30064 1

Page 44: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 201424

SummaryDevice 4Loop ASM 2Sub SADGCD

# Adders/Subtractors 198 2 2 1# Registers 0 32 2 2# Comparators 200 2 2 0# Multiplexers 298 14 11 7# FSM 0 1 1 1# DSP 0 0 0 0# XOR 0 0 0 33Time Delay 478 20.7 15.5 23.6

out of 4Loop % ASM 2Sub SADGCD# Slices 3758 2748 73 36 30 33# LUTs 15032 8776 58 98 85 110# MUXCYs 7516 4760 63 48 52 16# Registers 30064 0 0 34 34 34

Page 45: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 201425

Conclusion & Future Work

The Design of 16-bit GCD and its Implementation it on Xilinx Spartan6 FPGA was demonstrated. The area-speed tradeoff has been shown in different Levels:

High Behavioural Level ASM Behavioural Level Direct Structural Level Optimized Structural Level

Future Work: Primitives + Check new FPGAs where GCD might be implemented inside a DSP

Page 46: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 201426

https://www.youtube.com/watch?v=DMSaYhD1GkM

http://esd.cs.ucr.edu/labs/tutorial/

http://en.wikipedia.org/wiki/Greatest_common_divisor

And many others

Spartan-6 FPGA Configurable Logic Block User Guide (UG384 (v1.1) February 23, 2010)

References

Page 47: FPGA-Based Design and Implementation of the …...2 iHaz 2014 Design 16-bit GCD (the Greatest Common Divisor) and Implement it on Xilinx Spartan6 FPGA. It is challenging is to design

iHaz 201427

Thank You


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