four bit alu presented by: project manager: arturo coronado digital circuit design: rodger stamness...
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![Page 1: Four Bit ALU Presented By: Project Manager: Arturo Coronado Digital Circuit Design: Rodger Stamness Clocking:Rodger Stamness I/O:Juan Tello](https://reader030.vdocuments.site/reader030/viewer/2022032521/56649d585503460f94a3835a/html5/thumbnails/1.jpg)
Four Bit ALU
Presented By:
Project Manager: Arturo Coronado
Digital Circuit Design: Rodger Stamness
Clocking: Rodger Stamness
I/O: Juan Tello
![Page 2: Four Bit ALU Presented By: Project Manager: Arturo Coronado Digital Circuit Design: Rodger Stamness Clocking:Rodger Stamness I/O:Juan Tello](https://reader030.vdocuments.site/reader030/viewer/2022032521/56649d585503460f94a3835a/html5/thumbnails/2.jpg)
Objective
• Familiarization with the full custom IC design methodology.
• Develop good test and debugging skills.
• Learn to work on a team
• Learn documentation procedures
• Have fun!!!!!!
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Design Flow
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Philips’s 74L181
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Specifications
• Functionality: Logic and Arithmetic implementation of Philips 74L181
• Frequency: 25MHz
• Power: 750 mW
• Area: 1800 X 1800
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Chip Input & Output Circuits
• Design quality is a critical factor
-Reliability
-Signal Integrity
-Interchip Communication speed
• ESD
-Most prevalent causes for chip failures:
-Manufacturing and Field Operation
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Schimtt Trigger
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Super Buffer
![Page 9: Four Bit ALU Presented By: Project Manager: Arturo Coronado Digital Circuit Design: Rodger Stamness Clocking:Rodger Stamness I/O:Juan Tello](https://reader030.vdocuments.site/reader030/viewer/2022032521/56649d585503460f94a3835a/html5/thumbnails/9.jpg)
Padframe Floor plan
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Functions
![Page 11: Four Bit ALU Presented By: Project Manager: Arturo Coronado Digital Circuit Design: Rodger Stamness Clocking:Rodger Stamness I/O:Juan Tello](https://reader030.vdocuments.site/reader030/viewer/2022032521/56649d585503460f94a3835a/html5/thumbnails/11.jpg)
Cell-Base implementation
• A.O.I each function to get circuits.
• Each circuit is turned into a cell.
• Each cell builds up the ALU one cell at time; thus Bottom-Up design.
• Approximately 1/3 of the Design
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Transistor Level Design
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Cell Z1
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Cell-Base implementation
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Layout Cellular Design
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Final ALU Test Bench
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Waveform
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Project Update
• Completed:
-15/16 Functional Logic Blocks
-DFF
-Superbuffer
-Schmitt Trigger
• To be Completed
-Final Floor Plan and Verification Block
-Full Layout Assembly and Test
May 15, 2002