107/10/07

D. M. Lee, LANL

Forward Vertex DetectorStatus: R&D: Scientific and Technical Resources

• Technical Design Overview

• Design status

• R&D

• Cost and schedule

• Scientific Resources and Manpower

• Issues and Concerns

207/10/07

D. M. Lee, LANL

Forward Vertex DetectorTechnical Design – Specifications

• Cover the Muon Spectrometer Acceptance – both Arms (10-35 deg)

• Full Azimuthal coverage – hermetic

• DCA resolution < 200 µm at 5 GeV

• ≥ 3 space points / track

• Maximum Radiation Length < 2.4%

• Survive 10 year integrated dose = 200k Rad

• Low Occupancy in Au – Au Central < 10.0%

• Co-exist with barrel VTX

• Compatible with PHENIX DAQ

307/10/07

D. M. Lee, LANL

Forward Vertex DetectorTechnical Design – Mechanical

Combined VTX + FVTX without outer enclosure FVTX

“Big Wheel”

Location for all readout

electronics

407/10/07

D. M. Lee, LANL

Forward Vertex DetectorTechnical Design – Mechanical

4 hermetic disks, z=18.5 – 38 cm

48 wedge segments per disk ( 7.5 deg)

Inner disk radius = 3.5 cm (4.5 cm active)

Outer disk radius = 17 cm

75 micron strips, 550,000 strips/endcap

Total power load of disks = 50 W each

Power load of Readout cards= 450 W in big wheel

Room temperature operation

Each Endcap

507/10/07

D. M. Lee, LANL

Forward Vertex DetectorTechnical Design – Mechanical

Mechanical Integration with the Barrel VTX

Fully integrated model

607/10/07

D. M. Lee, LANL

Forward Vertex DetectorTechnical Design – Wedge

Backplane (0.76mm graphite fiber composite)

Screw (nylon)

Pin hole(for alignment)

Pin hole (for alignment)

HDI

Connectors for extension cables

Detector

FPIX Chips (26, 13 ea. side)

Screw (nylon)

All bonded with rigid epoxies

HDIDetector

FPHX Chips

Backplane

Rigid, thermally conductive epoxy

Rigid epoxy

707/10/07

D. M. Lee, LANL

Sensor HDIHDI

FPHX Chips (13 per column)

Mini-strips are oriented to approximate an arc

Forward Vertex Detector FVTX Sensor

• Sensor– 2 columns of strips– 1664 strips per column– strip length 2.8 to 11.2 mm– 75 µm spacing– 48 wedges per disk (7.5˚/sensor,

~15˚/wedge)– 0.5 mm overlap with adjacent wedges

• FPHX Chip– 1 column readout– 128 channels – ~ 70 µm channel spacing– Dimensions –9mm x 1.2 mm

807/10/07

D. M. Lee, LANL

Sensor layoutR&D prototyping design

Zoom in …

one FPHX chip

testing pads

(both staged)

bonding pads

Guard ring

Dicing edge

Vaclav Vrba, Prague

Thickness 300 µm

Doping of starting material n type

Resistivity 2-5 K-cm

Wafer diameter 6 “ preferred

Passivation SiO or SiN

907/10/07

D. M. Lee, LANL

SensorR&D A real prototype

Vaclav Vrba, Prague

1007/10/07

D. M. Lee, LANL

HDI Stack Up

GND

Signal

Signal

Power

HDI trace count

2 R/O lines x LVDS pair x 26 chips 1044 Download and Reset lines 42 Clocks x LVDS pair 41 Calibration line 1

113

Forward Vertex Detector HDI-High Density Interconnect

• High Density Interconnect (HDI) – kapton flat cable to transfer data from the chip to the read-out electronics

– 176 μm thick– 4 copper planes (ground, power, 2ea signal), 5

Kapton films, 8 glue layers

HDI

glue

glue

glue

glue

glue

glue

glue

glue

kapton

kapton

kapton

kapton

kapton

1107/10/07

D. M. Lee, LANL

Max deflection10.4μm

Zero deflection (boundary conditions)

Wedge R&D Analysis Temperature & Stress

3-D Temperature Contour

Max Tº = 20.3ºCWarmest ROC

Min Tº = 15ºC

• Warmest FPHX Chip is 5.3ºC Warmer than Back Edge of Backplane

3-D Distortion Contour

1207/10/07

D. M. Lee, LANL

Forward Vertex Detector Half-Disk Assembly: Details

Thermally conductive

Silicone

Plastic inserts for screws and pins

Single piece plastic insert for screws and pins

Standoff plate

Foam core

Honeycomb core

1307/10/07

D. M. Lee, LANL

Disk-Level R&D Modeling Thermal distortion

Max deflection of detector ~8μm

Fundamental vibration mode: 164 HzDistortion due to cooling

1407/10/07

D. M. Lee, LANL

Half Cage Assembly

Cooling hose (silicone)

Stat

ion

1

Stat

ion

2

Stat

ion

3

Stat

ion

4

Z

Y Al Honeycomb core, C face sheets

1507/10/07

D. M. Lee, LANL

Liquid Cooling CircuitR&D

FVTX Inlet: 10°C, ~5 psig

station 4: ~20.6°C

Outlet plane 4: 10.3°C

FVTX Outlet: 11.1°C, ~3 psigstation 3: ~20.9°C

station 2: ~21.2°C

Outlet plane 3: 10.6°C

Outlet plane 2: 10.9°C

Warmest Chip, station 1: ~21.4°C

1607/10/07

D. M. Lee, LANL

Half Cage AssemblyR&D

Gravity Sag (Max = 3.2µm) Drum mode shape (f=137.7 Hz)

1707/10/07

D. M. Lee, LANL

VTX+FVTXFinite Element Model R&D

First Mode: 38Hz

1807/10/07

D. M. Lee, LANL

FPHX Chip DesignR&D Phase 1

• Designed by FNAL• Based upon well tested FPIX2 chip design• Data push readout over 2 output lines• Zero suppression with programmable

threshold• Fully programmable logic with masking

capabilities• Data contains:

– 3 bit ADC– 7 bit Strip Information– 6 bit Beam Counter

• Noise 150e + 140e/pf• Power <110 µW per channel

Data Word structure TBDTime (ns)

1907/10/07

D. M. Lee, LANL

FPHX Chip DesignSpecifications – Phase 2

• Match to 75 µm strip spacing, ~ 70 µm channel spacing

• Design to strip capacitance ≤ 1.5 pf

• Dynamic range to extend to 50000 e-

• Noise ≤ 425 e-

• Chip readout, 4 hits in 4 beam clocks

• Use Data push architecture

• 4 bit ADC required, 5 bit goal, with programmable reference voltages

• 2 output lines

• All other FPIX2 specifications*

* FPIX2 has same output architecture as FPHX so FPIX2 is used for testing DAQ designs

2007/10/07

D. M. Lee, LANL

Forward Vertex DetectorTechnical Design – Electronics DAQ

Readout electronics split into two parts

– Near the detector (ROC)– Compresses and serializes the

data from a group of chips– Radiation tolerance use

FLASH based FPGAs from Actel– Fiber link to the control room

– In the Control Room (FEM)– Buffer data for 64 beam clocks– Send data to DCM upon LVL1

trigger request– SRAM based FPGAs from Xilinx

N FPHXChips ROC FEM PHENIX

DCM

1,2 output lines per chip

Stream of 20-bit data words @ 150 MHz– under design

Zero suppression

Programmable Threshold

Buffers Data for 64 Clocks

Upon Lvl-1 grab relevant data

Build packet

Send data to DCM/LVL1

Pass Clock to ROC

Slow controls manager

PHENIX StandardLimit <2000 20-bit words/DCM

GTMLVL1

fiber

SlowControl

Deserialize and Combine data from several FPHX chips

Strip Synch Words

Send data over fiber

Calibration

2.5 Gb/sfiber link

Inside IR In Counting House

2107/10/07

D. M. Lee, LANL

ROC Design Specifications

• Combine serial data from 52 FPHX chips ( 2 wedges)

• Synchronize readout and strip off Sync Words

• Generate ~130 MHz Serializer Clock

• Provides Control, Download and Calibration signals for the chips

• Append CHIP ID to the data

• Send parallel data word output at 130 MHz over 2 fiber interface to the FEM

• Move from ACTEL A3PE600 to ACTEL A3PE3000 FLASH based FPGA

= done

2207/10/07

D. M. Lee, LANL

ROC Block Diagram

2307/10/07

D. M. Lee, LANL

ROC Prototype R&D

USB Interface

Actel Board

DigiIO

8-chip module

• Actel A3PE600 prototype board

• Slow control via USB interface (DLP-2232M)

• Output data via NI-6534 PCI card at 20 MHz (up to 640 Mbps)

• Test an 8-chip FPIX module (FPIX is progenitor of FPHX chip and has similar digital backend)

2407/10/07

D. M. Lee, LANL

ROC Prototype R&D

USB Interface

Actel Board

DigiIO

8-chip module

Covers 30 deg (16 wedges)

2507/10/07

D. M. Lee, LANL

FEM Design Specifications

• FEM receives data from a single ROC channel over two fibers at fixed rate of 2.5 Gbits/s

• Main functionality– Store the data by BCO counter – Buffer data for 64 BCO clocks – Read the data from certain clock to output buffer at 300 MHz – Send the output buffer content to the DCM

• Plan to combine the data from 4 FEM channels on single FEM board• Implementation

– Xilinx mid-scale Virtex-4 FPGA VC4VSX35– Use built-in FIFOs and Relationally Placed Macros (RPMs) for maximum

performance and predictability (Provided by XILINX)

= done

2607/10/07

D. M. Lee, LANL

FEM R&D

• Design tested with single chip readout and “fake” data and running chip calibration chain

• 100% of hits propagates through FEM with realistic triggered readout• Readout to PC tested at 640 Mb/s rate using NI-6534 readout board

Virtex-4 test boardFPIX Chip

2707/10/07

D. M. Lee, LANL

Test of Calibration System

• Test each pixel by injecting 64 pulses at gradually increasing amplitude

• Upper figure shows histogram of turn-on curve for one channel

• Lower figure shows noise

• Inject capacitor = 3fF Noise ~ 102 e

2807/10/07

D. M. Lee, LANL

Summary Designs and R&D

• Mechanical design is well along and mature

• Some mechanical prototyping needed

• Sensor prototype finished and ready for testing

• Readout ROC and FEM prototyped and tested– Fiber link prototyped and under test– All other requirements met– Calibration circuit designed and to be implemented on ROC board

• FPHX conceptual design done, first pass

• FPHX R&D critical path

FEM with fiber readout

2907/10/07

D. M. Lee, LANL

Remaining R&D

• DAQ – ROC and FEM electronics PC boards are now in progress and will be complete by Jan 2008 – LDRD funded

• FPHX – complete design and chip layout – SOW in progress, signed by LANL and FNAL, ready for BNL signature – Start July 2007

• FPHX – First MOSIS run, early 2008

• Mechanics – some prototyping desirable 2007

FEM with fiber readout

3007/10/07

D. M. Lee, LANL

Mechanical structures – HYTEC estimate based on prior experience with VTX and ATLAS

Sensors – Quotes from CIS, MICRON

FPHX – FNAL estimate based on prior experience

Electronics Interface DAQ – estimate based on prior experience

Wire bonding – PROMEX quote

DCM,slow controls, etc – Muon system experience, Steve Boose

Cost Basis - Major Items

3107/10/07

D. M. Lee, LANL

FVTX Schedule Assumptions

•Construction start – January 1, 2008 ( 2nd QTR FY08)• LANL R&D start - January 2006

• BNL R&D start – October 2006

• Schedule durations determined by engineering estimates, vendor quotes

• Duration of project made to match funding profile

• VTX and LDRD impact the schedule especially R&D

• Wedge assemblies tested at a rate of 3/day ( automated computer tests)

• Disk assembly assembled in 2 week, metrology of disk in 2 week

• Commissioning for 8 months

3207/10/07

D. M. Lee, LANL

FVTX Major Cost Items

Major Item Base Cost Contingency Sum

Mechanical Ladder and support $416k 26% $524k

Sensor $410k 26% $517k

FPHX Chip $240k 36% $326k

Wire bonding $188k 26% $237k

ROC boards $443k 36% $603k

FEM boards $323k 36% $440k

HDI $111k 25% $139k

Total Project (FY07) $3669k 25% $4595k

3307/10/07

D. M. Lee, LANL

Scientific resources and ManpowerDOE Office of Nuclear Physics

J. Simon-GilloFederal Program Manager

DOE Project ManagerM. Butler

Brookhaven Site Office

BNL Program ManagerTom Ludlam

BNL

PHENIX FVTX Project OfficeProject Manager: M. Brooks (LANL)

Deputy Project Manager: D. Lee (LANL) Electronics System Engineer: E. Mannel (Columbia)Mechanical System Engineer: W. Sondheim (LANL)

PHENIX ManagementSpokesperson

B. JacakOperation Manager

E. O’BrienUpgrade Manager

A. Drees

Offline

SoftwareX. WangNMSU

SimulationX. Wang

NMSU,LANL,Saclay

Database

ROCM. Prokop

LANL

FEM

QAS. Butsyk

LANL

DAQM. Brooks

LANL

SensorJ. Kapustinsky/

LANL

Sensor DesignJ. Kapustinsky

LANL, Columbia,Czech

Sensor QAD. Winter/TBD

Columbia, UNM,Czech

FPHXJ. Kapustinsky/

D. WinterLANL/Columbia

FPHX DesignR. Yarema

FNAL,LANL,Columbia

FPHX QAR. Yarema

FNAL, LANL

CablingD. Fields

UNM

Flex CableD. Fields

UNM

HDIM. Hoferkamp

UNM, Columbia

FibersD. Fields

UNM

WedgeD. WinterColumbia

Wedge AssemblyD. Winter/TBD

Columbia, NMSU,UNM

Wire BondD. Winter/TBD

Columbia

Wedge QAD. Winter/TBD

Columbia, NMSUUNM

MetrologyD. Winter/TBD

Columbia

IntegrationMechanics

R. PakBNL

Mech StructuresD. LeeLANL

AssemblyInstallation

S. PateNMSU

Disk AssemblyS. Pate/PD

NMSU

Disk MetrologyS. Pate/PD

NMSU

Ancillary ServiceR. PakBNL

Cage AssemblyS. Pate/PD

NMSU

3407/10/07

D. M. Lee, LANL

Scientific resources and Manpower

Institution Construction Responsibilities Post Construction ResponsibilitiesBARC, Mumbai, India Simulations Data Analysis

Brookhaven National Laboratory(BNL physics, C-AD)

FVTX detector integration into PHENIX, E.S.H&Q, commissioning

Data Analysis

CEA, France Offline Data Analysis, Software

Charles University, Prague, Czech Republic Sensor, Software Data Analysis

Czech Technical University, Prague, Czech Republic Sensor, Software Data Analysis

Columbia University Wedge and sensor QA, FPHX, commissioning Data Analysis, Calibrations, Software

High Energy Accelerator Research Organization (KEK), Tsukuba, Japan

TBD Data Analysis

Iowa State University LVL-1 Data Analysis

Institute of Physics, Academy of Science, Prague (Czech) Sensor, software Data Analysis, Software

Kyoto University, Kyoto 606, Japan TBD Data Analysis, Software

Los Alamos National Laboratory Project ManagementDAQ electronics, FPHX, commissioningMechanical systemOversight of the mechanical system

Data Analysis, Calibrations, Software

New Mexico State University Simulation study, wedge, disk, cage assembly,commissioning Data Analysis, Calibrations, Software

University of Jyvaskyla, Finland TBD Data Analysis, Software

University of New Mexico HDI, flex cabling, Sensor Q/A and testing, commissioning Data Analysis, Calibrations, Software

Yonsei University, Seoul, Korea TBD Data Analysis, Software

7-2-2007 Draft

3507/10/07

D. M. Lee, LANL

Infrastructure and Facilities

• Columbia – Electronics lab and test equipment, 400 sq ft clean room

• Czech – Electronics lab and test equipment, clean room

• LANL – Electronics lab and test equipment, 600 sq ft clean room

• UNM – 256 sq ft clean room, probe station, test equipment

• BNL – lab space, measurement facilities

LANL Clean Room UNM Clean Room Columbia Clean Room

3607/10/07

D. M. Lee, LANL

Issues and Concerns

• FPHX is new and the highest risk item – will require careful attention

• Integration – VTX/FVTX integration– Strip layers still being designed– Big wheel electronics

• Electrical – grounding and shielding

• Extensive system tests will be required

3707/10/07

D. M. Lee, LANL

Backups

3807/10/07

D. M. Lee, LANL

Schedule

3907/10/07

D. M. Lee, LANL

Schedule

4007/10/07

D. M. Lee, LANL

Schedule

4107/10/07

D. M. Lee, LANL

Schedule

4207/10/07

D. M. Lee, LANL

Cost

Forward Endcap Cost Estimate - FVTXFY2007 dollars

total Cost with2 endcaps R&D R&D Construction(k$) comments contingencyContingency 2008.00 2009.00 2010.00

BNL(k$) LANL(K$)Mechanical ladder and support structure 50 100 416 HYTEC Estimate 0.26 523.92 523.92Alignment and Assembly jigs 72 engineering estimate 0.23 88.80 88.80Silicon Sensor 50 purchase 410 CIS and ON quotes, 10% spare, 80% yield0.26 516.60 516.60 setup and masks 30 CIS and ON quotes sensor Q/A and testing 50 University students + engineer 0.16 58.00 58.00PHX chip, tested 295 engineering run 240 FNAL estimate 0.36 326.40 326.40 testing 50 FNAL tech 0.16 58.00 58.00attach HDI to backplane 30 engineering estimate 0.22 36.60 36.60attach sensor 30 engineering estimate 0.22 36.60 36.60wire bond assembly 55 188 Promex quote 0.26 236.88 236.88test wedge assembly 40 engineering estimate 0.22 48.80 48.80ROC electronics 243.5 preproduction proto 73.3 engineering estimate 0.36 99.69 99.69 production 443.19 engineering estimate 0.36 602.74 602.74 Q/A 20 engineering estimate 0.14 22.80 22.80FEM electronics 246.5 preproduction 93.13 engineering estimate 0.36 126.66 126.66 production 323.18 engineering estimate 0.36 439.52 439.52 Q/A 20 engineering estimate 0.14 22.80 22.80Racks,LV,HV,DCM,install 81 existing designs 0.12 91.02 91.02slow controls 5 existing designs 0.01 5.06 5.60calibration system 22 Assemble endcap 90 techs and students 0.26 113.40 113.40Electronics Integration 250 Engineer 0.14 285.00 95.00 95.00 95.00Mechanical Integration 250 Engineer 0.14 285.00 95.00 95.00 95.00HDI bus 40 111.4 422 HDI, 10% spares, $250 ea. 0.25 139.04 139.04flex cables, sensor to ROC 25 51.2 784 flex, 2% spares, $42 ea. 0.13 57.64 57.64fibercables, ROC-FEM 3 31.2 56ea. -12 and 8 channel units 0.15 35.83 35.83lab equipment 100 probe, test equipment 0.1 110.00 110.00Management 200 0.14 228.00 76.00 76.00 76.00

total 345 815 3668.6 0.25 4594.80 1573.73 2545.59 476.02Inflation adjusted(.035 per year) 4883.04 1628.81 2726.33 527.91

BNL overhead 18%LANL overhead and GRT 19.5% All labor fully burdened

4307/10/07

D. M. Lee, LANL

LANL LDRD-DR - $589.9k expected ( to date) finish

• DAQ Interface Modules - $489.9k ($100.9k) Jan2008

• Mechanical design - $100k ($100k) Apr2007

LANL Heavy Ion Program - $130k

• Mechanical design - $130k ($130k) Apr2007

BNL R&D funds - $345k

• FPHX design and Prototype - $295k ( $67k) Jul2008

• Mechanical prototype - $50k ($0k) Jan2008

Czech Institute of Physics, Academy of Sciences

• Sensor – prototype finished – contribution

R&D Costs Associated for FVTX

4407/10/07

D. M. Lee, LANL

Disk Detail

4507/10/07

D. M. Lee, LANL

VTX – FVTX IntegrationThe need began 2 years ago

But we found this 2 months ago

Interference!

4607/10/07

D. M. Lee, LANL

Funding Profile

0

500

1000

1500

2000

2500

3000

FY06 FY07 FY08 FY09 FY10

Fiscal Year

$k

R&D

Construction

Funding Profile

4707/10/07

D. M. Lee, LANL

Manpower Fraction

Manpower Fraction

Manpower

Materials65%35%