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Reg. No. :

B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2009.

Third Semester

Electronics and Communication Engineering

EC 2203 — DIGITAL ELECTRONICS

(Regulation 2008)

Time : Three hours Maximum : 100 Marks

Answer ALL Questions

PART A — (10 × 2 = 20 Marks)

1. Prove that the logical sum of all minterms of a Boolean function of 2 variables

is 1.

2. Show that a positive logic NAND gate is a negative logic NOR gate.

3. Suggest a solution to overcome the limitation on the speed of an adder.

4. Differentiate a decoder from a demultiplexer.

5. Write down the characteristic equation for JK flipflop.

6. Distinguish between synchronous and asynchronous sequential circuits.

7. Compare and contrast static RAM and dynamic RAM.

8. What is PAL? How does it differ from PLA?

9. What are Hazards?

10. Compare the ASM chart with a conventional flow chart.

Question Paper Code : T3032

132 132 132

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T 3032 2

PART B — (5 × 16 = 80 Marks)

11. (a) (i) Express the Boolean function ZXXYF += in product of Maxterm.

(6)

(ii) Reduce the following function using K-map technique

( ) ( ) ( )6,214,12,10,8,7,4,3,0,,, dDCBAf += π . (10)

Or

(b) Simplify the following Boolean function by using Quine-Mcclusky method

( ) ( )∑= 13,12,10,8,7,6,3,2,0,,, DCBAF . (16)

12. (a) Design a carry look ahead adder with necessary diagrams. (16)

Or

(b) (i) Implement full subtractor using demultiplexer. (10)

(ii) Implement the given Boolean function using 8 : 1 multiplexer

( ) ( )∑= 6,5,3,1,, CBAF . (6)

13. (a) (i) How will you convert a D flipflop into JK flipflop? (8)

(ii) Explain the operation of a JK master slave flipflop. (8)

Or

(b) Explain in detail the operation of a 4 bit binary ripple counter. (16)

14. (a) Implement the following Boolean functions with a PLA

( ) ( )∑= 4,2,1,0,,1 CBAF

( ) ( )∑= 7,6,5,0,,2 CBAF

( ) ( )∑= 7,5,3,0,,3 CBAF . (16)

Or

(b) Design a combinational circuit using a ROM. The circuit accepts a three

bit number and outputs a binary number equal to the square of the input

number. (16)

15. (a) Design a three bit binary counter using T flipflops. (16)

Or

(b) Design a negative-edge triggered ‘T flipflop’. (16)

———————

132 132 132

Question Paper Code: 31353 B.E./BTech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2013.

Third Semester

Electronics and Communication Engineering

EC 2203/EC 34/080290010/10144 EC 304 — DIGITAL ELECTRONICS

(Regulation 2008/20 10)

(Common to PTEC 2203 — Digital Electronics for B.E. (Part—Time) Third Semester —

Electronics and Communication Engineering Regulation 2009)

Time: Three hours Maximum: 100 marks

Answer ALL questions.

PART A—(10 x 2= 20 marks)

1. State Distributive Law.

2. What is Prime Implicant?

3. Enumerate some of the combinational circuits.

4. List out various applications of Multiplexer.

5. Define: Latches.

6. Write short notes on Digital Clock.

7. What is Volatile and Non-Volatile memory?

8. Give the advantages of RAM.

9. What is Synchronous Sequential Circuit?

10. Write short notes on Hazards.

PARTB—(5 x 16=80 marks)

11. (a) (i) Simplify xy + x’ z + yz. (6)

(ii) Simplify the following expression using K-map method.

Y = ∑�(7,9,10,i 1,12,13,14,15). (10)

Or

(b) (i) Write short notes on don’t care conditions. (6)

(ii) Explain about NAND and NOR implementations. (10)

12. (a) Draw the logic diagram of BCD —. Decimal decoder and explain its

operations. . . (16)

Or

(b) Draw the block schematic of Magnitude Comparator and explain its

operations. (16)

13. (a) (i) Draw the block diagram of SR—FF and explain. (6)

(ii) Explain about triggering of flip-flops. (10) �

Or.

(b) Draw the block schematic of up-down counter and explain its operation. (16)

14. (a) Discuss in detail about the classifications of memories. (16)

Or

(b) Discuss in detail about the FPGA with suitable diagrams. (16)

15. (a) Design a serial binary adder using delay flip-flop. (16)

Or ..

(b) List out various problems arises in asynchronous circuits. Explain any

two problems in detail. (16)

B.E/ B.TECH DEGREE EXAMINATION, MAY/JUNE 2012

THIRD SEMESTER

ELECTRONICS AND COMMUNICATION ENGINEERING

EC2203-DIGITAL ELECTRONICS

PART -A 10x2=20

1. What is meant by weighted and non-weighted coding?2. Show that the Excess – 3 code is self –complementing3. Write down the truth table of a half sub tractor4. Define Combinational circuits5. What do you mean by encoder?6. What is PAL? How it differ from PROM and PLA?7. Draw the state diagram of ‘T’ FF, ‘D’ FF8. What are Mealy and Moore machines?9.What is meant by critical race?10.How to eliminate the hazard?

PART - B 5x16=80

11.a Reduce the following equation using Quine McClucky method ofminimization F (A,B,C,D) = _m(0,1,3,4,5,7,10,13,14,15)or

b,Find the MSP representation forF(A,B,C,D,E) = _m(1,4,6,10,20,22,24,26) + _d (0,11,16,27) using K-Map methodDraw the circuit of the minimal expression using only NAND gates

12.a(a) Draw a diode ROM, which translates from BCD 8421 to Excess 3 code(b) Distinguish between Boolean addition and Binary addition

orDesign a combinational circuit which accepts 3 bit binary number and converts its

equivalent excess 3 codes

13.a,Explain the operation of 4 to 10 line decoder with necessary logic diagramorb,.Design a combinational circuit using a ROM ,that accepts a 3- bit number and

generates an output binary number equal to the square of the given input number

14,a Design a modulo 5 synchronous counter using JK FF and implement it. Constructitstiming diagramorb,Design a binary counter using T flip – flops to count in the following sequences:(i) 000,001,010,011,100,101,110,111,000(ii) 000,100,111,010,011,000

15,a Summarize the design procedure for asynchronous sequential circuita. Discuss on Hazards and racesb. What do you know on hardware descriptive languages?

orb.Design an asynchronous sequential circuit with two inputs X and Y and with oneoutput Z.Whenever Y is 1, input X is transferred to Z.When Y is 0,the output does not changefor any change in X