floyd, digital fundamentals, 10 th edshanghai jiao tong [email protected] midterm...
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Floyd, Digital Fundamentals, 10th ed Shanghai Jiao Tong [email protected]
Midterm Examination
Wednesday, 11/21/201215:50 ~ 17:50East Upper Hall (东上院 ) 106
Floyd, Digital Fundamentals, 10th ed Shanghai Jiao Tong [email protected]
Digital Fundamentals
Tenth Edition
Floyd
Flip-flops
© 2008 Pearson Education
Floyd, Digital Fundamentals, 10th ed Shanghai Jiao Tong [email protected]
Latches
R
SQ
Q
EN
Show the Q output with relation to the input signals. Assume Q starts LOW.
Keep in mind that S and R are only active when EN is HIGH.
S
R
ENQ
Floyd, Digital Fundamentals, 10th ed Shanghai Jiao Tong [email protected]
Latches
R
SQ
Q
EN
Show the Q output with relation to the input signals. Assume Q starts LOW.
Keep in mind that S and R are only active when EN is HIGH.
S
R
ENQ
Floyd, Digital Fundamentals, 10th ed Shanghai Jiao Tong [email protected]
Edge-triggering
Floyd, Digital Fundamentals, 10th ed Shanghai Jiao Tong [email protected]
The J-K Flip-flop Named after its inventor: Jack Kilby. The feedback lines prevent SET (or RESET) operations when it is already in SET (or RESET) state.
Floyd, Digital Fundamentals, 10th ed Shanghai Jiao Tong [email protected]
The J-K Flip-flop
Create a T Flip-flop with a J-K Flip-flop.
Connect the input and its complement to J and K respectively.
Floyd, Digital Fundamentals, 10th ed Shanghai Jiao Tong [email protected]
The J-K Flip-flop
Create a D Flip-flop with a J-K Flip-flop.
Connect both J to D and K to complemented D.
Floyd, Digital Fundamentals, 10th ed Shanghai Jiao Tong [email protected]
The J-K Flip-flop When the pulse (spike) from the Pulse Transition Detector is not short enough, the J-K flip-flop will encounter the same invalid-state problem as basic S-R latches.
Floyd, Digital Fundamentals, 10th ed Shanghai Jiao Tong [email protected]
The J-K Flip-flop Another type of J-K flip-flop is called Master-Slave J-K Flip-flop, or pulse-triggered Flip-flop. In the example below, inputs are latched into the master S-R latch at the rising edge of the clock, and propagate into the slave latch at the trailing edge.
Symbol of master-slave FF
Floyd, Digital Fundamentals, 10th ed Shanghai Jiao Tong [email protected]
The J-K Flip-flopTable on the right shows the operation of the pulse-triggered J-K FF.
The timing diagram shows an example of negative pulse triggered J-K FF.
Floyd, Digital Fundamentals, 10th ed Shanghai Jiao Tong [email protected]
TE: Test EnableTI: Test Input
Flip-flop Applications – the scan Flip-Flop
Scan FF is a very useful type of FF in modern IC design.
Floyd, Digital Fundamentals, 10th ed Shanghai Jiao Tong [email protected]
Flip-flop Applications – the scan Flip-FlopThe scan flip-flips in a chip forms a chain.When TE is enabled, pre-defined test inputs may be injected into the chain through TI input, becoming the initial state of these FF.
Floyd, Digital Fundamentals, 10th ed Shanghai Jiao Tong [email protected]
Flip-flop Applications – the scan Flip-FlopTE is disabled after all FFs have been loaded, and then the FFs operate as normal D FFs. The states of the D FFs may be retrieved later through the TO output by asserting TE again.
Floyd, Digital Fundamentals, 10th ed Shanghai Jiao Tong [email protected]
Homework
1. Determine the Q output in Figure 1. Assume that Q is initially LOW.
2. Show the Q output of flip-flop B in Figure 2 in proper relation to the clock. Assume the flip-flops are initially RESET.