Abstract ––In this work, we describe thanalog pulsed circuits for programming the elfloating gate p-channel transistors. These ciinjection current into the floating gatesupporting the expected good resolution in tfrom observing two operating cycles. In tconstant injection current is applied then, inthe resulting drain current is compared withkeeping the floating gate transistor inside thcircuit, where it belongs to. Both cycles, whichinterleaved are valid until the target currentdetected by a current comparator. This strateno appreciable programming error. For the sit is introduced an injection current modetechnology used in this programming circmicron, n-well, CMOS, whose electrical contained in the Mentor IC Nanometer Suite.

Keywords ––FGMOS, pFGMOS, prograinjection, hot electron injection, VLSI, floatGraphics.

I. INTRODUCTION At present, the p-channel, floating gate(pFGMOS) is taken as an essential elemmemories and low frequency analog signal [1,2]. The main drawback in the usage otransistors is the need of removing andelectrical charge at the floating gate structurisolated poly-silicon strip), which ultimthreshold voltage parameter. Hot electrophysical mechanism by which electrons genof holes in the channel near the drain gain esurpass the SiO2 energy barrier injecting gate and therefore diminishing its total posinjecting electrons into the floating gate diminish (program) its positive charge maka versatile device to use amidst a wideUsually 2 phases can be observed withpFGMOS transistors, one in which the taking place and a second in which the pwithin an application circuit. However, themight change due to the effect of neequivalent capacitances when the programreconnected at the working circuit. The programming protocol presented iproblem into account and minimizes it for in operational amplifiers. On the other handimproved and applied to a large array of t

Floating Gate MOSFET Pr

O. Hernández-Garnica1, F. G1Department of Electr

E-mail: ohernandezgarn

he low-complexity lectrical charge of rcuits control the

e. The principle this system comes the first cycle, a

n the second cycle, h a target current he working analog h are periodic and t is reached, event egy seems to have simulation results, el supporting the cuit namely, 0.5-parameters were

amming, CMOS, ting gate, Mentor

e MOS transistor ment for analog processing tasks of the pFGMOS d/or altering the re (an electrically mately sets the n injection is a

nerated by impact energy enough to into the floating sitive charge. By it is possible to

king the transistor e set of circuits. hin the usage of

programming is pFGMOS is used e resulting charge w voltages and

mmed transistor is

n [3] takes this differential pairs

d, this approach is transistors in [4],

increasing the programming resoldemanding a complex algorithm. Inorigin of the programming error afeature, we propose a differentsupported by external standard parts

II. PROGRAMMING PR We show the programming priwhere M1, M2 and M3 are pFGMOsame floating gate. During the progFig.1 the switch SW1 is openetransistor M1 is used to inject eleinto this common floating gate, dimcharge during a finite time T1 by aV2 to sustain a difference of Vsd ~used as a bias transistor, fixing the pa constant current I_bias and also cV4. Both M1 and M2 are active dcycle (Fig.1) and passive during tThe programming and the analog cintervals T1 and T2 respectively. Aperiod T, whose frequency is F = 1/V1 through V6 along with VDD1 an

Fig. 1 Circuit representing the pr

rogramming Circuit for Standard CMO

Gómez-Castañeda1, J.A. Moreno-Cadenas1, L.M.trical Engineering, CINVESTAV-IPN, Mexico D.F., MexPhone (52) 55 5747 3800 Ext. 6261

nica@gmail.com; {fgomez, jmoreno, lmflores}@cinvesta

lution and velocity, but n our work, observing the s a charge redistribution t programming system s.

RINCIPLE

inciple in Figs.1 and 2, OS transistors sharing the gramming cycle shown in d, SW2 is closed and ctrons at a constant rate

minishing its total positive applying voltages V1 and ~ 5.1V. Transistor M2 is potential Vg as a result of constant voltages V3 and during the programming the analog cycle (Fig.2). cycles appear in two time Also T1+T2 conform the /T. In both Figs. 1 and 2, nd VDD2 are DC levels.

rogramming cycle.

OS Technology

Flores-Nava1 xico

av.mx

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Fig. 2 Circuit representing the analog

During the analog cycle (T2) we make trM2 passive by applying voltage VDD1 tdrain terminals and M3 active by closing opening switch SW2 as can be seen in Fprogramming cycle and the activation of tvoltage in the floating gate changes rescharge redistribution ΔQ into C1, C2, CoxCox1 and Cox2 are the gate capacitances respectively. ΔQ is the electronic charge injprogramming cycle. Voltages V3 and V5 come from a gfeedback and their values are observed as: external DC voltage and, 2) the change of Vobeys to the capacitive balance: ΔV5=Q/Ccapacitances are neglected); where Q is thecharge, C1 is defined by geometrical layoparasitic capacitance resulting of the bottThe injection current of electrons into the be estimated using the model below. _ Vg V2 λ

Where Is is the source current of M1. originally reported for 0.35-micron CMO[5], with: α = 1.30x10-5, β = 155.75, δ = 0the other hand, the same parameters (α, β, 0.5-micron, n-well, CMOS technology havcomputed in a parallel work [6], followingMarquardt optimization method from expefabricated floating gate transistors, getting:

α = 70x10-5 β = 1415 δ = 4.683 λ = 1.695

g cycle.

ransistors M1 and to its source and switch SW1 and

Fig.2. Due to the transistor M3 the sulting from the x1, Cox2; where of M1 and M2,

njected in a single

gain block with 1) V3 follows an V5 namely, ΔV5 1 (other parasitic e present injected out and C2 is the tom plate of C1. floating gate can

λ V1 V2

This model was OS technology in

.702, λ = 1.0; on δ and λ) for the ve been recently g the Levenberg-erimental data on

The analog current I_d3 is percascode array (formed by transistorwhose output is subtracted from target current, I_targ). The sign oI_diff, which is given by a curdetermines stopping the programmI_d3 equals I_targ, the whole of injQtotal=(N)(T1)(I_inj), where N is to reach I_targ. Likewise, the chang ∆

III. SUPPORTING ANALOG AND DI This section presents the entire pincludes analog and switching compintegrated and other external. In diagram of the actual programmIntegrated transistors Ms1, Ms2, Mthe switches SW1 and SW2 showchange the circuit between theprogramming cycle and the analog are the gain blocks: OpAmp1 (alOpAmp3, not shown in Fig. 3); belong to the current sources I_electrical diagrams are shown in Fisources use an integrated p-channel with an external resistor (R1 and Rand OpAmp3 are LMC662 electroDC supply. R1 and R2 are 10x106 oDC voltages for regulating a 100 nC1 is 0.1 pF (thus, C2 is 0.017 pstates of the pulsed voltages: V_pulT1 and T2. In fact, these pulsgenerated by standard electronics; thwork. Lastly, the current compintegrated based on contemporary din [7].

riodically copied by the rs M5, M6, M7 and M8),

a reference current (or of the difference current rrent comparator block,

ming process. Thus, when jected charge is given as: the count of pulses used

ge of Vg is given by (1):

(1)

IGITAL COMPONENTS

programming circuit that mponents, which are some

Fig. 3 is the electrical ming circuit is shown.

Ms3, Ms4 and Ms5, act as wn in Fig.1 and Fig.2 to e functionality of the cycle. The external parts

long with OpAmp2 and OpAmp2 and OpAmp3

_bias and I_targ, whose gs. 4 and 5. Both current transistor (M9 and M10)

R2). OpAmp1, OpAmp2 onic parts, with 0V-12V ohm each; V7 and V8 are nA-current. The capacitor pF). Table I presents the lse1 through V_pulse6 at sed voltages should be hey are not shown in this arator block might be designs; one candidate is

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428

Fig. 3 Detailed programming circ

Fig. 4 Implementation of I_bias curren

Fig. 5 Implementation of I_targ curren

cuit.

nt source.

nt source.

Table I

Cycle =>> “Programming” (TV_pulse1 VDD2 V_pulse2 V1 V_pulse3 V2 V_pulse4 V4 V_pulse5 VDD1 V_pulse6 GND

IV. ELECTRICAL SIMU

This programming circuit wamicron, n-well, CMOS ON Sparameters. The initial floating established ramping from ground toDC voltage sources. This procedurconvergence in DC [1], considers thTable II shows the size ratio, W/Lanalog transistors, and Table III transistors. The DC voltage levels fpulses are in Table IV. Figs. 6 and 10 ms each at the beginning aprogramming process, respectively in M1 (Figs. 6a and 7a), and for the(Figs. 6b and 7b). For this sample si1 KHz in the switching pulses withms is considered. Also, the analyinterval [0 s, 10 s]. During the “proIbias is 100 nA, M2 sets Vg at 3.voltage is kept at 2.0 V); transistorinjection current value of 15.82 fAcurrent is 1.97 uA. The progexperiments a change of its drain ctime 0.005 s) to 1650 nA (at time 1to the change of the floating gate 2.378 V to 2.069 V).

Table II

M1 0.6M2 0.6M3 0.6M4 0.6M5 7.5M6 7.5M7 7.5/M8 7.5/M9 9.0M10 9.0

T1) “Analog” (T2) GND

VDD1 VDD1 VDD1

V6 VDD1

ULATION

as simulated using 0.5-emiconductor electrical

gate voltage (Vg) is o the working voltage all re, which avoids lack of he ideal case where Q=0.

L in micro/micron for all does for the switching

for supply and switching 7 show two snapshots of

and at the end of the for the injection current

e floating gate voltage Vg imulation, a frequency of

h T1= 0.5 ms and T2=0.5 ysis is done in the time ogramming” cycle, where .723 V, (its source-drain r M1 provides a constant A, meanwhile its source rammed transistor M3 urrent from 0.745 nA (at

10 s), which is associated voltage: 309 mV (from

6/0.9 6/9.0 6/9.0 6/9.0

/7.5 /7.5

/30.0 /30.0

0/0.6 0/0.6

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Table III

Ms1 0.9/0.6 Ms2 0.9/0.6 Ms3 0.9/0.6 Ms4 0.9/0.6 Ms5 0.9/0.6

Table IV

VDD1 3.0 V VDD2 6.5 V

V1 5.1 V V2 0 V V3 4.5 V V4 2.5 V V5 4.42 V V6 2.0 V V7 5.5 V V8 2.0 V

Fig. 6 (a) constant injection current (b) floating-

first 10 pulses.

Fig. 7 (a) Constant injection current (b) floating-

last 10 pulses.

-gate voltage at the

-gate voltage at the

V. CONCLUSIO

An analog pulsed programmingthis work to inject a constant finite the floating gate of pFGMOS programming pulse until a target dWe used an injection current mstandard CMOS 0.5-micron, n-wellwide interval of drain current valuefrom nA to uA) in which the procan be reached using a represenAlso, the time for programming isseconds. It remains estimating the acurrent as a function of the time in tnamely, T1. This technique might blow number of floating-gate transprototype and reducing the need to i

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[2] Learning on Silicon. AdaptivCauwenberghs, G. and Bayoumi, Publishers (1999).

[3] A Precision CMOS Amplifier Ufor Offset Cancellation. Srinivasaand, Hasler, P. IEEE J. Solid-S(2007), pp. 280-291.

[4] Adaptive Algorithm Using Programming Analog Computatio0.2% Accuracy Over 3.5 DecadesG.J., and Hasler, P. IEEE J. Solid(2006), pp. 2107-2114.

[5] A Simulation Model for FTransistors. Rahimi, K., DioriBrockhausen, M.D. 2002 Internaand Systems, ISCAS 2002, Vol. 2

[6] Injection Current Model FittingMOS Transistors Using the LHernandez-Garnica, O., Gomez-CJ.A., and Flores-Nava, L.M. 201Electrical Engineering, ComputControl, CCE 2013, Sept. 2013,published in this proceedings serie

[7] Low-Power High-Speed Current Cand Toumazou, C. Electronics Lpp. 171-172.

ON

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model fit describing the l, technology. There is a s (3 orders of magnitude, gramming target current

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