Flip-Flops

Lecture L8.2

Section 8.1

Recall the !S-!R Latch

!S

!R

Q

!Q

0 00 11 01 1

!S !R Q !Q1

1

0

1 0 1

0 0 10 1 11 0 11 1 0

X Y nand

1 0 Set

1 0 Store

0 1 Reset

1 1 Disallowed

Q0 !Q0

Edge-triggered D Flip-flop

!S

!R

Q

!Q

1

2

3

4

5

6

CLK

D

F1

F2

F3

F4

F5

F6

0 1

1

1 0

1

Edge-triggered D Flip-flop

!S

!R

Q

!Q

1

2

3

4

5

6

CLK

D

F1

F2

F3

F4

F5

F6

1

0

1 0

1

1 0

1

Edge-triggered D Flip-flop

!S

!R

Q

!Q

1

2

3

4

5

6

CLK

D

F1

F2

F3

F4

F5

F6

1

0

1 0

1

0 1

1

Edge-triggered D Flip-flop

!S

!R

Q

!Q

1

2

3

4

5

6

CLK

D

F1

F2

F3

F4

F5

F6

1

0

0 1

1

0 1

0

Edge-triggered D Flip-flop

!S

!R

Q

!Q

1

2

3

4

5

6

CLK

D

F1

F2

F3

F4

F5

F6

1 1

0

0 1

0

0

1

Edge-triggered D Flip-flop

!S

!R

Q

!Q

1

2

3

4

5

6

CLK

D

F1

F2

F3

F4

F5

F6

1 1

0

1 1

0

0

1

Edge-triggered D Flip-flop

!S

!R

Q

!Q

1

2

3

4

5

6

CLK

D

F1

F2

F3

F4

F5

F6

0 1

1

1 0

1

0

1

!S

!R

Q

!Q

1

2

3

4

5

6

CLK

D

F1

F2

F3

F4

F5

F6

Edge-triggered D Flip-flop

!S

!R

Q

!Q

1

2

3

4

5

6

CLK

D

F1

F2

F3

F4

F5

F6

Edge-triggered D Flip-flop

Edge-triggered D Flip-flop with asynchronous preset and clear

!S

!R

Q

!Q

1

2

3

4

5

6

CLK

D

F1

F2

F3

F4

F5

F6

ap

ar

7

8

F7

F8

!S

!R

Q

!Q

1

2

3

4

5

6

CLK

D

F1

F2

F3

F4

F5

F6

ap

ar

7

8

F7

F8

Edge-triggered D Flip-flop with asynchronous preset and clear

D Flip-Flop

CLK

D Q

!Q0 0 11 1 0X 0 Q0 !Q0

D CLK Q !Q

D gets latched to Q on the rising edge of the clock.

Positive edge triggered

Each Xilinx 95108 macrocell contains a D flip-flop

Controlled inverter

Each Xilinx 95108 macrocell contains a D flip-flop

Note asynchronouspreset

x

Q.AP = x

Note asynchronousreset Q.AR = y

y

Q.D = z

z

Divide-by-2 Counter

CLK

Q0

Q0.D = !Q0

CLK

D Q

!Q

Q0.D = !Q0

Q0Q0.D

!Q0

MODULE div2cnt

TITLE 'Divide By 2 Counter'

DECLARATIONS

" INPUT PINS "

PB PIN 70; " push-button switch (clock)

" OUTPUT PINS "

Q0 PIN 44 ISTYPE 'reg buffer'; " LED 16

div2cnt.abl

CLK

D Q

!Q

Q0.D = !Q0

Q0Q0.D

!Q0

RegisteredBuffer output

EQUATIONS

Q0.C = PB;

Q0.D = !Q0;

test_vectors(PB -> Q0)

.C. -> 1;

.C. -> 0;

.C. -> 1;

.C. -> 0;

.C. -> 1;

.C. -> 0;

END

div2cnt.abl (cont’d)

CLK

D Q

!Q

Q0.D = !Q0

Q0Q0.D

!Q0

.C. means clock goesLO-HI-LO

Power-on output Q0 = 0

A 1-Bit Register

CLK

D Q

!Q

CLK

Q0

!Q0

LOAD

INP0

Q0.D = Q0 & !LOAD # INP0 & LOAD

reg1Q0

!Q0

LOAD

INP0

CLK

MODULE reg1bit

TITLE '1-bit register, R. Haskell, 10/13/02'

DECLARATIONS

hex7seg interface([D3..D0] -> [a,b,c,d,e,f,g]);

d7R FUNCTIONAL_BLOCK hex7seg;

" INPUT PINS "

PB PIN 70; " push-button switch (clock)

LOAD PIN 11; " switch S6:1

clear PIN 7; " switch S6:2

INP0 PIN 1; " switch S7:4

" OUTPUT PINS "

Q0 PIN 44 ISTYPE 'reg buffer'; " LED 16

[a,b,c,d,e,f,g] PIN 15,18,23,21,19,14,17 ISTYPE 'com';

" Rightmost (units) 7-segment LED display

EQUATIONS

Q0.C = PB;

Q0.AR = clear;

Q0.D = Q0 & !LOAD # INP0 & LOAD;

[a,b,c,d,e,f,g] = d7R.[a,b,c,d,e,f,g];

d7R.D0 = Q0;

d7R.[D3..D1] = [0,0,0];

test_vectors([PB,clear,LOAD,INP0] -> Q0)

[.C.,1,0,1] -> 0;

[.C.,0,1,1] -> 1;

[.C.,0,0,0] -> 1;

[.C.,0,1,0] -> 0;

[.C.,0,0,1] -> 0;

[.C.,0,1,1] -> 1;

[.C.,0,0,0] -> 1;

[.C.,0,0,1] -> 1;

[.C.,0,1,0] -> 0;

END

A 4-Bit Register

reg1Q0

!Q0

LOAD

INP0

reg1Q1

!Q1INP1

reg1Q2

!Q2INP2

reg1Q3

!Q3INP3

CLK

reg1Q0

!Q0

LOAD

INP0

CLK

4-Bit Register reset to 1010

reg1Q0

!Q0

LOAD

INP0

reg1Q1

!Q1INP1

reg1Q2

!Q2INP2

reg1Q3

!Q3INP3

CLK

ar

ap

ap

ap

ap

ar

ar

ar

Resetto A = 1010

MODULE reg4bit5INTERFACE (clk,reset,load,[IN3..IN0] -> [Q3..Q0]);TITLE '<Name 1>, <Name 2>, <Date>'

DECLARATIONS" Input Pins "clk PIN ; reset PIN ;

load PIN ; IN3..IN0 Pin ; INP = [IN3..IN0]; " 4-bit input data " Output Pins "Q3..Q0 PIN ISTYPE 'reg buffer'; Q = [Q3..Q0]; " 4-bit register

EQUATIONS

Q.c = clk;[Q2, Q0].ar = reset;[Q3, Q1].ap = reset; "reset Q = 5Q.d = INP & load # Q & !load;

END reg4bit5

J-K Flip-flops

CLK

D Q

!Q

J

K

CLK

Q

!Q

Q.D = J & !Q # !K & Q

J K Eq. (8.1) 0 0 Q.D = Q 0 1 Q.D = 0 1 0 Q.D = !Q # Q = 1 1 1 Q.D = !Q

J-K Flip-flops

J

CLK

Q

!QK

0 0 Q0 !Q00 1 0 11 0 1 01 1 TOGGLEX X 0 Q0 !Q0

J K CLK Q !Q

J K Eq. (8.1) 0 0 Q.D = Q 0 1 Q.D = 0 1 0 Q.D = !Q # Q = 1 1 1 Q.D = !Q

T Eq. (8.2) 0 Q.D = Q 1 Q.D = !Q

T Flip-flops

CLK

D Q

!Q

CLK

Q

!QT

Q.D = T $ Q

T Flip-flops

T

CLK

Q

!Q

0 Q !Q 1 !Q Q

T CLK Q !Q

T Eq. (8.2) 0 Q.D = Q 1 Q.D = !Q

MODULE Tdiv2cntTITLE 'Divide By 2 Counter using T flip-flop' DECLARATIONS" INPUT PINS "PB PIN 70; " push-button switch (clock) " OUTPUT PINS "Q0 PIN 44 ISTYPE 'reg buffer'; " LED 16 EQUATIONSQ0.C = PB;Q0.T = 1; test_vectors(PB -> Q0).C. -> 1;.C. -> 0;.C. -> 1;.C. -> 0;.C. -> 1;.C. -> 0; END

T

CLK

Q

!Q

0 Q !Q 1 !Q Q

T CLK Q !Q1