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TRANSCRIPT
AD A145 694 ZERO-IF RECEIVER STUDY REVISION(U) ITTAEROSPACE/OPTICAL DIV FORT WAYNE IND E J NEYENS ET AL.10 dUN 83 ITT-A/OD O31174A O03 DAAKO-81-C-0154
UNCLASSIFIED F/G 07/2.1
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%i1CRC0P RESOLL)TiON TEST CHART
NA.. . iiE, ii BiT S i I II
ITT-A/OD NO. 31174A003
to ZERO-IF RECEIVER
STUDYI
FINAL TECHNICAL REPORT
CDRL NO. A003 DTICSfILECTE
SEP 2 4 W4
PREPARED FOR:
UNITED STATES ARMY
__ COMMUNICATIONS-ELECTRONICS COMMAND-. 5
-. FORT MONMOUTH, NEW JERSEY 07703
~ CONTRACT NO. DAAK80-81-C-0154 [D STkIRUTUN STATEMENT A.C= Approved for public teleksq
Ditribution Unlimitedi _._
AEROSPACE/OPTICAL DIVISIONFORT WAYNE, INDIANA
84 06 29 078
ITT-A/OD 31174A003 10 JUNE 1983
FINAL TECHNICAL REPORT
CDRL NO. A003
FOR
ZERO-IF RECEIVER STUDY
CONTRACT NO. DAAK8O-81-C-0154
REVISED EDITION
PREPARED BY
E. J. NEYENSD. J. SCHWARZ
ITT AEROSPACE/OPTICAL DIVISION3700 EAST PONTIAC STREET
P.O. BOX 3700FORT WAYNE, INDIANA 46801
FOR
UNITED STATES ARMYCOMMUNICATIONS-ELECTRONICS COMMAND
FORT MONMOUTH, NEW JERSEY 07703
Table of Contents
Section No. Title Page
1 INTRODUCTION ...................................... 1
2 TECHNICAL OBJECTIVES AND PROGRAM REQUIREMENTS ..... 32.1 DESIGN SPECIFICATIONS AND PROGRAM DESCRIPTION 32.2 TECHNICAL APPROACH ................................ 32.2.1 Preselector Filters ............................... 42.2.2 RF Amplifier and RF AGC Circuits .................. 42.2.3 Signal Splitter Circuit ........................... 142.2.4 Quadrature LO Circuit ............................. 182.2.5 Baseband Filter ................................... 182.2.6 Low-Noise Amplifier ............................... 182.2.7 Baseband AGC ...................................... 182.2.8 Demodulator ....................................... 192.2.9 Audio Circuits .................................... 19
3 ANALOG DEM4ODULATOR ................................ 273.1 PHASE-LOCKED-LOOP DEMODULATOR ........................ 303.2 ANALYSIS OF PHASE-LOCKED-LOOP DEMODULATOR ......... 333.3 ANALOG ZERO-IF RECEIVER BREADBOARD .................. 383.4 TEST RESULTS - ANALOG ZERO-IF RECEIVER ............ 40
4 DIGITAL DEMODULATOR .................................. 444.1 VECTOR PROCESSOR .................................. 454.2 EXPLANATION OF VECTOR PROCESSOR ..................... 474.3 DIGITAL ZERO-IF RECEIVER ............................. 514.4 TEST RESULTS: DIGITAL ZERO-IF RECEIVER ............. 51
5 CONCLUSIONS AND RECOMMENDATIONS ...................... 56
6 OPERATIONAL INSTRUCTIONS ............................. 576.1 TEST EQUIPMENT REQUIREMENTS .......................... 576.2 POWER SUPPLY CONNECTIONS ............................. 576.3 SIGNAL GENERATOR CONNECTIONS ......................... 576.4 RECEIVER POWER-UP ................................. 586.5 SINAD MEASUREMENTS ................................ 586.6 RECEIVER POWER-DOWN ............................... 586.7 CONVERSION FROM ANALOG TO DIGITAL DEMODULATION ..... 586.8 CONVERSION FROM DIGITAL TO ANALOG DEMODULATION ..... 59
7 DIGITAL ZERO-IF COMPUTER SIMULATION ............... 60
APPENDIX SCHEMATIC DIAGRAMS, PARTS LIST,A COMPUTER SIMULATION LISTING, AND FUNCTIONAL
DESCRIPTION OF THE ZERO-IF RECEIVER .............. 61
List of Illustrations
Figure No. Title Page
2.2-1 Breadboard Block Diagram ........................... 52.2.1-1 Block Diagram of Preselector Filters ............... 62.2.1-2 Zero-IF Preselector Filter Band 1 .................. 102.2.1-3 Zero-IF Preselector Filter Band 2 .................. 112.2.1-4 Zero-IF Preselector Filter Band 3 .................. 122.2.2-1 Block Diagram of RF Amplifier Attenuator Board ...... 132.2.3-1 Block Diagram of Splitter/Mixers ................... 152.2.5-1 Frequency Response of Baseband Filter .............. 172.2.6-1 Block Diagram of the Low-Noise Amplifier ........... 202.2.6-2 Low Noise Amplifier Frequency Response .............. 222.2.7-1 Block Diagram of Baseband AGC ...................... 232.2.9-1 Block Diagram of Audio Circuits .................... 242.2.9-2 Zero-IF Receiver Audio Board Filter Response ....... 263-1 Filter Bandwidth and Phasor Diagram ................ 283-2 Demodulator Output (Positive Output) ............... 293-3 Demodulator Output (Negative Output) ............... 293-4 Discriminator Characteristic ....................... 293-5 Basic Zero-IF System ............................... 313.1-1 Analog Demodulators ................................ 323.1-2 Bode Plot Zero-IF PPL Demodulator (2nd Order) ...... 343.2-1 Zero-IF Phase-Locked-Loop Processor ................ 353.3-1 Zero-IF Receiver Block Diagram ..................... 394. 1-1 Zero-IF Digital Demodulator Block Diagram .......... 484.2-I Vector Processor Block Diagram ..................... 494.2-2 Vector Processor Flow Chart ........................ 504.3-1 Digital Zero-IF Receiver Block Diagram ............. 52
i i
List of Tables
Table No. Title Page
2.2.1-1 30-43 MHz Preselector Filter Response .............. 72.2.1-2 43-66 MHz Preselector Filter Response .............. 82.2.1-3 62-88 MHz Preselector Filter Response .............. 92.2.2-1 RF Amplifiers with PIN Diode Attenuator ............ 142.2.5-1 Channel Filter Frequency Response .................. 162.2.6-1 Frequency Reaponse Zero-IF Receiver Low
Noise Amp Input Voltage - 3 mVrms Constant ........ 212.2.9-1 Frequency Response Audio Filters Input
Voltage = 0.66 mVrms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252.2.9-2 Percent of Distortion of Audio Filters ............. 25
4-1 Digital Demodulation Techniques .................... 46
Section 1
INTRODUCTION
The Zero-IF Receiver Study was performed to design andfabricate a breadboard model of a Zero-IF receiver with both analog anddigital techniques. The value of this Zero-IF architecture will befully realized when the low frequency circuits inherent in a Zero-IFsystem are reduced to one or two LSI circuits. In today's LSI tech-nology, in which complete synthesizer subsystems may be integrated on asingle chip (less voltage controlled oscillator and crystal reference),the receiver becomes the transceiver subassembly that has the greatestneed for unique size reduction techniques. This 4ero-IF technique,when applied to the design of small hand-held FM transceivers, offersdistinct advantages with respect to size and weight reduction. Notonly can the "IF" and demodulator be integrated, but this receiverarchitecture places reduced requirements on the receiver preselectorfilters.
In typical available transceivers, the receiver occupiesone-third or less of the volume of the transceiver. The rest of thepackage contains a synthesizer and transmitter. htand-held transceiversnormally employ relatively low-power transmitters (five watts or less)because of practical battery limitations. These transmitters, there-fore, are relatively small and are not the major size limitingsubassemblies of hand-held transceiver systems. The larger portions ofthe receiver are normally the receiver preselector and the IF crystalfilter.
A Zero-IF receiver design is basically a form of superhe-terodyne design in which the receiver local oscillator operates at thesame frequency as the RF signal. For a frequency modulation systembased on the Zero-IF principle, all of the gain and signal processingafter mixing is accomplished at audio frequencies. The KF gainrequired is only that necessary to maintain noise figure for desiredreceiver sensitivity. The primary advantage of this type of design isthat the majority of receiver gain and subsequent signal demodulationand signal processing are done at audio frequencies. With today'sintegrated circuit technology, much of this audio circuitry can be con-verted to digital circuitry and processed with highly producible largescale integration (LSI); this leads to lower cost receiver-transmitter
designs. Uther advantages for this type of receiver design are asfollow:
" No stringent attenuation requirements on the KF sectionof the receiver to meet the image response requirementof a conventional design.
" Synthesizer-controlled, variable-frequency oscillator(VFU) can function directly as both the receiver localoscillator and as the transmitter exciter withoutchanging frequency. Only modulation must be introducedto perform the transmit function.
In a Zero-IF receiver system, the local oscillator signalis at the same frequency as the incoming RF signal. Therefore, thepreselector provides no attenuation of the local oscillator signal.The problem of high local oscillator radiation in a Zero-IF system issolved through the use of high reverse isolation RF amplifier designtechniques. The local oscillator attenuation achieved with these RFamplifiers, when added to that of the double-balanced mixers, willreduce the local oscillator radiation to less than -73 dBm.
Both the analog and digital Zero-IF breadboard met or ex-ceeded all of its performance goals and the other program objectives.
2
Section 2
TECHNICAL OJECTIVES AND PROGRAM REQUIREMENTS
The objective of the Zero-IF Receiver Study was to fabri-cate a breadboard model of a Zero-IF receiver to illustrate the feasi-bility and performance of this design concept. Initially, a completereceiver system was designed, breadboarded, and tested with a phase-locked-loop (PLL) Zero-IF demodulator. After the successful completionof this effort, a digital demodulator was designed and fabricated. Thedigital demodulator was fabricated on a sub-chassis that plugged intothe original PLL receiver. During this study, emphasis was placed onFM Zero-IF demodulator techniques, however, a complete receiver wasfabricated to demonstrate what performance could be achieved with aZero-IF system and to compare these results with a conventionalsuperhetrodyne receiver such as the AN/PRC-68. The preselector, RFampilfier, and mixer circuits were of a conventional design such asthat used on many ITT programs. The deliverable breadboard uses asignal generator as a local oscillator.
2.1 DESIGN SPECIFICATIONS AND PROGRAM DESCRIPTION
The Zero-IF receiver breadboard was designed to meet thespecifications shown below in Table 2.1-1. These specifications wereconsidered design goals inasmuch as the Zero-IF system represents anovel approach to receiver design. Lach was met or exceeded.
Table 2.1-I. Zero-IF Specifications (Design Goals)
Sensitivity (10 d8 SlUA) -113 d~m
Adjacent Channel Rejection 70 d3
Selectivity ( 6 db down) > lb kHz
Spurious Responses -60 di3
Local Oscillator Radiation <-73 dBm
This program resulted in the development and demonstration
of both an analog and digital demodulation systems.
2.2 TECHNICAL APPROACH
At the beginning of the program, a complete Zero-IFreceiver was designed. The demodulator section used a PLL demodulator.This receiver was tested and met the goals set for it. The PLL demodu-lator section was then put aside, and a digital demodulator wasdesigned. The receiver was again tested, and again met the goals set
L.... .__
for it. Figure 2.2-1 is a general block diagram of the breadboardedreceiver. It consists of the receiver front end, IF filters, IFAmplifiers, the demodulator, and audio circuits.
2.2.1 Preselector Filters
The block labeled as number 1 in Figure 2.2-1 representsthe preselector filters. The requirements of the preselector filtersfor a Zero-IF receiver are similar to the requirements of the filtersfor an up-converter. That is, the filters need only be designed tosuppress third-order mixing products to ensure sufficient attenuationfor all order products. These filters usually have a bandwidth of onehalf octave. Therefore, only three filters are required to cover the30 to 88 MHz band. Several versions of RF band filters were checkedout. A combination low pass and high pass was chosen because a band-pass filter yielded undesirable component values. In addition, the lowpass - high pass combination is more desirable for future transceiverapplications in which the transmit path includes only the low passfilter. Figure 2.2.1-1 is a block diagram of the preselector. In thefigure, the switches shown represent PIN diodes which are controlled bythe band select switch on the front panel of the radio. Note on theschematic, page A-2 of Appendix A, each filter has a PIN diode on bothits input and its output. A -15 Vdc level is forced on the PINdiodes when a particular band is not desired. This dc level causes thediode to be reverse biased and, therefore, effectively no signals arepassed in that particular band. The selected band, on the other hand,has a +11 Vdc level forced on it because the voltage divider consistsof the 10 K and 1.5 K resistors. The positive dc level forward biasesthe diodes on the selected band, thereby enabling the signals in thisband to be passed on to the RF gain/attenuator stage. Tables 2.2.1-1through 2.2.1-3 are lists of the filter responses for the three bands -
30-43 MHz, 43-62 MHz, and 62-88 MHz. Figures 2.2.1-2 through 2.2.1-4are plots of the data.
2.2.2 RF Amplifier and RF AGC Circuits
The block labeled as number 2 in Figure 2.2-1 representsthe RF amplifier and RF AGC circuits. These circuits contain twohybrid amplifiers (Part numbers QBH-102 and QBH-104 from Q-bit Corp.)and a PIN diode attenuator. Figure 2.2.2-1 is a block diagram of theRF Amplifier attenuator board. Schematics of these circuits can befound in Appendix A. Page A-3 is a schematic of the RF amplifier andattenuator, while Page A-4 is a schematic of the RF attenuator controllogic. Each amplifier has 12 dB of gain. The PIN diode attenuator has48 dB of attenuation and is controlled by the baseband AGC circuits.Table 2.2.2-1 shows the amount of attenuation of each step for threedifferent frequencies. Without this attenuator, the maximum on-channelinput signal that the receiver can handle without distortion is -40dBm. With the addition of this circuit and the RF gain control, thereceiver is able to operate with signals up to 0 dBm. It has beendesigned in a bridge-T configuration which maintains a good VSWR(better than 2:1) for all levels of attenuation. This is most impor-
4
I-CD
x
LJ
0o
0co
L) 0Lo -4
o-j 0
Le))
-m 0 -
0 0
CDI z
830] 3-2
5 L
_k ,.TO RF GAIN/AGC
Figure 2.2.1-1. Block Diagram of Preselector Bandpass Filters
6
Table 2.Z.1-1. 30-43 Miz Preselector Filter Response
lrequency (Mlz) kilter Response (db)
3.000 -46.80
7.000 -41.80
12.000 -48.70
18.000 -55.20
22.000 -25.30
27.000 -4.00
32.000 -1.30
36.000 -1.50
41.000 -1.3U
4b.O0 -. 70
51.U0 -18.70
56.000 -34.50
60.000 -46.40
65.000 -40.80
69.000 -41.40
74.000 -44.90
84.000 -47.40
89.000 -50.30
94.000 -53.40
98.000 -5b.80
103.000 -b0.bO
107.000 -64.60
112.000 -bb.40
7
Table 2.2.1-2. 43-bb Mhz Preselector Filter Response
Frequency (MHz) Filter Response (dB)
3.000 -49.60
8.000 -42.20
12.000 -41.80
18.000 -46.80
23.000 -56.b0
27.000 -51.30
32.000 -28.00
36.000 -8.70
41.000 -1.20
46.000 -1.00
51.000 -1.40
56.000 -1.40
bl.000 -1.00
65.000 -1.30
70.000 -5.50
74.000 -13.50
79.000 -22.20
84.000 -31.00
89.000 -41.70
94.000 -62.50
98.000 -48.80
103.000 -4b.40
108.000 -46.00
112.000 -46.50
8
Table 2.2.1-3. 62-88 Mz Preselector Filter "esponse
Frequency (Mktz) Filter Kesponse (db)
3.000 -54.40
8.000 -46.20
12.000 -44.10
17.000 -44.70
22.000 -49.50
27.000 -65.60
32.000 -44.80
36.000 -39.30
41.000 -39.10
46.000 -38.20
51.000 -17.bO
56.000 -5.20
61.000 -I.I0
65.000 -1.20
70.000 -1.60
74.000 -1.50
79.000 -1.20
84.000 -1.10
89.000 -1.50
93.000 -Z.60
99.000 -7.60
103.000 -Ib.40
108.000 -2b.IU
112.000 -38.80
9
10
-10
-30
-50
-70
1 31 61 91 121
FREQUENCY (MHz)
Figure 2.2.1-2. Zero-IF Preselector Filter Band I
10
-10
~-30
-50
-70
1 31 61 9112
FREQUENCY (MHz)
Figure 2.2.1-3. Zero-IF Preselector Filter Band 2
11
10
-10
-30
~-50
-70
31 61 91 121
FREQUENCY (MHz)
Figure 2.2.1-4. Zero-IF Preselector Filter Band 3
12
+12 dB 48 dB IN 12 dB +2d
FROM BASEBAND ACATTENUATOR
0 CONTROL
Figure 2.2.2-1. Block Diagram of RE Amplifier Attenuator Board
13
JA
tant at the 0 dB attenuation setting because any loss under low signalconditions will add to the noise figure of the receiver. The atte-nuator control logic controls the PIN diode attenuator. It is anextension of the baseband AGC circuit and consists of a shift registerwhich steps the PIN diode attenuator in four 12 dB steps. This processdoes not begin until the baseband AGC reaches its maximum attenuationand, therefore, the receiver noise figure is not degraded except athigh signal inputs where noise figure is not a concern. For moredetail on how this circuit operates, see section 2.2.7.
Table 2.2.2-1. RF Amplifiers with PIN Diode Attenuator
Conditions: -20 dBm input from HP8640 signal generator and output ter-
minated by 50 ohm load of Boonton RF voltmeter.
30 MHz 59 MHz 88 MHzAttenuation Output Amount Output Amount Output Amount
Step Level of Atten. Level of Atten. Level of Atten.(dBm) (dB) (dBm) (dB) (dBm) (dB)
0 2.9 - 2.7 - 2.6 -
1 -9.4 12.3 -9.6 12.3 -9.6 12.2
2 -21.6 24.5 -21.8 24.5 -21.6 24.2
3 -33.0 35.9 -32.4 35.1 -30.8 33.4
4 -44.0 46.9 -43.5 46.2 -40.0 42.6
2.2.3 Signal Splitter Circuit
The blocks labeled 3, 4a and 4b in Figure 2.2-1 comprise
the signal splitter circuit. The signal splitter circuit consists of apower splitter and two mixers. The primary concern was to match signalamplitude and phase in the two signal paths. A Merrimac (PDS-20-50)power splitter and two Mini-Circuits (MCLSBL-1) mixers are the partsselected for this circuit. Figure 2.2.3-1 is a block diagram of thesplitter/mixer circuit. A schematic of this circuit can be found onpage A-5 of the Appendix. In the circuit, the -3 dB power splitter(block 3) splits the desired signal into two in-phase signals. Thesesignals are then mixed with the two quadrature signals from the localoscillator circuit described in section 2.2.4. The output of eachmixer (blocks 4a and 4b) is a baseband signal along with a signal whosefrequency is twice the local oscillator frequency. The undesiredsignal, that signal which is at twice the local oscillator frequency,is then filtered out using the baseband filter described in section2.2.5.
14
BASEBAND I CHANNEL
I CHANN L LO IN
RF INPUT -3 d8 -------------POWER
SPLITTER
CD
Q CHANNEL LO IN
BASEBAND CHANNEL
Figure 2.2.3-1. Block Diagram of Splitter/Mixers
15
2.2.4 Quadrature LO Circuit
The block labeled number 5 in Figure 2.2-1 is a 90 degreepower splitter/combiner. This is an off-the-shelf part which is usedto provide the two quadrature local oscillator (LO) signals. Blocknumber 6 represents an RF signal generator external to the breadboardwhich is used as the LO. By running the LO through the splitter/combiner, two quadrature signals are generated that are then suppliedto the mixers shown in the schematic of the signal splitter circuit onpage A-5 of the Appendix. An Anzac part (JH-131) was selected to per-form the function of block number 5.
2.2.5 Baseband Filter
The channel bandwidth is defined by the baseband filters.The baseband filters are passive with a cutoff frequency of 8 kHz. InFigure 2.2-1, they are represented by blocks 7a and 7b. The schematicfor this circuit can be found on page A-6 in the Appendix. note thatthese filters are seven-pole filters. It was necessary to use a seven-pole filter in order to achieve an adjacent channel attenuation of70 dB. The component values for these filters were carefully calcu-lated and the final circuit is composed of close tolerance parts (onepercent) selected to be as close as possible to the calculated valuesso that both filters are identical. Table 2.2.5-1 shows the frequencyresponoe of this circuit. Figure 2.2.5-1 is a plot of this data.
2.2.6 Low-Noise Amplifier
The blocks labeled as numbers 8a and 8b in Figure 2.2-1represent the low noise amplifier for each channel. Figure 2.2.6-1 isa block diagram of the circuit. A schematic can be found on page A-7in Appendix A. The first stage of the low-noise amplifier is a 1:40step-up transformer. A low-noise op-amp follows the transformer. Thefrequency response of this circuit was adjusted to decrease the noisebandwidth. The modifications consisted of adjusting the compensationcapacitor on the first amplifier and adjusting the feedback (gain)of the second active filter stage. Note the power supply lines arealso filtered. Figure 2.2.6-1 is a block diagram of the low noiseamplifier. Table 2.2.6-1 is a table of the frequency response of thiscircuit. Figure 2.2.6-2 is a plot of the data.
2.2.7 Baseband AGC
The block labeled as number 8 in Figure 2.2-1 representsthe baseband AGC circuits. As shown in the schematic on page A-8 ofthe Appendix, the baseband AGC circuits are made up of a digital stepattenuator followed by a compression amplifier. The digital step atte-nuator switches in or out attenuation in 6-dB steps, depending on therectifier/detector circuitry. When all eight steps (48 dB) areswitched on, a "carry out" bit goes to the RF attenuator control logic.When the rectifier/detector indicates more attenuation is necessary,the RF attenuation is used in the same manner. When the
16
Table 2.2.5-1. Channel Filter Frequency Response
Amplitude Response Amplitude ResponseFrequency Channel I Channel 2
(iz) (d]) (dlB)
5 -1.2 -1.310 -1.5 -1.b50 -1.4 -1.550 -1.4 -1.5
500 -1.4 -1.51 K -1.2 -1.32 K -.6 -.73 K 0 -.14 K 0 -5K -.4 -.5b K -1.2 -1.37 K -1.7 -1.8
7.5 K -1.5 -1.68 K -1.5 -1.6
8.5 K -1.7 -I.b9 K -2.7 -3.3
9.5 K -4.7 -5.410 K -7.8 -7.7
10.5 K -9.8 -10.71 K -13.5 -14.212 K -18.6 -18.913 K -22.8 -23.314 K -26.b -27.315 K -30.6 -31.3
20 K -46.6 -46.925 K -63.2 -53
27.9 K -70.4 -80.5
29 K -77.4 -7b.831 K -72.6 -72.5
32.6 K -71.4 -71.535 K -71.5 -71.540 K -7b.3 -76.345 K -81.b -81.5
17
LZ.
- "WaS
83013-08
18_________________________
Figure 2.2.6-1. Block Diagram of the Low-Noise Amplifier
19
Table 2.2.b-1. Frequency Xesponse Lero-lk eceiver Low
Noise Amp input Voltage 3 mVrms.
krequency (kiz) Uutput Voltage (Vrms) dh (I kHtz)
5 b.1 -. 5
1U b.3 -. 3
5U b.4 -.1
100 b.4 -.1
4UU b.5 U
iK b.5 0
2K b.4 -.1
3K b.3 .34K b.2 .5
5K 5.9 -L.0DE 5.b -1.4
7K 5.2 -2.0
8K 4.9 -2.b9K 4.4 -3.5
IK 4.2 -4.015K 2.8 -7.b20K 2.0 -10.4
30K 1.75 -15.7
50K .195 -30.b
20
- - - - ZH 0008 -
__L2
177..
J(qP) 39viinA ifldinnf 83013-09
21
rectifier/detector indicates less attenuation is necessary, attenuationis switched off in exactly the reverse order that it was switched on.In other words, if a starting point of no attenuation on is used, theleast significant bit of attenuation is switched in and more asnecessary. When less attenuation is needed, the mst significant bitthat was switched in is then switched out down to the least significantbit. The attenuation control logic also disables itself whenever therectifier/detector indicates more attenuation is necessary and allattenuation is switched on, or whenever the indication is for lessattenuation and all attenuation is switched off. Furthermore, therectifier/detector has a window of 18 dB to ensure that the AGC circuitdoes not bounce between two steps of attenuation. In addition, thecompression amplifier provides a constant level output for the varian-ces that will occur with signal level variances not exactly equal toone step of attenuation. Overall, the AGC circuits provide 116 dB ofattenuation, 48 dB at RF and 48 dB at baseband in step attenuation with20 dB in the compression amplifier. Figure 2.2.7-1 is a block diagramof this circuit.
2.2.8 Demodulator
Block number 9 in Figure 2.2-1 represents the demodulator.Section 3 is a discussion on the analog demodulator. Section 4 coversthe digital demodulator. Please refer to these sections for infor-mation on the demodulation processes.
2.2.9 Audio Circuits
The final section contains the audio circuit, which isrepresented by block number 10 in Figure 2.2-1. As shown in the sche-
matic on page A-I of the appendix, the audio circuits are made up of alow-pass, high-pass filter and a speaker amplifier. The filter sectioncreates a bandpass (3 dB) from 350 Hz to 3 kHz, and the speakeramplifier delivers 1/2 Watt to an 8-ohm speaker. A block diagram ofthe audio circuit board is shown in Figure 2.2.9-1. Table 2.2.9-i is aset of frequency response data for this circuit. Figure 2.2.9-2 is aplot of the data. Table 2.2.9-2 is a set of data showing the distor-tion of the audio filters.
22
LOW NOISE COMPRESSIONAMPL IFI ER AMPLI FIER
CHANNEL. ATTENUATIONBCAN 46 dB IN
ATTENUATION LEVELCONTROL DETECTOR
Q CHANNEL ,48 dB IN No "'
6 dB STEPS
LOW NOISE COMPRESSIONAMPLIFIER AMPLIFIER
,3
Figure 2.2.7-1. Block Diagram of Baseband AGC
23
AUDIO INACTIVE RCIEAUIOI BANDPASS SIGNALFILTER
AUDIO AM4PLIFIER
Figure 2.2.9-1. Block Diagram of Audio Circuits
24
Table 2.2.9-1. Frequency Kesponse of Audio Filters
Input Voltage = U.6b mVrms,
Frequency (hz) Output Voltage (Vrms) df
5 0.72 mV -b8.9
10 2.2b mV -58.9
20 11.0 mV -45.230 27 mV -37.440 52 mV -31.7
50 84 mV -27.5b0 0.125 -24.1
70 0.17 -21.4
80 0.23 -18.890 0.295 -16.6I00 0.3b2 -14.8120 0.54 -11.4150 0.82 -7.7175 1.075 -5.4200 1.32 -3.6300 1.875 -0.b
400 2.00 -0.0500 2.00 -0.01K 1.95 -0.22K 1.875 -0.6
3K 1.55 -2.24K 1.06 -5.55K 0.74 -8.bbK 0.51 -11.77K 0.38 -14.48K 0.29 -16.89K 0.23 -18.810K 0.185 -20.715K 0.085 -27.420K O.051 -31.730K 0.026 -37.7
Table 2.2.9-2. Percent of Uistortion of Audio Filters
Output Frequency ThiL (I.)
300 tiz 0.2451 K iz 0.1583K ltz 0.044
25
AJ.
14.
0
(9P 0OiO nio8031
26'
Section 3
ANALOG DhMODULATOK
In an FM demodulation system using the Zero-IF concept,the RF carrier and double-sideband modulation spectrum are linearlytranslated to zero IF frequency by an asynchronous local oscijlator (atthe same frequency of the RE carrier). This causes the lower sidebandof the RF signal to be folded over exactly on top of the upper sidebandat the IF frequency. This folding of the RE spectrum requires someform of novel processing to demodulate the overlapping baseband infor-mation.
This superposition of sidebands can be resolved by usingtwo quadrature baseband IF channels, each covering the frequency rangeot zero (dc) to half the original RF channel bandwidth. See Figure3-I. A decision as to the original position ot the RF signal relativeto the local oscillator reterence can be made by comparing the phase ofthe signals in the two channels. When the trequency modulated RFsignal is higher in frequency than the local oscillator, the two signalphasors at points (I) and (2) will be rotating faster than the localoscillator reference phase. When they are translated to baseband bythe local oscillator, which atfects both in a similar way, the signa-in channel (1) will lead that in channel (2) by n/2 radians. When theRE signal is lower in frequency than the local oscillator, the two KFphasors (1) and (2) are rotating slower than the local oscillatorreference and, therefore, channel (1) will lag channel (Z) by n/2radians.
The two quadrature baseband signals are then filtered toremove the upper sideband of the mixing process (approximately twicethe local oscillator frequency) and to define the noise bandwidth ofthe receiver.
A frequency discriminator is connected to the output otthese two filtered baseband channels; this produces a dc voltage with amagnitude proportional to the frequency that the slowly moving Kcarrier has deviated trom the local oscillator and a polarity deter-mined by the relative phase of the two baseband channels.
Originally, a sine-cosine frequency discriminator was pro-posed tor the Zero-IF receiver study. T'he sine-cosine demodulator is aclassical design that is relatively easy to analyze and understand.Figure 3-2 is a block diagram o the sine-cosine demodulator. It con-sists of two differentiators, two linear four-quadrant multipliers, anda summing network.
The operation of this sine-cosine discriminator can bevisualized by considering the KF carrier to be initially higher thanthe local oscillator frequency by 6w. Figure 3-2 shows an instan-taneous view of these signals. Note that channel (1) leads channel(2). The output trom ditferentiator (I) is equal to channel (2), but
27
J ) i i ii ,
iM
CHANNEL 1
rtx ~LOCAL OSCILLATOR
-- 12 J - - HANNEL 2
(A) Filter Bandwidths
0 © 0 0
L.O. REFERENCE L.O. REFERENCE
RF SIGNAL HIGHER IN RF SIGNAL LOWER INFREQUENCY THAN L.O. FREQUENCY THAN L.O.
-4
(B) Phasor Diagrams
Figure 3-1. Filter Bandwidth and Phasor Diagram
28
a cos dw M3
dt adw cos dw
d / -adw sin dw / 2dt a dw
a sin dwd7-a dw sin dw
M4
Figure 3-2. Demodulator Output (Positive Output)
a cos dw M3
dt-a 2dw cos d
/
d-ads sin idn
+2 2 2+a dw sin dw -a dw
IM 4
Figure 3-3. Demodulator Output (Negative Output)
V
/o /
/
Figure 3-4. Discriminator Characteristic
29
is phase shifted by n/2 with amplitude proportional to its frequency(6w). The output of differentiator (2) is similar. Multiplier M3linearly multiplies its two inputs to produce an output at twice theinput frequency which has an amplitude linearly proportional to theoriginal input frequency (6w). The amplitude also depends upon thesquare of the original input signal level (a). Multiplier M4 producesa similar output of opposite polarity, lagging in phase by 1T/2.
Figure 3-2 shows that the combination of the two waveformsproduces a dc voltage (cos 2 6w + sin 2 6w = 1) of amplitude proportionalto 6w, the original input frequency (difference frequency of RF andlocal oscillator) and to the square of the input amplitude. Figure 3-3shows that the RF carrier is lower in frequency than the local oscilla-tor by 6w; the frequencies in the two channels are the same as in theprevious case, but channel (2) now leads channel (I). The circuit per-forms as before, but it now generates a negative dc voltage. Figure3-4 shows the complete discriminator characteristic.
Using these techniques to construct a practical FMreceiver, it is necessary to include some means of maintaining aconstant audio output level for widely varying input RF levels. Anautomatic gain control (AGC) circuit could be implemented at either RFor baseband. To minimize power consumption, the latter is preferred.Although this is an FM system, limiting amplifiers are not acceptablebecause the differentiators will produce spikes with amplitudes depen-dent only upon the slew-rate of the square waves (from the limiters)and not their frequency. This demodulation scheme is completed byadding a post-detection filter after the summer; the filter's solefunction is to define the output noise bandwidth and not to reconstructthe modulation (Figure 3-5).
Although the sine-cosine demodulator is practicallyfeasible, it was abandoned for the Phase-Locked-Loop (PLL) approach foranalog demodulation at the beginning of the program. The PLL systemwas designed and breadboarded because it requires less accurate phaseand amplitude balance between the I and Q channels and, because it is afeedback system, it has slightly better performance at low signal-to-noise ratios.
3.1 PHASE-LOCKED-LOOP DEMODULATOR
The phase-locked-loop (PLL) demodulator is actually quitesimilar to the sine-cosine demodulator. Figure 3.1-1 is a simplifiedblock diagram of both the sine-cosine and PLL demodulators. Both demo-dulators cross multiply both channels by the derivative of the otherchannel. The Sine-Cosine demodulator derives this differentiatedsignal directly with a differentiator circuit, much as that used inanalog computers. The PLL demodulator uses an indirect approach.
This is a Type I PLL, which consists of one integrater in theloop, which is the voltage controlled oscillator (VCO). The referencesignal for this PLL is a free-running oscillator, at the same nominalfrequency of the VCO. The mixed output of the VCO and the free-running
30
CL''--
ID~
C-4I
-4 -4
-4E C
-
:30 83013-19
31
SINE-OSINEPHASE-LOCKED LOOP
- AUD+ + -
Figure 3.1-1. Analog Demodulators
32
oscillator with no modulation and no frequency error is a dc level. Ifmodulation or a frequency error exists, these outputs are the deriva-tives of the I and Q channels as in the sine-cosine demodulator.
The PLL is a Type I (I integrater) second order (2 poles)PLL. The characteristics of the desired response were derived by usingtechniques presented by Gardner in Phaselock Techniques, using thefollowing equations.
(PLL loop damping ratio) = I
Bi (channel bandwidth) =16 kHz
D (modulation index) = 1.66
wn(min) (min PLL natural frequency) =
iT Bi D ' /
(- - 2 + 1-2 )2 + 1 + -
or wn (min) = 103,555 radian
Figure 3.1-2 is a Bode plot of the open loop gain of thephase-locked-loop demodulator.
3.2 ANALYSIS OF PHASE-LOCKED-LOOP DEMODULATOR
Figure 3.2-1 is a general, block diagram of the PLL demodu-lator. For analysis purposes, each of six mixers or multipliers areassumed to be ideal four quadrant linear multipliers. The followingmathematical analysis describes the operation of the Zero-IF phased-locked-loop demodulator. As shown in Figure 3.2-1, the frequency modu-lated input signal is given by
AW
S = AcCOS(wct + - SIN pt)P
where
Ac is the amplitude of the signal,
Wc is the carrier frequency,
Aw is the peak deviation, and
p is the frequency of the modulating audio signal.
33
JFI
_ _ _ _ _ AME ___ ~7
_______ _____I
---- ---- -
Law, A 34 i @gegg mg N
I EMM 0 "Fpp
tc
lif-! F
34
_j c
CD C)
oo Ct,
W 0-
qt Cl
LArc-CD (.
LA L
0 +
aa
cli ua)_j A l
06 A
0C-D
U- _j llj . 39
The signal is converted to baseband by mixing with thelocal oscillator in mixers M 1 and M2. Baseband signals X1 and X2 arein phase quadrature because of the 90' phase shift provided in thelocal oscillator signal applied to M i.
X1 is given by
XI - ACSINwot COS (wct + A- SIN pt)P
where
Wo is the frequency of the local oscillator.
Expansion yields
X, = 2ArSIN(wo t + wct + ALSIN pt) + Ar-SIN(wot - wct - AwSIN pt)
and
Ac AP P
The lowpass filters, FLI and FL2 , remove the sum productsof Xj and X2 and at the output of the filters, the baseband signals aregiven by
Y1 = -SSIN(wot - Wct - A--SIN pt)2 P
Ac -A
Y2 = :-COS(wot - wct - AwSIN pt)P
These two quantities are the inputs labeled I and Q on the schematic onpage A-9. Let the output of the voltage controlled oscillator (VCO)shown on the schematic on page A-10 be
V - AvCOS(wvt + a)
where
8 is the phase,
Wv is the frequency of the VCO, and
AV is the amplitude.
36
The signals, W1 and W 2 , are quadrature baseband signalsderived from mixers M3 and M4 by mixing the quadrature components ofthe reference oscillator with the output signal of the VCO.
w Av + + + Av- -)
Av Av
W2 = SIN(w t + wvt + ) + A--SIN(wat - (wvt - 5)
The lowpass filters, FL3 and FL4 , remove the sum productsand U 1 and U2 result.
U, = zOS(wt - wvt - 8) and
U2 = -v SIN(wt - wvt - 8).
U1 and U2 are the outputs of the circuit shown on theschematic on page A-I of the appendix. The baseband signals Z1 andZ2 are the result of mixing Y1 and U1 in M5 and Y2 and U2 in M6.These mixers are shown on page A-10. Z1 is given by
Z 1 = AcAvSIN(wot - wc t - AwSIN pt)COS(,,t - wvt - 5)
Z1 = AcAvSIN(wot - Wct - AwSIN pt + wkt - vt- )P
+ -vSIN(wot - wct - A-SIN pt - w t - wvt + 8).P
Similarly,
-AcAv
Z2 SIN(wot - wct - ASIN pt + wt - t
8 SIN(wot - uct - A-SIN pt - Wat + w t + 8).8 P
At the output of the voltage comparator
Z2-z - AV SIN(wot - wct - A-SIN pt - wat + wvt + 8)74
The last equation is the SIN of the phase error in thephase-locked loop. For a locked condition, the argument must be zeroand
L- SIN pt - wot + Wct + Wat - WvtP
The VCO is an integrator and the phase of the VCO signal isthe integral of the control line voltage, VCo; therefore,
Vc = __
where
k is a constant describing the VCO.
Vc is then
Vc = kAwCOS pt - wo + Wc + Wa - Wv
The recovered audio signal is the first term of the last
equation and is the output labeled VCO control on page A-10. Theremaining terms are dc components and are used for AFC as shown by theAFC output shown on page A-10.
The recovered audio signal is independent of the level of
the input signal, S, and only dependent on Aw which are the require-ments for a demodulated FM signal.
3.3 ANALOG ZERO-IF RECEIVER BREADBOARD
The analog receiver developed under the original contractwith CECOM uses a PLL circuit for demodulation. As indicated, the PLL
approach was chosen over the sine-cosine demodulator because of itsreduced sensitivity to phase and amplitude mismatch between the twochannels. Figure 3.3-1 is a block diagram of the analog Zero-IFreceiver. It consists of three major sub-assemblies, the RF circuits,baseband circcuits and analog demodulator, each discussed previously.As shown later, the RF circuits and basebands circuits are identical tothe digital zero-IF receiver. The breadboard model has only two frontpanel controls, volume and preselector hand selector. The preselectorbands are
1) 30-43 MHz2) 43-62 MHz
3) 62-88 MHz
The breadboard also includes a rear panel 50 ohm jumper
between the output of the preselector and the input of the RFamplifier. This jumper may be removed to evaluate the receiver at fre-quencies other than 30 to 88 MHz. The RF circuits will provide reaso-
nable performance from 20 to 200 MHz.
38
-Jw
CC
U~j 0
uj -X
Li
83013-16
39N
3.4 TEST RESULTS - ANALOG ZERO-IF RECEIVER
This analog Zero-IF receiver breadboard was formally testedon July 29, 1982. The test data is shown below. The results of thesetests demonstrate excellent performance. The goals for the variousparameters are based on the performance achieved by the AN/PRC-68. Theparagraph numbers are referenced to the test plan.
40
4.0 RECEIVER TEST PROCEDURE DATA SHEETS FOR ZERO-IF RECEIVERSTUDY
4.1 a) Unit: Zero-IF Receiver Breadboard
4.2 b) Tested by:
Date:
4.3 c) Witnessed by:
4.4 Test Data
4.4.1 SensitivityRF Level For
Test Frequency 10 dB SINAD Goal
30 MHz -118 dBm <-113 dBm
43 MHz -120 dBm <-113 dBm
59 MHz -120 dBm <-113 dBm
62 MHz -120 dBm <-113 dBm
87.975 MHz -120 dBm <-113 dBm
4.4.2 Audio Distortion
Modulation Measured
Frequency Distortion Goal
300 Hz 3.1% THD <10% THD
I kHz 3.2 % THD <10% THD
3 kHz 3.8 % THD <10% THD
4.4.3 Audio Frequency Response
Level of demodulated one 1 kHz tone 1.65 Vrms. 1.5 Vrms +20%
Frequency of -3 dB Points
Upper -3 dB 3200 Hz 3000 Hz + 20%
Lower -3 dB 215 Hz 250 Hz + 20%
Ripple 0.3 dB <2 dB
41
4.4.4 AGC Range
RF Signal Audio Output AudioLevel (dBm) Level (Vrms) SINAD (dB)
-110 1.65 22.8
-100 1.65 28.5
-90 1.65 29.2
-80 1.66 28.8
-70 1.67 30.0
-60 1.66 29.6
-50 1.66 29.7
-40 1.65 29.5
-30 1.66 29.6
-20 1.66 29.6
-10 1.66 29.5
0 1.66 18.4
4.4.5 Spurious Response
10 dB RequiredLO SINAD Spurious Spurious Spurious Goal (dBs
Freq. LEVEL Frequency Level Rejection is dB above(MHz) (dBm) (MHz) (dBm) (dB) Sensitivity)
30 -116 60 -10 106 >60 dBs
43 -118.5 86 -28.5 90 >60 dBs
62 -120 124 -18.5 101.5 >60 dBs
42
4.4.6 LO Radiation
Level At
Frequency Antenna Port Goal
30 MHz (-100 d=m <-73 dBm
59 MHz <-100 dBm <-73 dBm
87.975 -99 dBm <-73 dBm
4.4.7 Receiver Selectivity
Signal Generator #2 116.5 dBm (10 dB SINAD) +5 dB - -111.5 dBm
Frequency of Level of Rejection
Signal Generator Signal Generator (dB)
#1 #1 (Gen #1 - Gen #2)
49.0 MHz -11.5 dBm 100
54.0 MHz -11.5 dBm 100
58.0 MHz -15.5 dBm 96
58.8 MHz z -20.0 dBm Z 91.5
58.9 MHz -25 dBm 8b.5
58.95 MHz -13.0 d~m 98.5
58.975 MHz -19.0 dBm 92.5
59.025 MHz -18.0 dBm 93.5
59.050 MHz -17.5 dBm 44.)
59.1 MHz -20.0 dBm 91.5
59.2 MHz -20.0 dBm 91.5
60 MHz -13.0 dBm 98.5
64 MHz -11.0 dBm 100.5
69 MHz -7.5 dBIm f14.
43
Section 4
DIGITAL DEMODULATOR
The most significant advantage of digital demodulation ofFM signals is that digital integrated circuit technology is well estab-lished. This means that a complete demodulator could be fabricated ona single chip, requiring a minimum number of external components. Assuch, this chip would form the heart of a small, low cost transceiversystem. Every Zero-IF demodulation technique involves using an inphase(I) and a quadrature (Q) channel because the lower sideband is foldedover on top of the upper sideband. To extract the modulation and toeliminate the beat frequency between the local oscillator and inputfrequency these two channels (I and Q) are necessary.
There are various approaches to digital demodulation ofZero-IF signals, each using different algorithms and having differentadvantages and disadvantages. Each approach, however, does requirethat the baseband channels be converted to a sequence of binary numberpairs by an A to D converter. Then, each binary number represents an Iand Q sample value. The three most promising methods for digital de-modulation of Zero-IF FM signals are as follows:
1. Arctan look-up table
2. Complex multiplication of (I + jQ) and a unit
reference vector. (Vector Processor)
3. Zero crossing system that requires additional basebandchannels.
After the I and Q signals have been digitized, the signalmay be demodulated by any of these three approaches.
Using the Arctan look-up approach, the instantaneous volta-ges of the I and Q channels are represented by two numbers. A ROMlook-up table is used to determine the log of the absolute value ofthese numbers and the signs (+ or -) are stored. After finding thelogs, these numbers are subtracted, smaller from larger, which amountsto dividing the amplitude of the two signals. Information as to whichsignal was larger is also stored. Now, by taking an antilog of thisnumber, the result is I + Q (or Q t I). The phase of the demodulatedsignal is determined by finding the arctan of this quotient withanother look-up table. This results in a number describing the phaseangle between 0 and 45 degrees. This information is expanded to a full3600, based on the sign of the I and Q channels and which was larger.The desired FM demodulation results when successive samples of thephase information are subtracted, which is in essence a discrete dif-ferentiation. The FM output, still digitized, is passed through an D/Aconverter and is lowpass filtered, this provides an analog demodulatedFM signal that may be amplified to drive a speaker or earphone.
44
The vector processor approach is an alternate method, whichdoes not require any division or log look-up tables. Instead it uses asequence of a and b digital pairs representing the rectangular coor-dinates of a unit phasor. These correspond to the rotation of a unitphasor in predetermined angular increments. This sequence of a and bdigital phasor values is multiplied with the I and Q values to obtainthe equivalent of the actual phasor at the instant of the sample. Whenequality is reached, the phasor angle value, which is the address to aROM with the a and b values, is stored. This method, in effect, repla-ces the division operation with two multiplications and an add opera-tion. As in the arctan look-up table approach, successive samples mustbe subtracted to produce the desired FM demodulated signal.
Neither of these digital frequency demodulation methods usefeedback or limiting and, therefore, AM noise contributes to thedetected signal-to-noise and a threshold detection problem exists.However, digital feedback techniques can be applied to the baseband
signals to improve the threshold performance.
The zero crossing approach uses limiting amplifiers. Thisapproach eliminates the need for AGC circuits but reduces the phase-change sampling from continuous to four per cycle. This reduction ofsampling time reduces the ultimate SINAD to about 30 dB. If a cleanersignal is desired, this method could be modified to create more samplepoints with additional channels. This technique is similar to a con-ventional pulse counting FM detector. It has the FM improvement fac-tor, but suffers from reduced zero crossings in the Zero-IF architecture.
Each of these three approaches represent a viable solution
to digital demodulation of Zero-IF FM signals, each with its own par-ticular advantages and disadvantages. Table 4-1 is a summary ofthese tradeoffs.
4.1 VECTOR PROCESSOR
The digital demodulator approach chosen for the Zero-IFreceiver study was the vector processor approach, chosen because itreadily lends itself to large scale integration while still providinggood performance.
Figure 4.1-1 is a block diagram of the Vector ProcessorZero-IF Digital Demodulator. The two sample-and-hold circuits samplethe I and Q channels at a periodic rate. These two samples are thendigitized by the two analog-to-digital converters. The outputs of twoA/D converters represent a complex number of the form I + jQ.
In order to extract the frequency modulation signal fromI + JQ, it is first necessary to calculate the absolute phase of thesignal as a function of I + JQ at the instant in time when the sample-and-hold circuits sample the I and Q baseband channels. This isaccomplished by converting I + jQ to polar coordinates. The result ofthis conversion is the instantaneous amplitude and phase information.
45
Table 4-1. Digital Demodulation Techniques
Approach Advantages Disadvantages
1. Look-up Table e Good voice performance * No FM threshold
a Relatively easy to * Not easily integrated
implement
e Proven concept 9 Not-optimum for data
* Low risk
2. Vector Processor o Fairly easy to * No FM threshold
integrate
* Good voice performance e Not-optimum for data
* Requires microsecond
speed multiplication
3. Zero Crossing * FM threshold * Degrades ultimate
SINAD
* Eliminate AGC
* Good data performance
46
The block labeled as d/dt in Figure 4.1-1 takes the derivative of thephase with respect to time; this provides a frequency or FM output as adigital number. The d/dt function is accomplished by subtracting suc-cessive samples of the phase. A digital-to-analog converter then pro-vides an analog voltage that drives a conventional audio amplifier andspeaker.
4.2 EXPLANATION OF VECTOR PROCESSOR
The primary function of the Vector Processor portion of thedigital demodulator is the rectangular to polar conversion of the I andQ signals. This conversion must be done every 25 microseconds (40 kHzsampling rate). To perform this conversion at a high speed, a novelapproach is used. Figure 4.2-1 is a block diagram of the vector pro-cessor and Figure 4.2-2 is a flow chart of digital demodulation using avector processor. The operation of the vector processor is summarizedas follows.
STEP 1: The I and Q channels are split into two paths on
board I of the vector processor (See page A-13).
STEP 2: Continuing on board 1, one path determines if theamplitude of I and the amplitude of Q is positiveor negative. This information is used later.
STEP 3: The remaining paths take the absolute value(magnitude) of I and Q.
STEP 4: 1 and Q are converted from an analog to a digitalsignal (sample and hold, than A to D) and sent toboard 2 of the vector processor (page A-14).
STEP 5: I and Q are tested to see which has the greater
magnitude. The lesser is now called b. Thismagnitude information is used later.
STEP 6: The lesser value is sent to a magnitude comparatorand the greater value to a multiplier.
STEP 7: A Johnson counter from board 4 (page A-16)addresses a lookup table which stores the tangentof an angle, d, for d = 0 thru 45 degrees. Thegreater of I and Q is multiplied by the tangentfrom the lookup table. This becomes a.
STEP 8: Now a and b are tested to see which has thegreater magnitude.
If a < = b go to step 9aIf a > b go to step 9bThis magnitude information is sent to board 4.
47
LLJ (-)CD4
0 I-
F- -)4
C)) S.
cm (m 0
u-4
cx0
-:x4
cz 0 0
rx.
830 13-20
48
SIGN I
IROUTING OCTANT OCTANT
DGTZDb RESOLVER RSOLVE 00-3600
Figure 4.2-1. Vector Processor Block Diagram
49
MAGNITUDECOMPARE
___________CONTROL
LOOK UP COUNTERTABLEH
LATCH CONTROLPHASEREGISTER
PHASEREGISTER
_____[UE SIGN Ilo SIGN Q______________ > Q OR Q > I
co AND COUNTER OUTPUTTO OETERMINE'9
Figure 4.2-2. Vector Processor Flow Chart
50
STEP 9a: Store a "I" in the current test bit position ofthe phase register on board 4. Go to step 10.
STEP 9b: Store a "0" in the current test bit position ofthe phase register on board 4. Go to step 10.
STEP 10: Let the counter move one count to the next leastsignificant bit. If the bit just tested was the
least significant bit, latch the phase registeroutput. Go to step 11. If not, multiply thegreater of I and Q again by the lookup table out-put. Go to step 8.
STEP 11: The output of 10 is , an angle in the first
octant (I and Q are both positive with I greaterthan Q). This angle plus the output of step 2 andstep 5, which define the eight octants, results in8, which is the instantaneous phase of theincoming signal.
On board 3 (page A-15), the output 8 is then differentiatedby subtracting successive samples of the phase information. A digital-to-analog converter then provides an analog voltage that drives anaudio amplifier and speaker.
4.3 DIGITAL ZERO-IF RECEIVER
The digital receiver developed under the add on contractwith CECOM uses a vector processor for digital demodulation. As indi-cated, the vector processor approach to digital demodulation was chosenover the Arctan lookup table and zero crossing approaches because ofits good performance and ease of integration. Figure 4.3-1 is a blockdiagram of the digital Zero IF receiver. As can be seen by comparingthis figure with the figure of the analog receiver (Figure 3.3-1), theRF and baseband gain circuitry are the same. This enables the digitaldemodulator and analog demodulator circuit cards to be interchanged inthe deliverable breadboard. This change can be accomplished by merelyremoving one set of circuit cards and replacing them with the otherset.
4.4 TEST RESULTS: DIGITAL ZERO-IF RECEIVER
The Digital Zero-IF receiver was formally tested on March25, 1982. The test data is shown below. The results of these testsshow good performance. the goals for the various parameters were metor exceeded in every case. The paragraph numbers are in reference toparagraphs in the test procedure.
51
J J ii. .. . .. . j
C)
ICIA
im
Ll
-C4
cz 0
Lwi
Lin
cc 0
-CC4
-4
a)
exi
52
4.0 RECEIVER TEST PROCEDURE DATA SHEETS FOR ZERO IF RECEIVER
STUDY.
4.1 a) Unit: Zero IF Receiver Breadboard
4.2 b) Tested by:
Date:
4.3 c) Witnessed by:
4.4 Test Data
4.4.1 Sensitivity
Test Frequency Measured SINAD Goal
30 MHz -117 dBm <-113 dBm
43 MHz -119 dBm <-113 dBm
59 MHz -119 dBm <-113 dBm
62 MHz -119 dBm <-113 dBm
87.975 MHz -120 dBm <-113 dBm
4.4.2 Audio Distortion
Modulation Measured
Frequency Distortion Goal
300 Hz 4.3 % THD <10% THD
I kHz 2.6 % THD <10% TID
3 kHz 2.2 % THD <10% THD
4.4.3 Audio Frequency Response
Level of demodulated one kilohertz tone is 0.7 Vrms.
Frequency of -3 dB Points Goal
Upper -3 dB 2.4K Hz 3000 Hz + 20%
Lower -3 dB 215 Hz 250 Hz + 20%
Ripple 0.4 dB <2 dB
53
4.4.4 AGC Range
RF SIGNAL AUDIO AUDIOLEVEL LEVEL (Vrms) SINAD (dB)
-110 dBm 0.72 27
-100 dBm 0.72 30.8
-90 dBm 0.72 31.5
-80 dBm 0.72 32.0
-70 dBm 0.72 32.0
-60 dBm 0.72 31.4
-50 dBm 0.72 32.0
-40 dBm 0.72 31.0
-30 dBm 0.72 31.5
-20 dBm 0.72 31.8
-10 dBm 0.72 30.6
0 dBm 0.72 22.4
4.4.5 Spurious Response
10 dB Required SpuriousLO SINAD Spurious Spurious Rejection Goal (dBsFreq. LEVEL Frequency Level (dB) is dB above(MHz) (dBm) (MHz) (dBm) B-A Sensitivity)
30 -118.5 60 -27.5 +91.0 >60 dBs
43 -119.0 86 -27.0 +92.0 >60 dBs
62 -114.0 124 -40 +74, >60 dBs
54
4.4.6 LO Radiation
Level atFrequency RF 1/0 Goal
30 MHz <-90 dBm <-73 dBm
59 MHz <-98 dBm <-73 dBm
87.975 <-92 dBm <-73 dBm
4.4.7 Receiver Selectivity
Signal Generator #2 - -114 dBm (10 dB SINAD) +5 dB - -109 dBm
Frequency of Level of RejectionSignal Generator Signal Generator (dB)
#1 #1 (Gen #1 - Gen #2)
49.0 MHz -10 dBm 99
54.0 MHz -10 dBm 99
58.0 MHz -10 dBm 99
58.8 MHz -20 dBm 89
58.9 MHz -12 dBm 97
58.95 MHz -20 dBm 89
58.975 MHz -29 dBm 80
59.025 MHz -30 dBm 79
59.050 MHz -21 dBm 88
59.1 MHz -13 dBm 96
59.2 MHz -20 dBm 89
60 MHz -10 dBm 99
64 MHz -9 dBm 100
69 MHz -8 dBm 101
55
Section 5
CONCLUSIONS AND RECOMMENDATIONS
The Zero-IF Receiver Study Program has resulted in a bread-board receiver that demonstrates excellent performance for both theanalog and digital demodulators. The breadboard shows that Zero-IF isa viable technology for receiver systems. Both the analog and digitaldemodulators may be integrated into an LSI. The digital system is wellsuited to the universal gate array approach currently used inITT-A/OD's SINCGARS-V system. A preliminary analysis indicated thatthe digital demodulator could be implemented in the standard 400 gatearray and mounted in a chip carrier package less than one-half inchsquare. Similarly, the AGC circuits may be integrated in either 12L,bipolar or CMOS linear arrays. The CMOS array would consume the leastamount of power, but the bipolar offers the lowest 1/f noise. 12Loffers a compromise between the other two.
Integrating these receiver subsystem into an LSI promisesto provide the necessary components for the design of small, low cost,low power radio system. The Zero-IF approach is extremely well suitedto hand-held radio applications that do not require a narrow bandreceiver preselector. The Zero-IF architecture has no image frequencyand a preselector is only required to eliminate spurious responses.The Zero-IF spurious responses are far removed from the desired chan-nel, which permits the use of a fairly broad preselector. Eliminationof a narrow band preselector, either PIN diode switched or varactortuned, significantly reduces the size and cost of a receiver systems.
The Zero-IF architecture, however, is not limited to hand-held FM receivers. For high performance applications, a narrow bandpreselector may be included, with a corresponding increase in size andcost. Additionally, ITT-A/OD has demonstrated that the Zero-IF conceptcan be used for amplitude modulated systems and preliminary analysisshows that any form of modulation can be handled by a Zero-IF system.
The Zero-IF technique is not lirited only to receiver sub-systems. ITT-A/OD has demonstrated an FM modulator that is essentiallya Zero-IF FM receiver in reverse. As in the case of the receiver, thegreatest advantage of this approach is to integrate these circuit func-tions into one or more LSI circuits.
The ITT Corporation, through efforts at the Aerospace/Optical Division and Standard Telecommunications Laboratories inEngland, is devoted to continued development of Zero-IF architecture.The first commercial ITT product using the Zero-IF system is an ultra-miniature radio pager that has been sold in England to British Telecom.Shortly, these pagers will be sold in selected areas in the UnitedStates through Tandy Corporation's Radio Shack outlets for a price of$99.95, which attests to the value of Zero-IF architecture to producesmall, low-power, low-cost radio equipment.
56
Section 6
OPERATIONAL INSTRUCTIONS
The Zero-IF breadboard is a complete receiver system lesspower supplies and local oscillator.
6.1 TEST EQUIPMENT REQUIREMENTS
The following equipment is either required or optional forevaluating the Zero-IF breadboard:
Quantity Description Remarks
2 15 Volt Power Supplies (2A)2 RF Signal Generators (30-88 MHz)I Distortion Analyzer1 Oscilloscope (optional)
6.2 POWER SUPPLY CONNECTIONS
Connect the two 15-volt power supplies as follows:
A. Connect +15 volt line to +15 volt power supply.B. Connect ground to ground lug on +15 volt power supply.C. Connect -15 volt line to -15 volt power supply.D. Connect ground to ground (+ terminal) on -15 volt power
supply.
CAUTION: Double check connection to be sure the rightline is going to the right power supply or else damagemay occur to radio. DO NOT EXCEED + 15 Vdc.
6.3 SIGNAL GENERATOR CONNECTIONS
Connect the two signal generators as follows:
A. Set generator "I" to 10 ddm RF output.B. Turn off modulation on generator "1".C. Set frequency of generator "I" to 35 MHz.D. Connect to local oscillator input through a 50 4 coax
cable.E. Set generator "2" to -70 dBm RF output.F. Set modulation frequency to 1000 Hz on generator "2".G. Set deviation to 5 kHz on generator "2".H. Connect generator "2" to preselector input through a
50 il coax cable.
57
6.4 RECEIVER POWER-UP
To operate the receiver, do the following:
A. Set preselector switch to low.B. Turn volume control downC. Turn both power supplies onD. Slowly increase volume control until the demodulated
signal can be heard.
6.5 SINAD MEASUREMENTS
To measure the ultimate SINAD of the receiver, do the
following:
A. Connect distortion analyzer to received signal output
via a 50-ohm coax cable.B. Turn distortion analyzer on.C. Set function switch to set level.D. Set meter range knob to 0 on dB range.E. Set sensitivity switch to 0 on dB scale.F. Set frequency range to X100.G. Set frequency dial close to 10 as possible at pointer.H. Turn meter range switch clockwise until the meter begins
to come up.I. Fine tune frequency for maximum deflection and highest
meter range setting possible using the fine and coarseadjustment.
J. Read ultimate SINAD and record the level.
6.6 RECEIVER POWER-DOWN
After completing the SINAD or other additional tests, do thefollowing:
A. Disconnect distortion analyzer.B. Turn both power supplies off simultaneously.C. Turn off both RF generators.D. Disconnect test equipment from radio.
6.7 CONVERSION FROM ANALOG TO DIGITAL DEMODULATION
A. Be sure power is off.B. Remove the baseband multipliers board and the baseband
oscillator and VCO board (Part Nos. 31174-107 and31174-108). This can be accomplished by removing thetwo Phillips head screws that are securing each board tostandoffs and pulling the boards out of the connectors(J8 and J9).
C. Insert the two digital subchassis boards A15 and A16
into connectors J8 and J9, respectively.
58
D. Place the digital subchassis on top of the three tallstandoffs. Use a No. 4 screw, flat washer, and lockwasher at each standoff to secure the subchassis onto
the breadboard.E. Insert the four digital demodulator boards into the four
connectors. Part Nos. 31174-111, 31174-112, 31174-113,and 31174-114 fit into connectrr Nos. J1O, J11, J12 andJ13, respectively.
F. Secure each board to the subchassis in the same mannertliat the analog democulator boards were secured. Usetwo sets of screw, a flat washer, and a lock washer foreach board.
G. Follow the procedure for turn on, and the receiver willoperate with a digital demodulator.
6.8 CONVERSION FROM DIGITAL TO ANALOG DEMODULATION
A. Be sure power is off.B. Remove the four digital demodulator boards from the
digital demodulator subchassis. This can beaccomplished by removing the two Phillips head screwsthat are securing each board to standoffs and pullingthe board out of the connector.
C. Remove the three Phillips head screws that are holdingthe subchassis in place.
D. Lift the subchassis out of the breadboard.E. Remove the screws holding the wire harness boards in the
breadboard and remove the boards.F. Place the subchassis out of the way.G. Place the baseband multipliers board (Part No.
31174-107) into connector J8.H. Place the baseband oscillator and VCO board (Part No.
31174-108) into connector J9.I. Secure the boards in the same manner that the digital
demodulator boards were secured into the subchassis.Use two sets of a screw, flatwasher, and lock washer for
each board to secure the boards onto the breadboard.J. Follow the procedure for turn on and the receiver will
operate with an analog demodulator.
59
Section 7
DIGITAL ZERO-IF COMPUTER SIMULATION
This program simulates the Zero-IF receiver architectureand calculates the distortion (SINAD) of the system. Two modulatedsine waves, ninety degrees out of phase, represent the I and Q chan-nels. They are sampled and converted from analog to digital. Eachsignal is then sent through a simulated phase detector. Once the phaseof the I and Q channels are calculated, the difference between samplesis calculated. This difference calculation simulates the differentialprocess necessary for FM demodulation. The SINAD is then calculatedwith the formula (S+N+D/N+D).
Included in this program is the ability to change thenumber of A to D and phase quantization bits, along with changing thesampling rate. Insight can be gained into some of the limitations ofthe system. The program also provides a check for the hardware perfor-mance. Large variations between the program simulation and hardwareresults can be detected and subsequently corrected. This raises theconfidence level for both the hardware and the software simulation.
The performance goals for the hardware were set at 35 dBultimate SINAD, which provides ample voice recognition. Assuming a40-kHz sampling rate, the goals can be achieved by using six bits quan-tization for the A to D converter and three bits in 450 phase quan-tization. The simulation calculated a 38.7 dB SINAD for these inputparameters.
Currently, the hardware has eight A to D and seven phasequantization bits. The ultimate SINAD of the hardware measures 32 dBSINAD. The simulation calculates a 51 dB SINAD for the same con-ditions. This difference can be explained by the fact that the simula-tion does not consider phase or amplitude errors in the I and Qchannels. Typically, up to I dB channel imbalance and a deviation ofup to two degrees from phase quadrature is present in the hardware.The value of the simulation lies in the fact that it defines the opera-tional capability of the digital circuits only. The results of this isthat the hardware performance is not limited by the digital demodulatorbut by the analog circuits ahead of this demodulator. The fact thatthe digital system is actually capable of a better ultimate SINAD thanthat which is required explains why the ultimate SINAD of the digitalsystem is the same as the analog system. That is, both are limited notby the demodulators but by the phase and amplitude imbalance of theanalog circuits ahead of the demodulator.
A listing of this program can be found in the back of theAppendix.
60
APPENDIX
SCHEMATIC DIAGRAMS,
PARTS LIST,
COMPUTER SIMULATION
LISTING,
AND
FUNCTIONAL DESCRIPTION
OF
THE ZERO-IF RECEIVER
61
APPENDIX
SCHEMATIC DIAGRAMS,
PARTS LIST,
COMPUTER SIMULATION
LISTING,
AND
FUNCTIONAL DESCRIPTION
OF
THE ZERO-IF RECEIVER
61
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_____IM'PLICIT RFALAB (A-H IO-Z)!Mptic !e-I--IwvEER*4-f--NY-INTEPERI*4 JND(6)REAL *8 ADIS(6)INTEGER*4 NPHA(9),KADA(9)INTEGER*4 KATD
COMPLEX*6 SUMJJ XMJC. DTSC, TDXC, DDTSC, TTDXCCOMPLEX*8 TJ1(5),CTMJ,SUMT,TJ(5)DIMENSION 5RHjt20GSR(20)COMMON /RAND/1101 Ill
C -- - -
c ZERO IF SIMULATION PROGRAMC
r NPUTjj k VRIARLES:ZC DF =FM-FREiCUENCY DEVIATIONC FOD CARRIER FREQUENCY OFFSET DIFFERENCE
e TAI - CHA.NNEL PHASE OFFSETC TAG 0 CHANNEL PHASE OFFSETC TRC =TIME CONSTANT FOR MODULATION FILTER__
c TS =A/D SAMPLING RATE-C KAD NUMB3ER OF A/D BITS FOR I AND Q SIGNALS
r. NlH NU~nPR OF EPHA-- OIIANTIZATION. LEVELSc ND =NUMB3ER OF DATA SAMPLESC VARN = VARIANCE OF NOISE MODULATION
WRITE(1, 1)1 FORMAT(1X, 'SIN WAVE RUN') __ _
C IP1l THEN DEBUG PRINTOUT.__C IP=1
7 P=0110=1
C DF (KHZ)e FOD flH2
C TAI (RADIANS)C TAG (RADIANS)
FODO0.0TAT=n nTAQ=O. 0WRITE( 1, 5O3)DF, FOD, TAI, TAG
5e3 FORI1AT(t)X, ')F-',Et2. 4, 2X, 'FPOD' ,E-tL)-4, 2Xi-1'TAI-',El2. 4, 2X, 'TAG=',El2.4)
C TRC (MILLIStLC)THI;=O. O0oiVARN=1. 0WAf (i) "NPHA(2)= 4NPHA(3)=8
NPHA(5) -3PNPHA(6) -64
NPHA(8)=256NHA(9) 512KADA( 1 )-2KADA(2): 4
KADA(4)=SKADA(5): 12KADA (6) 17'-KADA(7)- 10L(AfA(S)tw 1
KADA(9)= 1'
ABTS~i)- .~ ON--ADTS (2):r. 0' .ADTS(3)=. 0;11'
ADTS(5)=. OC)1$25'rrn I I I00
IND( 3)=2000
C
DTS=ADTS( 11)ND=IND(II)
5C4 FORMAT(IX, 'TRC=',El2. 4,lX, lX, 'VARN=',IE12.4,lX, 'ND=',I5,1X, 'DTS= ,E12.4)LDO 1'VV I P- 6 aNPH=NPHA( 32)nnf i gRTg-j -
KAD=KADA( 13)WRITE( 1, 99c)NPH, RAD
TMJ1=O. ODC)PIE=4. QDO*DATAN(1. ODO)IE~i2=. 0ODQ*DATAN( 1. ODO)DCXM1=O. 01)0
SM2 I=0. 0DOSE21=0. ODOXMDC--. ef)C;ETA1=0. ODODO 101 IZ=:1,2O
SRIL ) -O.UvuSRMJ(IZh=O. ODO
10 1 COTITNUECC
CC
4 PULL UUTI1ERWORTH LOW PA55 FILTERC CHARACTERISTICS F13(3 D13 POINT)=5KHZr- qI 1 ~ - lq-q AR~ F-THE HLP~P -?O OLC-tIONs -C FOR THE FILTER. HKIJHK2,HK3,HK4 ARE THE
C COMPLEX PARTIAL FRACTION EXPANSION COEFFICIENTS. _
C
WRITE( 1,571 )F1571 FnRMAI ('F1=-' .:)XEpr .3)
WB=2. ODQ*PIt-*FBSL(1)=(-0.38i27,0. 9239)SL (2) =( 0. 9239 E). 332:7)~-SL(3)=(-0. 9239,' -0. 3827)SL(4)=(-0. 3827, -0. 9239)
HK C 3) = 0 4619 1 1 5 )
C
CC
t-M=lKH 1 NE__________
C
BETA =DAIAN(PIE*FM*DTS)
e ETA -E). E)- -- - ---
CCc DELAY CALCULATIONS FOR 4-POLICr Rt1TTFRWOUlT11 EDI ER
W*=FM / F1
DO 400 I=1,-1SOL=REAL(SL (I))
TDL=SGL/ (3GL.*SGL+ (W-GL) * (W-GL))
__ -SU1fl I1DLI-SUPM -
40 CONTINUtI.TOL =-SUMD /WrlJ
401 FORMAT('TDL:-',E20 B3)
CDTSC=CMPLX (SNGL (DTS),0. 0)DO 30 1=1,-l
C MULTIPLY BY W13 TO UNNORMALIZE POLESnnlzC~q' fT)m-DcX*jJ4 ___
HK I )=HK( I)*WjJ
DO 20 d.-b- __ 1IF( J. EQ. I)E< ( I, J) =CEXP (DDTSC)IF(J. NE. I)rEr( , J)=(O. 0, 0. 0) _ __
IM~ P. EQ 130WRITE( 1, lc9)ET( I, J), I, J19 FORMAT ( I ET-( E20. 8, ','E20. E3, ') ',SX, 'I=', 12, X,'J=.'.12)
YKI(I)=(0. 0,0. 0)UI)=( 1. 0, C). 0)
C
:30 CONTINUE
CCC
DO 100 I=1.NDXTJ=( I-i )*I)-IS
e GENERATE I AND ci SIGNALTMJ=DSIN(P] E2*FM*XTJ)TMJT=DS IN (2*P IE*FM*XTJ-3ETA)
IF(IP. EG. )WRITE(1.602)TMJ602 FORMAT(1X, TMJ=',E20.E8)
pT.I=(DFjFM)*(j 1 OD-CqSE2*Ei14N*-XT-)4~ARG=P 1E2-*F01)XtJ+PTJXIJ)=DCOS(AR(,*+TAI)1efkj-t. C0'E)*S!NAR0±TAciQ-_IF( IP. EG.1) WRITE( 1.506) XIJ, YQJ
506 FORMAT(1X1 'XIJ=",E12.4,5X, 'YGJ=',E12.4)-c-C DEMODULATION OF I AND ci SIGNALSrC A/D QUANTIZATION OF I AND 0 SIGNALS
IXJ=KATD(XIJ,1. ODOKAD)LQJ-KATD0(Y0J, 1. ODO, KAD)IFI IP. EQ.1)VWRITE( 1, 507) IXJ, LQJ
507 FORMAT(lX,'JXJ=',I6,5X, 'L0J=',I6) __
u E5TIMATE LJF PHAbh U51NG VECTOR METHODC
MQi=IABS(L0J)IPK=2. DO**KAD
505 FORMAT(lX, 'IPK=',14,2X, 'MI=',I5,2X, 'M0=',I5,2X. 'NPH='.I5)CALL VEPAC(MI, M0,NPH, KAD, ETA)IF( IF.E0. 1)WRITE( 1, 502)ETA
502 FORMAT(1X, 'FTA='sE12.4)
C TEST I AND Qi CHANNELS FOR PHASE QUADRANTIF(IXJ. CT. 0)GD TO 200ETA-P!IE+THF7 AIF(LQJ. CT. O)ETA=PIE-THETAGO T0 201
Ro0 ETA=P IE2-TH-.TAIF(L0J. G1.0)ETA=THETA
IF( IP. E0.1) WRITE( 1, 501 )ETA501 FORMAT (I1X, 'ETA=', E12. 4)
DELTA-ETA FiI --- - --IF(DABS(ETA-ETAl).LT.PIE)GO TO 210IF(ETA. GT. V.TA1 )DELTA=DELTA-PIE2IF(E-TA.G;T.ETAl)G0 TO 210DELTA=DEL-TA'-P 1E2
XMJ=DELTA/ (P 1E2*DF*DTS)IF( IP. E. I)1IRITE( 1.213)XMJ
t3--~~- i ~~,2.B
ETA I =ETAe.
C LOW-PASS FILTERING OF DIFFERENCE____I- SIGNAL U51NG 4-POLE BUTTERWORTH FILTER.- -
C
CC
DO 230 IJ=1,4ETJ=(0. 0,0.C)
CnnO P.'M jj=1..4ETJ=ET( IJ,JJ)*YK1 (JJ)4-ETJ
220 CONTINUElF(lP.EG.t)WRuTEut,22t)ETfj _
C2 OMT EJ 2.8 2.8C
YK( IJ)=XMJC:*HK( IJ)+ETJIF(IP.EO.1)WRITE(lj2",2)YK(IJ)
222 FO3R MAT( 'Y-'E23.O 8, ,E20 8,_230 CONTINUE
IF( IP. EQ. 1)WRITE( 1,231)de:1 FUFRMAI('2JO LOOP COMPLETED')C
e LOW PASS FILTERIN@ OF REFERENCEC SIGNAL TO COMPARE WITH LOW-PASS FILTEREDC DIFFERENCE SIGNAL.___
C
ETJ=(0. 0,0.0)C
DO 320 dJ=1,4ETJ=ET( IJ,JJ)*TJ1 (JJ)+ETJ
Ljieu CONTTMUZ
TMJC=CMPLX(SNGL(TMJT), 0.0)TJ( IJ)=TMJC*HK( IJ)+ETJ
333 CONTINUECC
SUMJ=(0. 0,0. 0)c:ZjmT=(Q 0.0 n)
DO 240 IJ=1,4
242 FORMAT('YIU=(',E20.8, ', ',E20.B, ')')
* SUMJ~U(ij)*Yk(IJ)+SumjSUMT=U( IJ)*TJ( IJ)+SUMT
P-40 eONTINUEIF(IP. EO.1)WRITE(1,241)
241 FORMAT('240 LOOP COMPLETED')
c
* TMJX=REAL (SUMT) *DTSXMJ=REAL (SUIMJ) *DTS
e WR 1TE ( 1t 20)Ti, -Tf,-TJ---C20 FORMAT(lX, 'XTJ=',El2.4,4X, 'TMJT=',El2.4,4X. 'TMJX=',E12.4)
IFCIP. EQ. 1)WRITE(1,211)SUMJ __
RI 1 FORMAT ('SLJMJ= ('E20.S 3, 'E20.B8, )Cr CAL LAii ATF TNtE1AE~C FOR DEMODULATED DATA TO CORRECTC FOR DC OFTF-3rTS
NMX=20
CALL SFTR(XMJ, SR, NMX)XMDC=(XMJ-SiR(NMX))/FLOAT(NMX)+XMDCI-"Mr- 1=x MYC
C XMJP=XMJ)-XM3JC
IF( IP. EQ.1) WRITE( 1,150) XMDC, XMJ.TMJ, SR (NMX)150 FORMAT(1X, 'XMDC=',E20.B,5X, 'XMJ=',E20. 8,5X, 'TMJ=',E20.8,
153-, 'SR (MX) -', E20. 8CC CALCULATE ERROR DIFFERENCE
160 EXM=XMJP-1'MJXT FC PPa1 ) WR IT 1 -1 5-)XM, JPTM, IX, EYkl4-
153 FO3RMAt('XMJP=',E20.8,5X, 'TMJX=',E20.8,5X, 'EXM=',E20.8)C GO TO 100
C CALCULATE MEAN AND VARIANCE OFC MODULATION VARIABLES FOR SIGNAL ____
c; PLUS D)I5TORTION 10 DISTORTION RATIOC
TF(T IT NIMY )Gnf TO 100NI=I-NMX IXNI=FLOAT(NI)
IF( IP. EQ. 1)WRITE( 1.302)XNI302 FORMAT(lX, 'XNI=',E20.8)
DCXM1=XMJP/XNI+XNI 1*DCXM1 /XNIDCXMI=DCXM
EDC 1=EDCXl12=XMJP**2SMR-XM1XNj-'XNI1t*SM2t/XNI -
EM2=EXM**P6E2=EM2/XNJ+XNI 1*SE21/XNISM2 I=5m" rSE21=SE2
1 ()j CflNTTNI
WRITE( 1, 303)FMC-9e3- FOR MAT( FM- ',F t .4)
CCC GO U T /
C CA' CI' ATE (S+iD)'D RATIO -
CVARM=SM2- (DC XM**2)
WRITE(1, 301 )VARM, VARE301 FORMAT(lX, 'VARM='.E20. 8,5X, 'VARE=',E20.8)___
5DR=1Q. 0DO*DLOG1Q(VARM/VARE)WRITE( 1, 300)SDR
175 CONTINUEWRITE( 1,998)
996 FORr1AT(t~-t)1998 CONTINUE1999 CONTINUE;R000 CONTINUE
C----. - -
C
SETOP
:WBOUTINE GRV(X1, S(, XV, YV)C
rI-4I SUB~ROUTINE GENERATES TWO ZNDEPENDEN-T GAUSSIAN- RANDOM VARIA13LESCC SG = DESIRED STANDARD DEVIATION OF GRV
e )(M- DESIRE!) MEAN OF GRVIMPLICIT RFAL*8 (A-H,O-Z)IMPLICIT INTEGER*4 (I-N)COMiMON /RAND/IIO, IIIP 1E2=8. 0D*DATANC1. ODO)r A' I R ANDU ( 7 0, . YnI 1,
Z=SQ*DSORT(-2. ODO*DLOG( 1. ODO-YD 1))e ALL R ANDU ( 1, f 1 , YfD2 _
C WRITE(1,10)YD1,YD210 FORMAT(lX1 'YD1= ,El2.5,5X, 'YD2=',El2.5)
PHI=PIE2*YD2Yv=7*nrDnfl(pHI ___
YV=Z*DSIN( PHI)RETURNEND ____
FUNCTION KA1'D(X 1 AK)Cc X=ANALOG SIG~NAL WITH MEAN = ZEROC A = MAX LEVEL FOR A/D CONVERTER
r K= NUMB3ER OF BITq G'JANTIZATION ISIMUDING S-IN --------- *--
C OUTPUT IS DISCRETE DECIMAL"LEVEL, NOT BINARYC
IMPLICIT !IEGER*4 (I N)REAL*8 X,A,.iINTEGER*4 KATD)
S=2. ODO*A/(2. ODO**K)AX=' X+A)Zq~KATD-KX-K2RETURNENE)SUBROUTINE VEPAC( IX, JY, NX, SAD, A)
CC- THIS 5UBUOUTINE CALCULATES THE VECTOR PHASEC ANGLE FROM THE INPHASE AND QUADRATUREr cST(--NAI GnMP2ONErNT-cC SIGNAL COMPONENTSC IX=MAGNITUDE OF SIGNAL COMPONENTe jY=MA&NlTUDE OF QUADRATURE SIGNAL COM-PONENT--C NX=NUMBER OF PHASE RESOLUTION CELLS IN 90 DEGREESC A=ANGLE (IN RADIANS) CALCULATED FROM IX AND J.N SIGNALS ___
IMPLICIT RFAL*8 (A-H1 O-Z)TMPRI lcTT 1 NIrGE-R*4 (T-N)INTEGER *4 KATD)PIE=4. ODO*DATAN(1. ODO)
IPK=2. ODO**(KAD-1. ODO)AIPK=IPKIZT=(AIPK**. D0)*JD'HI/2. gpoNXI=NX+1
200 FORMAT(lXs'DPHI=',El2.4,2X, 'IPK=',I55 2X1 'IZT=', I5,2X,1 'NX11, 15)96 1030 1-t, NX1 __
PHI=FLOAT( 1-1 )*DPHIAI=DCOS(PHI)
JAI=KATD(AJ, 1.000, KAD),JTnT=t4ATnl~nT- I OnnfljAD)
C WRITE(1, 1)AJBI1 FIRMAT(1X,'*JAI=',I6,5X, 'JBI'1,I6)
IF(JZT. LT. IZT)GO TO 101100 CONTINUE101 -0UNTINUL-
A-PHI
SBOUT INE RANDU(IX, IYYFL)
IMPLICIT IN1EGER*4 (I-N)
IY=IX*INTL(&5539)IF(IY.GEK.O)GO TO 6____
-7IYl " 4INL214748a647)+INTL( 1)6 YFL=!Y
y'iF =yFi -. k% ~ 613~p9-__ _
RETURNENDSUBROUTINE SFTR(X, SR NL)
CC THIS SUBROUTINE PERFORMS A SHIFT REGISTER
UIPEJATION. X IS THE NEWEST INPUT VARIABLE,C SR IS THE SHIFT REGISTER ARRAY, NL IS THE
r IFENGTH GlF THE SHIFT REGISTERCC
REAL*-B X,H-j,H2,9R ___
INTEGER*4 NL, I.NL1DIMENSION GR(20) _____
lF( IP. EG.1) WRITE( 1, 10)NL10 FORMAT( 'NL=', 15)
NI 1 =s1 - 1Hi=SR (1)DO 100 I=1.NL1HRi-SRU±I___ ___
SR(1+1 )=H1Hl=H2
100 CONTINUESR( 1)=XRP=T' 'PMEND
FUNCTIONAL DESCRIPTION OF THE ZERO-IF RECEIVER
INTRODUCTION
The Zero-IF receiver built under the Zero-IF receiver studycontract for the US Army is designed to operate in the 30-88 MHz bandreceiving an FM signal with 5 kHz peak deviation. It can receivesignals as strong as 0 dBm and as weak as -118 dBm. The following is adescription of how the receiver works.
RF Circuits
An RF signal is input to the radio via JI on the back panelof the chassis. It then passes through connector P1 which mates withJ1 and is input to the preselector filters. This connection is shownon the chassis wiring diagram (page A-1 of the appendix) in the linelabeled RF input. One of the three bands in the preselector (page A-2of the appendix) is selected by turning the band select switch locatedon the front panel of the radio. The three channels are labeled as L,M, and H. Of course, these letters stand for low, middle and highband. If the signal is within the passband of the selected filter itwill continue onto the EF amplifier/attenuator stage. If the signal isnot within the passband of the selected filter it will be attenuatedand effectively the radio will behave as if no signal was received. Inthis way, the preselector can be thought of as a tuner.
Band selection is accomplished in the circuit through theuse of PIN diodes. Each of the bands has a dc voltage applied to it.This voltage is provided by two control inputs. One control input (E12on the schematic) provides -15 volts for all 3 bands. The band whichis selected will have +15 volts connected to its other control input(E9, ElO, or Ell) causing current to flow through the voltage dividerof the 10K and 1.5K resistors. A +11 volt dc level is then applied tothe PIN diode, forward biasing it, and allowing the RF signal to pass.The bands which are not selected have the -15 volt level on theirdiodes, reverse biasing them, causing an open circuit for the RF signal.
The RF signal then leaves the preselector filters board viaP2 and enters J2. J2 is connected to J3 by a jumper on the back panelof the radio. J3 connects to P3 Ji and the signal enters the RFamplifier/attenuator board. The jumper between J2 and J3 can beremoved and by connecting an antenna to J3, signals outside the
30-88 MHz band can be received. The RF parts should provide good per-formance between 20 and 200 MHz.
The RF amplifier/attenuator board is a rwo section board.One section contains the RF amplifiers and the PIN diode variable atte-nuator pad, while the other section contains the attenuator pad controllogic.
The signal is first amplified by an RF amplifier Ul (pageA-3 of the appendix) and then enters the attenuator pad. The atte-nuator pad is used to control the RF level coming into the receiver.
46 IF-I
It has five different settings. The settings are 0, 12, 24, 36, and48 dB of attenuation. As the RF level increases, the baseband AGC cir-cuits control the level of the signal entering the demodulator. Afterthe baseband AGC's attenuation is exhausted, stronger signals couldcause clipping and degrade the SINAD. When the baseband AGC indicatesthat more attenuation is necessary, the shift register U3 in the atte-nuator control logic (page A-4 of the appendix) is strobed and one stepof RF attenuation is turned on. If the baseband AGC indicates thatthere is too much attenuation and the RF attenuator has some atte-nuation on, the shift register is strobed again, and one step of RFattenuation is turned off.
The attenuator uses analog switches to turn the individualsteps on and off. In the 0 dB of attenuation setting, Dl and D2 are onwhile D3 through D6 are off. This allows the signal to pass throughthe upper branch of the circuit (see the schematic on page A-3) by for-ward biasing the PIN diodes. In the 12 dB of attenuation setting, DIis turned off and D3 is turned on. All other points remain the same.If 24 dB of attenuation is required, D2 is turned off and D4 is turnedon. For 36 dB of attenuation D5 is turned on, and 48 dB of attenuationis achieved by turning on D6. At the full attenuation setting (48 dB),two diodes are off (DI and D2) and four diodes are on (D3 through D6).The RF signal leaves the attenuator pad and enters the amplifier U2.The RF signal is amplified by 12 dB and leaves this board and enters
the signal splitter/mixer board as shown on the chassis wiringdiagram. The local oscillator (LO) signal is supplied by an RF signal
generator. It enters the radio via J4 on the back panel of the radio.It then enters the local oscillator 90 degree splitter (LO splitter).The LO signal is then split into two signals, one in phase with the LOand one 90 degrees out of phase (in quadrature) with the LO. These twosignals are then input to the signal splitter/mixer board.
The signal splitter/mixer board receives the signal fromthe RF amplifier/attenuator board and inputs it to the 0* powersplitter UI (page A-5 of the appendix). This part splits the receivedsignal into two signals identical in phase and amplitude. These twosignals each proceed to the RF input of a mixer (U2 or U3). The LOinput on each mixer is connected to one of the two LO signals comingonto this board. The received signals are then mixed with the LOsignals. The output of the mixers is a baseband signal along with anRF frequency at twice the LO frequency. These two signals are theninput to the baseband channel filters board. It should be noted thatthe two baseband signals are identical except that they are 90 degreesout of phase. They can be referred to as the in-phase and quadraturesignals; hence, the names I and Q channels.
Baseband Circuits
The baseband channel filters board (page A-6 of theappendix) consists of two (one for each channel) seven pole passiveelement filters. These filters are low pass with a cut off frequencyof 8 kHz. These filters provide 70 dB of attenuation at 25 kHz whichis the adjacent channel. After the signal is filtered here, itcontinues on to the low noise amplifier board.
46 IF-2
The low noise amplifier board (page A-7 of the appendix) isdesigned to give small signal gain without adding noise from activedevices. Both channel signals go through a transformer, TI and T2.These transformers are arranged such that they are a 1:40 step up.Their outputs then go to Ul and U2. These are very low input noiseop amps. They provide 22 dB of gain. The signal then goes to afiltering and gain stage, U3, which has another 13 dB of gain. Afterthis stage the channel signals proceed to the automatic gain controlboard from Pins I and 22 to L and 12 respectively as shown on thechassis wiring diagram.
The automatic gain control (AGC) board (page A-8 of theappendix) is designed to amplify small signals and to attenuate largesignals. This is accomplished through the use of a digital step atte-nuator. The major components of the attenuator are the two shiftregisters U5 and U6, and the four analog switches U7 through U10.
The detector is made of the four op amps in U3. This cir-cuit half-wave rectifies each channel signal and sums the two together.This produces a dc level. This dc level is compred with two referencelevels, one being a low threshold and the other a high threshold. Whenthe dc level from the rectifiers is between the two thresholds, theamount of attenuation set in the attentuator is correct. If the dclevel is higher than the high threshold, the control logic causes theattenuator to increase the amount of attenuation. If the dc level istoo low, the control logic causes the attenuator to decrease the amountof attenuation.
Whenever a change in attenuation is necessary, the controllogic enables the clock, Ull. The clock causes the shift registers toshift in or out attenuation. The direction of shift is determined bythe mode control line. When the control logic causes this line to goto a high state, the attenuator will switch out attenuation with theclock. If the mode control line is in a low state, the attenuationwill switch in attenuation with the clock. When the proper amount ofattenuation is reached, the control logic once again disables theclock. The clock only runs when an attenuation change is needed. Thishelps reduce the amount of digital noise generated in this circuit.
The analog switches are used to provide the attenuation.As each switch is closed, attenuation is provided by the voltagedivider set up with the 20K ohm resistors R38 and R42 or R39 and R41.Note that the switches are wired in parallel so that each channelreceives the same amount of attenuation. Also, starting from the zeroattenuation setting, the swtiches U8 and UI0 are used first, then U7and U9 followed by the RF attenuation circuit.
The RF attenuation circuit is an extension of the basebandAGC circuit. The clock, the most significant bit from the AGC circuit(MSBAGC), and the mode control lines all are inputs to the RF atte-nuation circuit. The detector still functions the same after the base-band AGC is used up. The least significant bit from the R (LSBRF)
46 IF-3
stage and the most significant bit from the RF (MSBRF) stage are fedback to the baseband AGC circuit. The MSBRF is an overflow protectionbit which, when high, disables the clock if the detector indicates moreattenuation is necessary. This is to prevent the clock from runningand the circuits from trying to add in more attenuation when there isnone available. The LSBRF is used to tell the baseband AGC that all RFattenuation is off. Therefore, if less attenuation is necessary thebaseband AGC must turn off some of its own attenuation.
A compression amplifier (U4A, U4B) follows the AGC cir-cuitry in each channel. The purpose of the compression amp is two-fold. First, it smooths out the bumps caused by switching in and outdifferent steps of attenuation. Secondly, it provides a constantamplitude signal out for the demodulator. The key element in thecompression amplifier is the n-channel FET (Q5 and Q6) in each. TheFET is used as a variable resistor. The amount of attenuation can thenbe varied by changing the voltage on the gate. This is included in theclosed loop feedback to the op amps (U4A and U4B) along with the capa-citors and resistors which set the attack and release time constants.
The output of the compression amplifier is shown in Figure1. The center trace in these pictures is the modulation impressed onthe RF carrier. The upper and lower traces are the outputs of eachchannel. Note that the channel signals are identical except that theyare 90 degrees out of phase. Also note, as the modulation crosseszero, both channel signals undergo a 180 degree phase shift. Thiscorresponds to the reversal of the direction of rotation of the phasoras described in Section 3. Notice too that for lower modulation fre-quencies, the channel signals have more cycles of phase than for highermodulation frequencies. This corresponds to the longer time betweenzero crossings for lower modulation frequencies, and therefore the pha-sor rotates in each direction for a longer period of time.
The AGC output pins are J and K of J6. The signals areinput to the demodulator through connector J7 pins D and E. Both demo-dulators use these two pins for their input. The analog demodulatorboards plug directly into the chassis connectors J7 and J8. The digi-tal demodulator subchassis jumper boards also plug directly into theseconnectors for digital demodulation as shown on the chassis wiringdiagram.
Analog Demodulator
As explained in Section 3, the analog demodulation process
used in the Zero-IF receiver is a phase-locked loop (PLL) demodulator.The major advantage of this approach is that it is not sensitive toamplitude and phase matching of the I and Q signals. This translatesto the circuit being able to more completely eliminate the deviationtones from the demodulated output.
46 IF-4
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The PLL demodulator used in the Zero-IF receiver is verysimilar to an ordinary PLL circuit. Figure 2 is a block diagram of anordinary PLL circuit. A signal enters the loop at A and is input tothe phase detector. The phase detector output is then input to a lowpass filter (LPF). The demodulated signal is at the output of the LPF.This signal is also input to a VCO as the control voltage. The VCOoutput is then fedback to the other input of the phase detector,completing the loop.
Figure 3 shows that the Zero-IF PLL demodulator is dif-
ferent from the ordinary (PLL) demodualtor in that it has two channelsin the feedback path. Two feedback channels must be supplied becausethere are two input channels. The feedback signals represent the mixedoutput of the VCO and the baseband oscillator. If there is no modula-tion on the received carrier and no frequency error exists, the outputof the baseband oscillator and VCO mixers is a dc level. If modulationor frequency error exists, these outputs are the derivatives of the I
and Q channels.
The I and Q signals enter the phase detector (page A-9 ofthe appendix) which is implemented as two analog multipliers (U2 andU3). The other input to each multiplier is the filtered output of thebaseband mixers. The multiplier outputs are then subtracted one fromthe other in an op amp (U4A). The result from this subtraction is theerror voltage in the PLL. As it was shown mathematically in Section 3,the error voltage is the desired demodulator signal. The error voltageis sent to the audio circuits for filtering and is the control voltageinput (page A-10 of the appendix) for the VCO (u).
The control voltage for the VCO passes through two op amps(U8A and U8B). These op amps provide a level shift for the VCO controlvoltage so that the VCO frequency will vary linearly with voltage 20kHz about its nominal frequency (250 kHz). The VCO output is input tothe clock of a D type flip flop (UbOA) which is connected in the stan-dard manner for division by two. Both outputs of this flip flop areinput to the clocks of two more D type flip flops (UIA and U1IB) whichare also connected to divide by two. This results in a nominal fre-quency of 62.5 kHz which varies higher and lower by 5 kHz out of theflip flops. Figure 4 is a timing diagram showing the results of thisdivision. Note how the two final outputs (QD2 and QD3) are 90 degreesout of phase. This insures that the two signals generated by this cir-cuit are also 90 degrees out of phase. These two signals are input oneto each baseband mixer (U4, U5, and U6, U7). The other input to bothbaseband mixers is the free running baseband oscillator. This oscilla-tor (02) operates at 1 MHz and is divided down to 62.5 kHz (a divisionof 16) by the shift register (U3) and flip flop (UlOB). The mixerinputs driven by this result are in phase. The baseband mixer outputsare two IF signals, like those shown in Figure 1, which are 90 degreesout of phase. These signals are also the derivatives of the I and Qsignals. This is obvious because the VCO is an integrator in a feed-back path, therefore the VCO effectively differentiates the I and Qsignals.
46 IF-5
A N DTECOR NP PASS -p- OUTPUT
vCO
FIGURE 2: Basic PLL Circuit
PHASE DETECTOR
FITE
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FIGURE 3: Zero I.F PLL Demodulator
CLK01 (250 kHz)-FJLIFf -I -F-IF -F Jl
QDI (CLKD2) (125kIz
%D1 (CLKD3) (125 kz
FIGURE 4: Timing Diagram for Zero L.F.Receiver Divide by 4 Circuit
The baseband mixer outputs then pass through 50 kHz lowpass filters (U9A, U9B). The filtered output is fed back to the base-band multipliers board (page A-9 of the appendix). Here they pass onthe phase detector, completing the loop.
The baseband multiplier (phase detector) outputs are alwaysin phase with each other. Each output is the product of two signalswhose frequency varies from 0 to 5 kHz. Therefore, the output signalof each multiplier varies from 0 to 10 kHz. The output signals alsohave another component. This component is the error voltage for eachparticular phase detector. The error voltage represents the amount ofphase error present between the two signals that are input to themultiplier. It varies plus or minus depending on the amount the phaseof the two input signals is away from 90 degrees. These two errorvoltage signals are identical except that they are 1800 out of phase.Subtracting the two phase detector outputs yields the error voltagesadded together and the remainder of the signals canceling out. Thiserror voltage represents the desired demodulated signal.
The output error voltage from each phase detector is depen-dent on the magnitude of the phase difference between the two inputsignals. When the two input signals are 90 degrees out of phase, theoutput error voltage is zero. As the two signals vary from 90 degreesout of phase, the error voltage will vary about zero volts linearly.Figure 5 is a graph of the error voltage versus the difference in phaseof the two input signals. The two zero crossings represent the possi-bility of either input signal leading the other at any instant in time.As the modulation passes through zero crossings, the phase detectorbounces from working on one slope to the other because the inputsignals exchange roles leading in phase.
For the case of no modulation with a beat frequency, thephase detector outputs are a frequency of twice the beat frequencyriding on a dc level. The output frequencies are in-phase, while thedc levels are of opposite polarity. Subtracting the phase detectoroutputs yields the dc level only. This dc level directly representsthe beat frequency. When the magnitude of the beat frequency is small,the dc level is small. When the magnitude of the beat frequency islarge, the dc level is large. When modulation is present, the instan-taneous carrier deviation can be analyzed as a beat note. The carrierdeviation changes with time, following the modulation causing a changein the instantaneous beat note. These changes cause a varying dc levelwhich actually is the demodulated signal. If the LO and the receivedcarrier are at the same frequency, the demodulated signal will varyabove and below zero volts. When they are not at the same frequencythe demodulated signal will vary above and below the dc level caused bythe beat note. The dc level is eliminated from the demodulate signalby the high pass filter in the audio circuits (UA on the schematic onpage A-Il of the appendix).
46 IF-6
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The error voltage drives the VCO and is the demodulatedoutput as described previously. By changing the frequency of the VCOwith the error voltage the same beat frequency is generated in thefeedback loop. This frequency will be phase locked to the receivedsignal inputs. The phase error away from 90 degrees crates the dclevel which keeps the VCO on the proper frequency. Thus, the loop iscomplete. This dc level can also be used for automatic frequencycontrol (AFC). By low pass filtering the output (cutoff frequency of Ito 2 Hz), the dc level can be separated and fed back to the LO. Byrecognizing this as a tuning signal, the LO frequency may be adjustedto draw its operating frequency closer to the received carrier.Switching around the multiplier input connections will change thepolarity of the AFC signal and nothing else.
Digital Demodulator
As explained in Section 4, the digital demodulation processused in the Zero-IF receiver is the vector processor. The vector pro-cessor uses the successive approximation technique in finding theabsolute phase of a sample. It then differentiates by subtracting suc-cessive samples. To avoid the necessity of very high speed logic, thevector processor uses the pipeline technique for data manipulation.
SECTION 1
Section 1 of the pipeline receives the output of the AGCcircuit and samples the signal by the sample and holds ICs U8 and U9(page A-13 of the appendix). Comparators U5A and U5B check the sign ofthe sample. This information is stored in the latches U6A and U6B foruse in the next section of the pipeline. The signal is next input to afull wave rectifier U3A and U3B, and U4A and U4B. The rectified chan-nel signals are then input to the Analog to Digital converters, Ull andU12. The output of the Analog to Digital converters is sent to themagnitude compare and multiply circuit (page A-14 of the appendix) asshown on the digital subchassis wiring diagram (page A-12 of the appen-dix) and latched. This is the end of Section 1 of the pipeline.
SECTION 2
Section 2 begins by comparing the magnitudes of the samplesof the two channel signals in U6 and U7. The information received heredoes two things. First it is sent to the end of this section as aninformation bit and second, it is used to direct the greater of the twosamples to the multiplier U14, and the lesser to a second magnitudecomparator U8 and U9. The word that went to the multiplier ismultiplied by the tangent of 22.5 degrees. The multiplier output issent to the second magnitude comparator. The magnitude comparator out-put is sent to the phase register (page A-16 of the appendix) on thedigital timing circuits board.
46 IF-7
The phase register (U5B, U6, U7, U8, U9, U12 and U13) iscapable of representing any angle between 0 and 45 degrees to within0.351 degrees. It is used to find the phase angle of the signal at theinstant the sample was taken. It uses the successive approximationtechnique to accomplish this. First, the phase register is set to 22.5degrees by U9. This information passes to an EPROM on the magnitudecompare and multiply board. The EPROM is a look up table storing thetangent of the angles from 0 through 45 degrees. The tangent of 22.5degrees is sent to the multiplier. After multiplication, the secondmagnitude comparator sends a signal to the phase register. If themultiplier output is less than the lesser of the two samples, the 22.5degree bit is saved. If the multiplier output is greater than thelesser sample, the 22.5 degree bit is thrown out.
Next, the 11.25 degree bit is used. If the 22.5 degree bitwas saved, the EPROM will be addressed with 33.75 degrees, if not, theEPROM will be addressed with 11.25 degrees. The tangent is again sentto the multiplier, the multiplier outputs to the comparator, and thecomparator outputs to the phase register. The next least significantbit is used until all seven bits are used. When this process isfinished, a seven bit word representing the phase of the sample in 45degrees is on the output of the phase register.
Besides going to the EPROM, the phase register output alsogoes to the differentiator and DAC (Digital to Analog Converter) cir-cuit (page A-15 of the appendix) as shown on the subchassis wiringdiagram. Here the phase register output, the first magnitude comparebit and the sign bits from the first section of the pipeline are com-bined to represent the phase of the sample for 0 through 360 degrees.The previous word is then subtracted from this word in U8, U9, and U10.The subtraction output is lhtched in U14, U15, and U16. This is theend of the second section of the pipeline.
SECTION 3
Section 3 of the pipeline latches the phase register outputinto the previous sample register UIl, U12, and U13. It also containsthe DAC. The DAC outupt is then held for one sample period. The DACoutput is input to two filters. One filter is a 3100 Hz low pass. Theoutput of this filter is sent to the audio circuit. The other filteris a 0.75 Hz lowpass. The output of this filter is sent to J5 on theback panel of the radio as the AFC signal.
Audio Circuits
The audio circuits in the Zero-IF receiver (page A-li ofthe appendix) are very basic. The first element of the audio circuitsis a 300 Hz-3000 Hz bandpass filter. The filter is made up of anactive two pole 3000 Hz lowpass (UIB) and an active two pole 300 Hzhigh pass (UA) filter. The output of this filter is attenuated by R18
46 IF-8
and R17 and sent to the desired signal output which is connected to J6on the back panel of the radio. The desired signal output can be usedto measure the performance of the radio. The filter output is alsosent to the volume control and on to the speaker amplifier. Thespeaker amplifier drives the speaker with 400 milliwatts rms of power.
46 IF-9
I1