Overview of FLCC DFM Opportunities, August 28, 2006

FLCC Synergistic Design-For-Manufacturing (DFM) Research

Andrew R. NeureutherUniversity of California, Berkeley

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Feature Level Compensation and Control:Industry/University collaboration

through the U.C. Discovery Program

Test Structures

Sensors

Physical Models

Statistical Models

ProcessesProcesses MetrologyMetrology

SystemSystem

FLCC

Middle Year 3Planning Year 4

Four year research vision for compensating and controlling variability at the feature level

LithographyCMPPlasma Etch

Device/Diff/IntSensors & Ctrl

Novel VehiclesCollaborative

Experiments

Novel Apparatus

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The Industry Team

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Thanks to Our Participating Companies and the U.C. Discovery Program

• Very fortunate to have continuity in industry support from 17 companies with UC Discovery matching for 17 students at a time of cut-backs in university research.

• Support for Our University Research is only sustainable long term if it adds value to the Bottom Line of each of our Participating Companies.

• Mutual value starts with dialog between Working Technologists and Our Future Technologists.

• Looking for Guidance on High-Risk Opportunities where University Talent can do Pioneering Research.

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FLCC Assets for High-Risk Research• Academic Knowledge and Skills on Broad Fronts

– Physical Mechanisms, Process, Device, CAD, Circuits• Flexible Apparatus, Platforms and Software

– Scientific Apparatus and Instrumented Process Apparatus– Source Code for Rapid Prototyping

• Working Structure of FLCC– Novel Test Vehicle: ‘Zero Foot-Print Metrology’– Multi-Student Test Masks

• Collaboration with FLCC Companies– Phase-Shifting Test Masks– Vanilla CMOS Wafer Fabrication

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Scientific Apparatus: Leverage Univ. Legacywith minor investment (4%)

Sample and sample carrier

Slurry film Polishing padRotating platen

Slurry deliverypressurePotentiostat

samp

le2

Ref.

electr

ode

samp

le1

Polisher

Atomic Layer Deposition Source(Verify Molecular Dynamics Simulation of Clusters in FC)

0 200 400 6001015

1016

1017

1018

Con

cent

ratio

n (a

tom

s/cm

3 )

Depth (nm)

B in Ge as-imp; 32keV, 1013 cm-2

550°C 30 min anneal - simulation 550°C 30 min anneal - SIMS data B implantation - simulation

Annealing Furnace(diffusion Studies)CMP Wet-Bench

LEO SEM and Hitachi CD-SEM(PC and PCI bus upgrades)

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Process Apparatus: Industry ContributionAMAT Centura (Y1, Y3), laser for 248 nm AMSL (Y2)

Etch ModelingPlasma (JC, DG)

Test StructuresLith (AN)Zero Foot-Print

End PointSensors (NC)

AMAT Centura

Oxi

de

Si T

renc

h

Al • Emission

• Species• Probe

θi

Future MetalsDevice (TK)

• Compatible Gates for high-K• MEMS

CorrosionCMP(FD)

• Passivationalternatives

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UCB-DFMAerial Image Sensor

Novel Vehicle: Zero Foot-Print Metrology

θi

Interdisciplinary• Development

• Heterogeneous Assembly• Metrology and Control Interface•Modeling

• Monitoring Applications• Plasma Etch: End- Point Detection• CMP: End-Point Detection• Lithography: Image Monitor

Metrology wafer

Detection Window

CMP

Plasma Etching

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Multi-Student Process-EDA Test Mask4 Phase Alt-PSM: High-NA, PolFall 04; Fab: PhotronicsTested: AMD, Nikon, => UCB

Att-PSM: Short Loop NMOSMar 05; Fab: DuPontFab: Cypress

193 nm phases+ binary 248

4 Phase Pin-Hole Alt-PSM: High-NA, Pol; Spring 05; Fab: Benchmark & DuPontTest Plan: Nikon, AMD

2006 Mar Att-PSM for Enhanced NMOS, Apr 4 Phase Att-PSM for PI

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Validation Experiments in Collaboration on FLCC with Cypress Semiconductor: 2006 Tapeout

Cypress Experiments

Device Process

Circuits

60nm 60.5nm 61nm 61.5nm …

Ioff = 2nA 1.5nA 1.2nA 1nA 0.8nA

VT

Shift with different tips implant

80nm

=+

Super low power design

Finding correlation between gates

Circuits built to measure circuit variations

Using device design to measure CD variation

Characterizing your process

Cypress Experiments

Device Process

Circuits

60nm 60.5nm 61nm 61.5nm …

Ioff = 2nA 1.5nA 1.2nA 1nA 0.8nA

60nm 60.5nm 61nm 61.5nm …

Ioff = 2nA 1.5nA 1.2nA 1nA 0.8nA

VT

Shift with different tips implant

80nm

VT

Shift with different tips implant

80nm

=+ =+

Super low power design

Finding correlation between gates

Circuits built to measure circuit variations

Using device design to measure CD variation

Characterizing your process

Made possible by Feature Level Compensation and Control Program

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DFM Definition (home made)

• Design for Manufacturing (DFM) consists of fully integrating knowledge of the manufacturing process in to the product design process.

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Main Point of This Talk

Call to Arms to do more work on DFM in FLCC!

• Change in Mind Set: Linking our science among FLCC disciplines to form a whole is as important as individual new discoveries.

• Change in Investment: More of our effort should go into linking between disciplines and prototyping and applying new collaborative views of the whole.

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Disclaimer• The views expressed here are only those of the author

and not the FLCC.• In assembling inputs from industry observations

made in conversation have been used – without permission or proper credit and– with serious paraphrasing (filtering).

• The audience is welcome to express their views or identify and correct the phrasing of their observations.

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Outline

• Background on FLCC• Manufacturing Inabilities are a major Major Concern to

our Industry– Manufacturers, Fab-less Designers, Equipment and Software

Vendors, and 60 Start-Ups

• Key Questions for FLCC• Great FLCC/SRC/DARPA starting position• Key Opportunities and Actions for FLCC• Conclusion

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Inabilities Experienced by Industry• The inability to even identify the critical path due to lack of predictability

of interconnect effects has resulted in catastrophic time to market delays.• Twenty fold range of variation in standby leakage power when the

maximum can only be 1/3 of the maximum normal operating power.• Fab-Less designers have experience a disastrous variation in yields among

foundries and much of this is attributed to the lack of predictability of the foundry calibrated OPC parameters on the geometries that have passed design rule check in the chip layout.

• Without knowledge of process condition in a foundry it is nearlyimpossible and costly in terms of product delay for a circuit designer to initiate any actions to combat device and interconnect variations.

• New processes and materials such as resists require extensive calibration or model parameters that must be made with limited wafers, a small set of test patterns and fuzzy SEM measurements.

These issues are getting worse in going from 130, 90,65 and 45 nm generation.

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Inabilities Experienced by Industry (Cont.)• In the FEOL litho combined with etch results in significant variations in

gate length with variation components from feature to wafer length scales.• In the BEOL variations in CMP thickness and etch linewidth transfer result

in nonlinear increases in resistance in interconnect.• The low k1 factors in optical lithography today result in lower image

slopes, more cross-talk among neighbors, higher sensitivity to parameters in resolution enhancement and in feature compensation (not aberrations).

• Double patterning with k1 of 0.2 is a back-up to EUV lithography below 45 nm and there are major layout fracturing, overlay, and hard mask issues.

• Line edge roughness in resist development and its change over correlation lengths of 100 nm may impose a fundamental lithography limit.

• Both the statistical variations in doping and geometry will result in variations among devices.

• Enhancement of transistor performance by strained materials will likely result in pattern dependent stress variations and pattern dependent variation in diffusivity of dopants due to defects created by stress relaxation.

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Advice on An ApproachThe personal opinion of a technologist in one of our FLLC

companies is that there are two ways to do small feature control:

1) Do it with big R&D, by actually putting in large pilot lines withcutting edge (read expensive) equipment and create integration

practices that result in good control. This I clearly have opinions on how to do, but doesn't really apply to FLCC project.

2) Have a group of smart, experienced scientists like yourself cometogether and define how they can innovate without creating the

more industrial and exhaustive environment described in #1 above.

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Key Questions for FLCC

• Is there academic content to DFM?

• How do students work with our manufacturing, equipment, and software supporters and 60 start-ups on an industry wide win-win-win-win-win basis?

• How do we deal in an open university with the proprietary nature of sensitive design, process, compensation, and yield data?

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Key Answers for FLCC• Let’s find the academic content in DFM?

• Lets find a win-win-win-win-win approach for students to work on an industry wide basis with our manufacturing, equipment, and software supporters, and 60 start-ups.

• Let’s make one of the research goals to prototype new alternatives to deal with the proprietary nature of sensitive design, process, compensation, and yield data.

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Great FLCC/SRC/DARPA starting position• Feature Level Compensation and Control is already a subset of

DFM• The breadth of FLCC covers most of the processes• Our models provide understanding and efficient

characterization • Our test-pattern and validation experiments are of interest

industry wide• The “Collaborative platform for DFM” pioneered by Wojtek

Poppe is recognized as a first in the DFM field.• Our 2D maximal impact test patterns go where design rules

don’t reach• Our Pattern-Matcher software supports unique fast-CAD ideas

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Collaborative Platformfor DFM

Collaborative Platformfor DFM

Circuit Simulation

Collaborative Platform for DFM

Transistor Modeling Process Simulation

Validation Experiments

Manufacturing

Design

WojtekPoppe

SRC/DARPA

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Collaborative Platform for DFM: Philosophy

Communication is the Issue• Many domains of expertise and viewpoints

– Process/Metrology/Device/Circuit/CAD

• Moving information between domains is as important as the depth of understanding within one domain

• The university atmosphere is a great venue for creative ideas on DFM– Process/Metrology/Device/Circuit/CAD

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Parametric Yield Simulator (PYS)

Module 1Processing

Module 3Circuit

Module 2Device

BSIM transistor

model

Circuit Simulation across characterized process window

Non-rectangular transistors

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Verification Opportunity at Cypress SemiconductorControl of LithoControl of Mask and OPC

Different Illumination (Annular, Quasar, NA, Sigma)

Metal Active Contact

Corner Poly

Center Poly

Quasar OPC

Annular OPC

Metal Active Contact

Corner Poly

Center Poly

Metal Active Contact

Corner Poly

Center Poly

Quasar OPC

Annular OPC

Programmed defocus

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Characterizing All Sources of Process Variations

5BCAM

Leff Spatial Variation Decomposition

= +

Average Wafer Scaled Mask Errors Across-Field Variation

Across-Wafer Variation

+ + +

Die-to-Die Variation “Random” Variation

Paul Friedberg 2005

Bias features appropriately in Calibre.

Characterize your process

Characterized CD distribution can stem from any process variation. Multiple simulations can be done for various dies across the wafer.

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Liang Teck Pang’s Ring Oscillator Test Chip

Quantify the effects of layout, Vdd and body biasing on variations by measuring ring oscillator frequencies and leakage current.

1a 2a 3a 4a 5a 6a

M1

1b 2b 3b 4b 5b 6b

Dummy polySi

90nm CMOS16 columns and 10 rows(160 tiles) of each layout configurationDie size around 1.5mm x 1.2mm (incl. I/O pads)Ring Oscillator frequency and leakage current measurement results for 1 chip at Vdd=1V and 0.81V

Die photo of testchip

Previous experiments using ST’s 90nm flow showed various types of systematic variation. Cypress experiments to identifying the major causes.

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Collaborative Platform for DFM: StrategyLeverage what is Known• Much of the Device and Circuit Variation can be

attributed to a Few Physical Causes– Takes only a few key parameters

• Local effects are not only Correlated Laterally but they are even Interdependent Laterally– There is action where design rules don’t reach

Leverage Software Know How• Perturbational Pattern-Matching methods are Fast and

accurate– Real-time assessment during design likely possible

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Going Where Design Rules Don’t Reach

Example: proximity effect influence function for coma. • Function is about 5 feature sizes in diameter and easily reaches across

cell or compaction boundaries. • By computing influence functions for diffraction limited proximity Z1,

Defocus Z4 and Coma Z7 it is possible to quickly assess image changes through the process window and along a scanner slit.

• Similar patterns exist at a mm scale for assessing flare and CMP.

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Leverage Prior SRC IP from 2004: Pattern Matching Methods for Linking TCAD and EDA

LAYOUTPATTERN

SPLAT

AB-CAD

.gds

ExtractedMatch Region

• Prototype system with extraction to TCAD for aberrations, flare, CMP, reflective notching, etc.

• Validation with perfect SPLAT correlation

• New data structures and algorithms give 400X OPC speed

Frank GennariSRC PhD 2004

3mmx3mm abacus IC

Delta E vs. Match Factor

y = 0.2855x + 0.0037R2 = 0.9831

-0.2

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

-0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6

Match Factor

SPLA

T de

lta E

(Sim

ulat

ed)5.6GB hierarchical layout with OPC,

>100M rectangles/polygons, two matching test patterns, at every corner:17 min on a 2.8 GHz desktop (with file reading) and 1.3 GB RAM

Gennari SPIE 04

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Process Aware EDA Toolkit• New SRC Grant supporting 2 students for 3 years• Goes the next level in communication from

Collaborative Platform for DFM to Real-Time Assessment and Feedback During Design

• Strategy– Use only a few key physical parameters– Use lateral influence functions to go where design rules

don’t reach– Utilize the Speed of Pattern Matching and Perturbational

Methods

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UCB DFM-CAD TEAM

Robustness Metric and

Drag and Drop Hot-Spot Fixer

Lynn WangWojtek Poppe

Juliet HolwillEric Chin

CrosstalkJae-Seok Yang

Interconnect Delay

Lateral Image Interactions and Placement

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Leverage Current FLCC OpportunitiesTarget more in the DFM area with the resources we

have to attract additional long term future funding.• Understand relative contributions to device variations

from doping variations and feature geometry variations.

• Link CMP variations and pattern transfer feature size change including roughness contributions non-linear resistance changes in interconnect.

• Global non-uniformity in plasma etching possibly due to chamber flow, pattern global and micro loading.

• Industry-wide (universal) test patterns for calibration of OPC and PPC models.

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Recommended Action for Higher Leverage

Form a new operational structure that enhances and demonstrates the inter-area contributions among all projects to our theme of feature level compensation and control.

• This might be a student task force that summarizes likely physical causes and novel test patterns for distinguishing and quantifying them.

• We would include these patterns on test masks for experiments in the university and at Cypress and then interpret the results.

• We would also make the layouts and analysis descriptions available on the web to participating companies.

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Possible New Year 4 Proposal Ideas• No-fault assurance: The ability to prescreen complete chip layouts for

potential effects visa via the richness of a test pattern set. It is likely possible that this testing could be carried out by with SRC software by a third party or by a “virtual third party PC.” Alternatively we could find mathematically complete and physically reasonable test vectors and play them against both the test and chip layouts.

• System Information View of Characterization: We could develop aninformation systems approach to assess predictability of feature printability given the limited number and fuzziness of SEM measurements in parameter calibration. SEM to database comparisons might be possible by collaborating with AMD and or vendors on comparison of SEMs of printed patterns and layout.

• Understand the generation of defects from patterning and thermaltreatments of strained silicon layers and their role in dopant and Gediffusion.

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Conclusion

• DFM is a communications issue and moving information across boundaries is as important as the depth of understanding within the domains.

• We have expertise in all aspects of the DFM problem including process, device, circuits, CAD and technology CAD.

• Our science and instrumented apparatus in FLCC give us much more telling view into the physics than is available on production equipment.

• We have an important first that our students and their peers have their arms around the entire problem.

• Can we create strong win-win-win-win-win ideas that industry ‘Cannot afford not to fund”?