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------------------------------------------------------------------------------------ Company:-- Engineer:---- Create Date: 23:50:23 04/08/2013-- Design Name:-- Module Name: flash5 - Behavioral-- Project Name:-- Target Devices:-- Tool versions:-- Description:---- Dependencies:---- Revision:-- Revision 0.01 - File Created-- Additional Comments:------------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;

entity flash isPort ( Bus2IP_clk : in STD_LOGIC;

Bus2IP_reset : in STD_LOGIC;Bus2IP_cs : in STD_LOGIC;Bus2IP_rnw : in STD_LOGIC;FLASH_BYTE : in STD_LOGIC;

FLASH_ADDR : in STD_LOGIC_VECTOR (17 downto 0);FLASH_DATA_IO : inout STD_LOGIC_VECTOR (15 downto 0);Bus2IP_Data : in STD_LOGIC_VECTOR (15 downto 0)FLASH_CE: out STD_LOGIC;FLASH_OE: out STD_LOGIC;FLASH_WE: out STD_LOGIC;

);end flash;

architecture Behavioral of flash istype statetype is (idle,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15);signal state_vector,nextstate: statetype;begin

process(Bus2IP_clk ,BUS2IP_reset)beginif(BUS2IP_reset= '0') then

state_vector

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elseFLASH_OE

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FLASH_OE

nextstate